What is Functional Safety?

Transcription

1 Transportation and Safety Microcontrollers from Texas Instruments September 2012

2 What is Functional Safety? Safety is freedom from unacceptable risk of physical injury or of damage to the health of people, either directly, or indirectly as a result of damage to property or to the environment. Functional safety is part of the overall safety that depends on a system or equipment operating correctly in response to its inputs. Example: over-temperature protection device, using a thermal sensor in the windings of an electric motor to deenergise the motor before they can overheat Source: iec

3 Safety Failures and their Causes Failures in a functional safety system can be broadly classified into two categories: Systematic and Random failures Failures Systematic Failures Systematic Result from a failure in design or manufacturing Often a result of failure to follow best practices Random Rate of systematic failures can be reduced through continual and rigorous process improvement Random Failures Result from random defects inherent to process or usage condition Rate of random failures cannot generally be reduced; focus must be on the detection and handling of random failures in the application. Note: Software failures are considered to be systematic 3

4 Functional Safety vs. Quality/Reliability High quality and reliability does not guarantee safety. Methods to ensure quality and reliability have high overlap to methods used to manage systematic safety failures. Zero DPPM efforts Safe Launch programs Requirements to manage safety of random hardware failures in application typically do not overlap quality and reliability requirements. 4

5 Safety Integrity Levels SIL- Demand Mode SIL- Continuous Mode Closed-Loop view of Safety life cycle Source: EXIDA

6 Hercules TM Safety Microcontrollers New Product Overview

7 Hercules TM MCUs make the world a safer place Electronics are proliferating in safety-critical applications EN (railway) DO-254 DO-178B (aerospace) IEC (medical equipment) IEC (process industry) TM Hercules MCU IEC (furnaces) IEC (nuclear power stations) IEC ISO (machinery) IEC (safety) ISO (automotive) Hercules MCUs provide developers of safety-critical applications: Protection against random and systematic failures Headroom for application differentiation Simplified development and system certification 7

8 Typical Safety System Concept MCU MCU Safety = + 2x MCU MCU FPGA Safety = + 1x MCU + FPGA MCU ASIC Safety = + 1x MCU + ASIC TI Hercules Safety MCU Solution = 8

9 Hercules ARM Cortex Safety MCU Applications Aerospace & Railway Industrial Communications Gateway Industrial Motor Control Avionics / Autopilot Manufacturing / Robotics Anti-Skid Control Wind Power Motor Control Automotive Industrial Automation / PLC Airbag Braking / Stability Control Sensor & Communications Gateway Solar Power Hybrid & Electric Vehicles Radar / Collision Avoidance (ADAS) Oxygen Concentrators Anesthesia Active Suspension Chassis / Domain Control Electric Power Steering Respirators Medical 9

10 TI Hercules TM MCU Platform ARM Cortex Based Microcontrollers (confidential until September 6 th ) Hercules Platform TMS470M TMS570 RM4x Value Line Transportation and Safety MCUs Transportation Applications Automotive Q100 Qualification -40 to 125 C Operation LIN, CAN Connectivity ISO26262 ASIL-B IEC SIL-2 Cortex-M to 100 DMIPS High Performance Transportation and Safety MCUs Transportation Applications Automotive Q100 Qualification -40 to 125 C Operation FlexRay, CAN Connectivity ISO26262 ASIL-D IEC SIL-3 Cortex-R over 280 DMIPs High Performance Industrial and Medical Safety MCUs Industrial Applications Medical Applications TMS Qualification -40 to 105 C Operation Ethernet, USB Connectivity IEC SIL-3 Cortex-R over 350 DMIPs 10

11 Exida Has Certified TMS570LS20216S IEC SIL3 Capable 11

12 Hercules Safety Documents Documents provided by TI some under NDA to assist in the safety certification process: Hercules TMS570/RM Device Safety Manual (SM) Details product safety architecture and recommended usage NDA NDA Safety Analysis Report Summary (SAR1) Summary of FIT rate and FMEDA at DEVICE level for IEC and ISO Detailed Safety Analysis Report (SAR2) Full details of all safety analysis executed down to MODULE level for IEC and ISO NDA Safety Case Report (SCR) Summary of compliance to IEC and/or ISO

13 Hercules MCUs are tailored for safety critical applications RM48 Cortex -R4F RM48x Safety Critical Industrial & Medical Up to 220MHz (>350 DMIPS) Up to 3MB Flash 337 BGA 144 QFP Lockstep Floating Point CPUs CPU & RAM BIST, RAM & Flash ECC,CRC IEC Dual 12-bit ADCs, 10/100 Ethernet, USB Host & Device, MibSPI, CAN, UART, I 2 C N2HET sub-10$ to $30 TMS S570 Cortex -R4F TMS570LS 31x/21x TMS570LS 20x/10x High Performance Transportation Safety High Performance Transportation Safety Up to 180MHz (>280 DMIPS) Up to 160MHz (>250 DMIPS) Up to 3MB Flash 337 BGA 144 QFP Up to 2MB Flash 337 BGA 144 QFP Lockstep Floating Point CPUs CPU & RAM BIST, RAM & Flash ECC, CRC IEC & ISO & AEC Q100 Qual Dual 12-bit ADCs, 10/100 Ethernet, FlexRay, MibSPI, CAN, LIN, UART, I 2 C N2HET Lockstep Floating Point CPUs with over CPU & RAM BIST, RAM & Flash ECC, CRC IEC & AEC Q100 Qualification Dual 12-bit ADCs, FlexRay, MibSPI CAN, LIN, NHET $15 to $20 sub-10$ to $16 TMS470M Cortex -M3 TMS470MF 066x TMS470MF 042x/031x Transportation & Gen Purpose Safety Transportation & Gen Purpose Safety 80MHz (~100 DMIPS) 80MHz (~100 DMIPS) 640K Flash 100 QFP Up to 448K Flash 100 QFP CPU & RAM BIST, RAM & Flash ECC, CRC 10-bit ADC, MibSPI, CAN, LIN, UART, HET AEC Q100 Qualification CPU & RAM BIST, RAM & Flash ECC, CRC 10-bit ADC, MibSPI, CAN, LIN, UART, HET AEC Q100 Qualification $6 $ $5

14 Hercules Safety MCU Roadmap Industrial & Medical RM48L9x 2*R4F LS 3MB, 256kB 220MHz Production 4Q 2012 RM48L5x 2MB, 192kB ETHERNET Production 3Q 2013 RM46x 2*R4F LS 1.25MB, 192kB 220MHz RM42x 2*R4 LS 384kB, 32kB 100MHz Production 3Q 2013 ETHERNET QEP QEP / PWM Safe Motor Control Industrial Automation Safe Connectivity Medical Automotive & Transporta ation TMS570LS202S 2*R4F LS 2MB, 160kB 160MHz TMS570LS102S 1MB, 160kB TMS470MF066S ARM Cortex -M3 640kB, 48kB 80MHz TMS470MF042S 448kB, 24kB TMS470MF031S 320kB, 16kB TMS570LS31x 2*R4F LS 3MB, 256kB 180MHz Production 4Q 2012 TMS570LS21x 2MB, 192kB ETHERNET More memory options New peripherals Smaller memory options New peripherals Lower cost Stability Control Power Steering Vehicle Electrification ABS Power Steering Passive Safety CAN Communication Production Sampling Development Production/Sample Date Lockstep CPUs SIL ASIL-D 14

15 Hercules TMS570 Safety MCU Roadmap Production Sampling Development Future TMS570 HIGH NEXT Higher Performance More Memory New Peripherals Lockstep; IEC61508 SIL support planned TMS570LS31x 2*R4F LS 3MB, 256kB 180MHz TMS570LS202S 2*R4F LS 2MB, 160kB 160MHz TMS570LS102S 1MB, 160kB TMS570LS21x 2MB, 192kB ETHERNET Production 4Q 2012 TMS570LS NEXT More Memory Options New Peripherals TMS570LS VALUE Smaller Memory Options Lower Cost 15

16 High Performance Cortex-R4F floating-point CPU ARM v7r Cortex TM ISA fully backward Compatible to ARM7/9/11 Up to 220 MHz CPU Clock Speed Fast MULT, DIV, and SQRT enables modelbased control; simplifies algorithm implementation Lockstep CPUs: Single core programming model second core checks the first. ARM Cortex -R4F 220 MHz Supports ARM, Thumb and Thumb-2 instructions Single / double precision IEEE 754 floating-point Floating point and integer instructions operate in parallel 8 region memory protection Broad ARM IDE/Compiler Support: CCS, KIEL, IAR, etc Over 350 DMIPS of performance High performance floating point ARM-based: broad industry adoption Superscalar, SIMD, 8 stage pipeline delivers 1.6 DMIPS/MHz Scalable ARM Based Solutions from TI: Stellaris, TMS470M, TMS570 & Sitara 16

17 Hercules Cortex-R4F MCU safety features CPU Self Test Controller requires little S/W overhead ECC for flash / RAM / interconnect evaluated inside the Cortex R4F Safe Island Hardware diagnostics (RED) Blended HW diagnostics (BLUE) Non Safety Critical Functions (BLACK) Logical / physical design optimized to reduce probability of common cause failure Dual Core Lockstep - Cycle by Cycle CPU Fail Safe Detection Parity on all Peripheral, DMA and Interrupt controller RAMS Parity or CRC in Serial and Network Communication Peripherals ARM Cortex - R4F ARM Cortex - R4F Fail Safe Detection Memory Flash w/ ECC RAM w/ ECC Flash EEPROM w/ ECC Calibration JTAG Debug Power, Clock, & Safety OSC PLL POR CRC PBIST/LBIST ESM RTI/DWWD Memory Interface Enhanced System Bus and Vectored Interrupt Module Serial Interfaces Network Interfaces Embedded Trace DMA Dual ADC Cores External Memory Dual High-end Timers GIO Memory BIST on all RAMS allows fast memory test at startup On-Chip Clock and Voltage Monitoring Error Signaling Module w/ External Error Pin IO Loop Back, ADC Self Test, Dual ADC Cores with shared channels 17

18 Safety in hardware maximizes performance & speeds development CPU Usage (%) Safety software App. software App. software Up to 30% Headroom Significantly reduce safety software overhead with integrated safety features Improve time to market Spend less time developing complex safety software Spend less time proving your CPU safety solution to auditors, leaving more time to differentiate Safety manual Complete guide to developing a safety solution using a Hercules Safety MCU Competitive MCU Hercules MCU

19 TMS570LS31x ARM Cortex -R4F Floating Point Microcontroller Performance / Memory Up to 180 MHz ARM Cortex-R4 w/ Floating Point Up to 3MB Flash and 256KB Data SRAM 64KB Data Flash (EEPROM Emulation) w/ ECC 16 Channel DMA Features Safety Dual CPU s in Lockstep CPU Logic Built in Self Test (LBIST) Flash & RAM w/ ECC (w/ bus protection) Memory Built-in Self Test (PBIST) Cyclic redundancy checker module (CRC) Peripheral RAMs protected by Parity Communication Networks 10/100 EMAC (optional) FlexRay (optional) with 8KB RAM and dedicated DMA 3 CAN Interfaces (3x64 messages) 3 Muti-Buffered SPI (128 buffers/6cs each) + 2 Std. SPI 2 UART one with LIN 2.1 support 1 I2C Enhanced I/O Control 2x High End Timer Coprocessor (NHET) Up to 40 pins plus 6 monitor channels All pins can be used as Hi-Res PWM or Input Capture Dedicated DMA for HET 2 x12-bit Muti-Buffered ADC 24 total input channels (8 shared) Continuous Conversion Mode Calibration and Self Test 16 GIO w/ External Interrupt Capability Targeted Applications High End IEC61508 and ISO26262 Safety Applications Chassis Domain Control High End ESC ARM Cortex ARM - R4F Cortex - 160MHz R4F Up to 180MHz Fail Safe Detection Memory 3MB Flash w/ ECC 256 KB RAM w/ ECC 64KB Data Flash EEPROM w/ ECC Calibration JTAG Debug Embedded Trace DMA Power, Clock, & Safety OSC PLL PBIST LBIST POR CRC RTI/DWWD Memory Interface SDRAM EMIF Enhanced System Bus and Vectored Interrupt Module Serial I/F MibSPI1 128 Buffers; 6 CS MibSPI3 128 Buffers; 6 CS MibSPIP5 128 Buffers; 6 CS SPI2 (2CS) SPI4 (1CS) Network I/F 10/100 EMAC 2 ch FlexRay 8K Message RAM 3x CAN (64mb) 2x UART (LIN1) I2C ADC MibADC1 64 Buffers 12-bit, 16ch (8ch shared) MibADC2 64 Buffers 12-bit, 16ch (8ch shared) Timers / IO 2x High End Timer (NHET) 160 words GIOA/INTA (8) GIOB/INTB (8) Packages: LQFP: 144pin -20x20; nfbga: 337 pin-16x16, 0.8mm; -40 to 125 C Temperature Range Note :Above reflects max configuration of each module some functions are multiplexed. 19

20 RM48x Block Diagram Dual Core Lockstep ARM Cortex-R4F w/ Floating Point Performance / Memory Up to 220 MHz ARM Cortex-R4 w/ Floating Point Up to 3MB Flash and 256KB Data SRAM 16 Channel DMA Features Safety Dual CPU s in Lockstep CPU Logic Built in Self Test (LBIST) Flash & RAM w/ ECC Memory Built-in Self Test (PBIST) Cyclic redundancy checker module (CRC) Peripheral RAMs protected by Parity Communication Networks 10/100 EMAC USB: Host and Device 3 CAN Interfaces 3 Muti-Buffered SPI s+ 2 Std. SPIs 2 UARTs 1 I2C Enhanced I/O Control 2x High End Timer Coprocessor (NHET) Up to 40 pins plus 6 monitor channels All pins can be used as Hi-Res PWM or Input Capture Dedicated DMA for HET 2 x12-bit Muti-Buffered ADC 24 total input channels Continuous Conversion Mode Calibration and Self Test 16 Dedicated GIO pins All pins are External Interrupt Capable Targeted Applications Industrial Safety and Control Critical Care Medical RM48x ARM Cortex ARM - R4F Cortex - 160MHz R4F Up to 220 MHz Fail Safe Detection Memory 3MB Flash w/ ECC 256 KB RAM w/ ECC 64KB Data Flash EEPROM w/ ECC Memory Protection JTAG Debug Calibration & Trace DMA Power, Clock, & Safety OSC PLL PBIST LBIST POR CRC RTI/DWWD Memory Interface SDR / ASYNC EMIF Enhanced System Bus and Vectored Interrupt Module Serial I/F MibSPI1 128 Buffers; 6 CS MibSPI3 128 Buffers; 6 CS MibSPIP5 128 Buffers; 6 CS SPI2 (2CS) SPI4 (1CS) Network I/F 10/100 EMAC USB 1.1 Host & Device 3x CAN (64mbx) 2x UART (LIN1) I2C ADC MibADC1 64 Buffers 12-bit, 24ch (16ch shared) MibADC2 64 Buffers 12-bit, 16ch (16ch shared) Timers / IO 2x High End Timer (NHET) 160 words NHET1-32 ch NHET2 14 ch GIOA/INTA (8) GIOB/INTB (8) Packages: LQFP: 144pin -20x20; nfbga: 337 pin-16x16, 0.8mm; -40 to 105 C Temperature Range Note :Above reflects max configuration of each module some functions are multiplexed. 20

21 RM46x Block Diagram Dual Core Lockstep ARM Cortex-R4F w/ Floating Point Performance / Memory Up to 220 MHz ARM Cortex-R4F w/ Floating Point Up to 1.25MB Flash and 192KB Data SRAM Dedicated 64KB Data Flash (EEPROM Emulation) 16 Channel DMA Features Safety Dual CPUs in Lockstep CPU Logic Built in Self Test (LBIST) Up to 12 CPU MPU regions Flash & RAM w/ ECC (w/ bus protection) Memory Built-in Self Test (PBIST) Cyclic redundancy checker module (CRC) Peripheral RAMs protected by Parity Communication Networks 10/100 Ethernet MAC w. MII/RMII, MDIO Option* USB 2.0 Full Speed: Host and Device Option * 3 CAN Interfaces 5 SPI (3 Multi-Buffered) 2 UART, 1 I2C Enhanced I/O Control 2x High End Timer Coprocessor (N2HET) w/dma Up to 40 pins plus 6 monitor channels All pins can be used as Hi-Res PWM or Input Capture Motor Control Timers 7x etpwm (14 ch), 6x ecap, 2x eqep 2 x12-bit Multi-Buffered ADC 24 total input channels (16 shared) Calibration and Self Test Up to 101 GPIO pins (16 dedicated) Targeted Applications General IEC61508 Safety Applications Industrial, Medical, Energy ARM Cortex ARM - R4F Cortex - 160MHz R4F Up to 220MHz Fail Safe Detection Memory 1.25MB Flash w/ ECC 192KB RAM w/ ECC 64KB Data Flash EEPROM w/ ECC Calibration JTAG Debug DMA Power, Clock, & Safety OSC PLL PBIST LBIST POR CRC RTI/DWWD Memory Interface SDRAM EMIF Enhanced System Bus and Vectored Interrupt Module Serial I/F Network I/F ADC MibSPI1 128 Buffers; 6 CS MibSPI3 128 Buffers; 6 CS MibSPIP5 128 Buffers; 6 CS SPI2 (2CS) SPI4 (1CS) USB * Host & Device CAN1 (64mb) CAN2 (64mb) CAN3 (64mb) 2x UART (LIN1) I2C 10/100 EMAC* MibADC1 64 Buffers 12-bit, 24ch (16ch shared) MibADC2 64 Buffers 12-bit, 16ch (16ch shared) Timers / IO 2x High End Timer (N2HET) 160 words etpwm (14ch) ecap (x6) eqep (x2) GIOA/INT(16) Packages: LQFP: 144pin -20x20; nfbga: 337 pin-16x16, 0.8mm; -40 to 105 C Temperature Range Note :Above reflects max configuration of each module some functions are multiplexed.

22 RM42x Block Diagram Dual Core Lockstep ARM Cortex-R4 Microcontroller Performance / Memory 100 MHz ARM Cortex-R4 384KB Flash and 32kB Data SRAM Dedicated 16kB EEPROM Emulation Flash (4x4k) Features Safety Dual CPU in Lockstep CPU Logic Built in Self Test (LBIST) Up to 12 CPU MPU regions Flash & RAM w/ ECC (w/ bus protection) Memory Built-in Self Test (PBIST) Cyclic redundancy checker module (CRC); Peripheral RAMs protected by Parity Communication Networks 2 CAN Interfaces 3 SPI (1 Multi-Buffered) 1 UART Enhanced I/O Control High End Timer Coprocessor (NHET) Up to 19 channels 12-bit Multi-Buffered ADC (3.3V) 16 total input channels Continuous Conversion Mode Calibration and Self Test Motor Control Timers 2x eqep Up to 45 GPIO pins (8 dedicated) Targeted Applications General IEC61508 Safety Applications Industrial, Medical, Energy RM42x ARM Cortex ARM - R4F Cortex - 160MHz R4 100 MHz Fail Safe Detection Memory 384 KB Flash w/ ECC 32 KB RAM w/ ECC 16KB emue2 PROM Memory Protection JTAG Debug Power, Clock, & Safety OSC PLL PBIST LBIST Enhanced System Bus and Vectored Interrupt Module Serial I/F Network I/F ADC / IO MibSPI1 128 Buffers (4CS) 2 x SPI (1CS) CAN1 (32mbx) CAN2 (16mbx) 1x SCI/UART MibADC 64 Buffers 12-bit, 16ch GIOA/INTA (8) Package: LQFP: 100pin (14 x 14mm) -40 to 105 C Temperature Range POR CRC RTI Timers High End Timer 128 words up to 19ch eqep (x2)

23 1oo1D Dual Core Safety Concept Unique design to reduce common cause failures (βic) Second CPU mirrored and rotated Minimum distance 100µm between CPUs Cycle delayed lockstep Guard ring per CPU Duplicated clock tree per CPU Output + Control Cycle Delay Dedicated Power Ring CCM Self Test Compare Error > 100um CPU Compare Module Self-test capability Self-test error injection/error forcing Output error injection Cycle Delay Input + Control 23

24 1oo1D Dual Core Lockstep Advantages Advantages of lockstep CPUs vs. software and multi-core based solutions Faster fault detection. Enables safety in systems with tight control loop timing. Better fault coverage. Hard, transient, and AC fault types can be detected. Little to no performance impact. Full CPU performance available for application tasks rather than CPU diagnostics. Minimal memory impact. Flash and SRAM used for application rather than CPU diagnostics. Easy integration. Improve time to market without need to integrate complex software. Proven, easy to justify diagnostic coverage. Spend less time proving your CPU safety solution to auditors leaving more time to develop your application. 24

25 Flash / RAM ECC Protection Cortex-R4F 64 Inst. 8 Stage Pipeline 64 Data 32 Data Bits 4 ECC Bits Flash 8 ECC Error ECC Logic 8 ECC RAM 32 Data Bits 4 ECC Bits ECC evaluated in the Cortex R4F CPU Single Bit Error Correction and Double Bit Error Detection ECC evaluated in parallel to processing data/instructions No latency or performance impact Protects Busses from CPU to Flash and RAM 25

26 Error Signaling Module (ESM) ESM Errors for Group 1 INTEN INTLVL Low Level Interrupt Handling High Level Interrupt Handling To Interrupt Manager Errors for Group 2 Errors for Group 3 ERROR SIGNAL CONTROL LOW TIME COUNTER PRELOAD LOW TIME COUNTER nerror pin 26

27 Clock Monitoring External clock prescaler (ECLK) Allows external monitoring of CPU clock frequency Configurable pin (GIO or ECLK) Oscillator monitor Detects failure if oscillator frequency exceeds defined min/max thresholds Selectable hardware response on oscillator fail Reset device Switch to internal low power oscillator (LPO) clock source FMzPLL slip detector Indicates PLL slip if phase lock is lost Selectable hardware response on PLL slip Reset device Switch to internal low power oscillator (LPO) clock source Switch to external oscillator clock source LPO Input from Oscillator FMzPLL CLK Signal to CLK Control Module Bypass on Slip Slip Detector BPOS BPOS Reset on Slip ROS To Device Reset PLLMUL 27

28 Voltage Monitor Supply Voltage Monitor (VMON) Holds reset until core and I/O rails in expected range (removes power sequencing requirements) Asserts reset if core or I/O supply exceeds defined min/max thresholds Asserts reset when core supply is below specified min voltage and asynchronously sets all I/O pins to high impedance mode 28

29 Dual Analog to Digital Converters Dual12-bit ADC Cores: Analog channels shared between the 2 cores for safety critical conversions/comparison (1oo2 safety redundancy) Internal ADC reference voltages can be used to check converter functionality. Self Test Mode enables in application detection of opens/shorts on ADC inputs ADC calibration logic can improve accuracy or be used to detect drift between multiple test results. AD1EVT AD1IN[7..0] ADSIN[15..8] VccAD VssAD VrefHi VrefLo AD2IN[7..0] AD2EVT Self-Test & Calibration MibADC1 MibADC2 Self-Test & Calibration To Peripheral Bus To Peripheral Bus 29

30 NHET: High End Timer Co-Processor User Programmable 128 word instruction RAM with Parity Dedicated DMA (HTU) from NHET to Data Ram 32 I/O pins for complex or typical timing functions - capture, compare, PWM, GPIO Conditional program execution based on pin conditions and compares Multiple 25-bit virtual counters for timers, event counters, and angle counters Host interface Timer RAM Execution Unit Input/ Output Unit CPU wait control Shadow registers Program RAM Address Register Interrupt Control Operation Control Address/Data Bus Global & prescale control register Control RAM Prescaler Instruction Register Compare 32 High Resolution Channels Synchronizers 32 I/O Channels 32 bit ALU Data RAM Register A, B, T I/O Control Register Frees CPU MHz Supports typical/complex functions Simplified development environment Pulse Width Modulation Single, multi channel PWMs PWM with duty cycle update PWM with sync/async update Phase shift PWM's Symmetrical & asymmetrical PWM with deadband Timer/Counter Functions Frequency Modulated Output Pulse width count Time stamp Event counter Pulse accumulator Multi-resolution scheme Freq / Pulse Measurements Pulse and period measurement (same channel) Quadrature Decoding Special Functions SPI Emulation TFT Display Timing

31 ADINx ADIN0 MibADC Multi-Buffered ADC 16-1 Input Mux Self-Test & Calibration Cell Cont trol Signa alsv VCCAD Sequencer & ADC Result s Memory Interface Controller Peripheral Bus Interface Peripheral Bus VSSAD ADREFHI ADREFLO 12-bit Successive Approximation ADC End of Conv ADC Results Memory FIFO 12-bit Result Features 12bit resolution SAR in each MibADC. Absolute accuracy 0.1% Sample rate: 1.67 Mega-samples/second (x 2 using 2 MibADCs) 24 total channels (MibADC1=8, MibADC2=8, Shared=8) 64 result FIFO Buffer RAM with Parity protection on each MibADC Continuous multi-channel or single-channel conversion modes Three conversion groups w/ programmable sample times DMA capability from FIFO Buffer to Data RAM Power-down mode to conserve power consumption Embedded self-test & calibration for diagnostics 31

32 TMS570 Evaluation and Development Kit Overview Evaluation TMDX570LS20SUSB ($79) Low Cost TMS570 Evaluation Kit USB Powered On Board USB XDS100v2 JTAG Debug On Board SCI to PC Serial Communication Access to Select Signal Pin Test Points LEDs, Temp Sensor, Light Sensor and CAN transceiver QFP Packaged MCU $79 Developme ent TMDX570LS20SMDK ($695) - Full Featured TMS570 Development Kit Separate CPU Card and IO Card On Board USB XDS100v2 JTAG Debug External high speed emulation via JTAG TRACE pads for ETM/RTP/DMM FlexRay/CAN/LIN Transceivers Color Touch Screen TFT LEDs, Temp Sensor, Light Sensor BGA Packaged MCU $695 Software Included in Each Kit: CCStudio v4.x IDE: C/C++ Compiler/Linker/Debugger HALCoGen Peripheral Driver Generation Tool CCS and nowflash TM Flash Programming Tools HET GUI/Simulator/Assembler Demo Project/Code Examples 32

33 Hercules TM Development Kits RM48 Evaluation and Development Developme ent Evaluation TMDXRM48USB ($79) Low Cost RM48 Evaluation Kit USB Powered On Board USB XDS100v2 JTAG Debug On Board SCI to PC Serial Communication Access to Select Signal Pin Test Points LEDs, Temp Sensor & Light Sensor Accelerometer CAN transceiver TMDXRM48HDK ($199) - Full Featured RM48 Development Kit On Board USB XDS100v2 JTAG Debug External high speed emulation via JTAG TRACE pads for ETM/RTP/DMM LEDs, Temp Sensor & Light Sensor CAN Transceivers RJ45 10/100 Ethernet Interface USB-A Host Interface USB-B Device Interface $79 $199 Software Included in Each Kit: CCStudio v4.x IDE: C/C++ Compiler/Linker/Debugger nowgen Peripheral Driver Generation Tool CCS and nowflash Flash Programming Tools HET GUI/Simulator/Assembler GUI Demo with Project/Code Examples 33 33

34 Hercules TM Software Tools IDEs (compilers & debuggers) Program/debug code using these IDEs: Code Composer Studio IAR Workbench KEIL µvision RTOS Support Real Time Operating System Support: SAFERTOS: High Integrity Systems µc/os: Micrium ThreadX: Express Logic:(planned) GUI-based Code Generation Tools and Other SW Tools Safety MCU Demos Safety Feature Highlight Ambient Light & Temperature Demo LED Light Show Maze Game Source Code Viewable via CCS PLL Calculators Easily configure the FMzPLL and FPLLs in the Hercules platform Phase Lock Loop modules. HET IDE Graphical Programming Environment Output Simulation Tool Generates CCS-ready software modules Includes functional examples from TI nowgen User Input on High Abstraction Level Graphical-based code generation Easy configuration Quick start for new projects Supports CCS, IAR & KEIL IDEs now ECC ECC Generation Tool Command line program for generating Error Correction Code for Hercules devices. Can be used in conjunction with CCSv4 now Flash Flash Programming Tool GUI and command line programmer for loading code into Hercules devices without an IDE. 34