envm in Automotive Modules MINATEC Workshop Grenoble, June 21, 2010 May Marco 28, 2009 OLIVO, ST Automotive Group

Transcription

1 envm in Automotive Modules MINATEC Workshop Grenoble, June 21, 2010 May Marco 28, 2009 OLIVO, ST Automotive Group

2 envm in automotive: Outline marketing requirements <= technology table design challenges testing challenges silicon results perspectives 1

3 Marketing requirements: comments low costs expected usage of ~consolidated technologies with limited devices few added process steps for NVM function optimized IPs architecture (with a unique technology) to cover all differentiators cut modularity, blocks re-use safety requirements no content corruption auto-test system (digital, analog, address decoding) security end-user is not supposed to modify protected zone (legal aspects!) at present: anti-hacking password mechanism tomorrow: HW + FW tricks required (~ smartcards like) reliability 0-ppm target, no matter the market segment, full Temp range ECC, well marginated designs, severe screening at testing each single customer return to be analyzed M10 OR recent Sep issue: 15 accessibility th 08 vs. security trade off 2

4 envm in automotive: Outline marketing requirements technology table <= design challenges testing challenges silicon results perspectives 3

5 envm: technology benchmark vs automotive Flash EEPROM PCM Split-FG Split - TFS Split- Monos ReRAM MRAM Cell type 1T-Nor 2T-Flotox 1T-1R 1.5T 1.5T 1.5T 1T-1R 1T-1R Cell size,f ~ ? granularity Sector (Page) Word (page) 1bit Page Page Page 1bit 1bit NVM techno impact HV+NVM HV+NVM NVM HV+NVM HV+NVM HV+NVM NVM NVM Endur Wr ? 10 17? cycled good good low good fair fair? fair Automotive Maturity code & data (code) data N.A. Code (data?) N.A. Code? N.A. N.A. Array Effic > 1MByte Med-high Low fair fair fair fair High? fair scalability HV limit HV limit good 1.5T? 1.5T? 1.5T? Good? Current? PROs Reliability, envm std Granularity Cost, Tacc, granularity Tacc, envm std Tacc Tacc Endurance cost Endurance CONs Design HV, density M10 OR complexity Sep 15 th 08 cycling New techno cycl New techno High current 4

6 envm Technology: comments envm scalability usually penalized vs. SRAM and digital envm is relatively dense, w.r.t. stand-alone NVM technology by mayor automotive player still based on FG SST split-gate code memory mainly, small-medium cut size simpler circuitry high volumes 1T-NOR code and data memory (including Page flash), medium-large cut size design complexity well partitioned between w/e controller (often programmable) and array most advanced techno node 90nm and, in developing phase, in 55nm node epcm? adding just a few back-end process steps, to digital techno 5

7 envm in automotive: Outline marketing requirements technology table design challenges <= testing challenges silicon results perspectives 6

8 envm in automotive: design challenges products low price -> simpler techno -> reduced number of basic components (gate oxides) for designing e.g. just LV trs (1.2V) and HV trs (<10V) available aggressive Tacc and 128(256)bit reading parallelism Low voltage requirements min Vdd_12 = ~1V min Vdd5 (Vdd3) = 2.7V, or lower automotive full temperature range at present -40C 150C (junction) tomorrow wider Temperature range forceability & observability of most of analog, nvm cells, digital nodes is a MUST due to stringent requests for a complete inspection of customer returns Low volumes, slow ramp-up production phase 7

9 envm 1T-NOR architecture: CODE & DATA TWO independent modules CTL-LOG HV handling (CODE) FLASH ARRAY (CODE) 512KB CTL-LOG HV handling (DATA) FLASH ARRAY (DATA,4x16KB) CTL-LOG is: engine for w/e ops. command interface programmable BIST engine M10 OR Sep 15low th 08 pin-count test interface 1T-NOR Flash architecture divided into three sub-blocks Flash array (memory design) HV handling (analog design) CTL-LOG (pure digital design) 8

10 envm in automotive design challenges: solutions [1] Few basic components available in low cost techno DK: specifically designed circuit solutions wide usage of trimmings (NVM fuses largely available) whenever analog circuits accuracy would ask for very large silicon area Aggressive Tacc and 128(256)bit reading parallelism: specific low voltage reading architecture, fast and noise immune accurate pre-silicon simulation environment on a netlist really representative of worst case layout conditions read timings carefully margined vs. P,V,T variations Low voltage requirements: dual-supply SoC system (1.2V; 3.3(5)V) re-used for LV (sensing) and HV (voltage multipliers) flash system partitioning careful lay-out and sizing of supply rails and related filter capacitors 9

11 envm in automotive design challenges: solutions [2] automotive full temperature range: analog and digital widely margined bitline leakage (1T-NOR killer) under control by accurate and stable analog & sensing environment specific proprietary w/e sequences and algos forceability & observability through a mini-set of SoC pins: CTL-LOG glued with SoC, inheriting all DFT techniques (fault loc) each NVM cell fully accessible (I/V char, stress application ) HV sub-blocks independently accessible Low volumes, slow ramp-up prod phase: anticipation work (characterization) on split lots mandatory to secure circuits specifications compliancy vs. technology variations, in advance vs. products proliferation 10

12 envm in automotive: Outline marketing requirements technology table design challenges testing challenges <= silicon results perspectives 11

13 envm in automotive: testing challenges test time of large (> 1MB) envm cuts may take several seconds per part parallel test is a must two NVM testing steps (pre/post bake) required SoC/uC digital testing strategy largely based on scanning technique at wafer sort test interface based on a few pins ATE usually not equipped with memory extension direct access to envm addr/data bus strongly discouraged envm BIST is required ATEs/Handlers dedicated to extended automotive Temp range seem being a pretty rare good Burn In required to secure screening for 0ppm PROs: several slow envm tests may be executed during BI CONs: really expensive test step 12

14 envm: Low Pin count test interface decreasing flash test content Test steps step1 step2 step3 increasing test pin count increasing test parallelism Flash Flash {N-Modules} {N-Modules} SRAM for programmable BIST code execution flash controller & Glue Logic pre-fetch buffer & ECC Flash & SRAM Test Interface eflash Boundary (supply domain) 13

15 envm in automotive: Outline marketing requirements technology table design challenges testing challenges silicon results perspectives <= 14

16 envm in automotive: 1T-NOR perspectives 1T-NOR cell scaled from 90nm into 55nm techno node evolutionary scaling nvm cell scaled keeping 90nm electric parameter ~unchanged HV transistors scale on lithography and profile optimization LV & SRAM from 55nm in-house digital techno main design challenges max cut: ~ x2 factor vs existing techno node improved area/speed trade-offs improved w/e algorithms highly enhanced safety & security requirements test time reduction 15

17 envm for automotive Thank You! 16