BM1680 Datasheet V1.0. Copyright 2017 BITMIAN TECHNOLOGIES LIMITED. All rights reserved.

Transcription

1 BM1680 Datasheet V1.0 Copyright 2017 BITMIAN TECHNOLOGIES LIMITED. All rights reserved.

2 Version Update Content Release Date V /10/25

3 CONTENT 1. Overview Key Features Typical System BM1680 Power Specs Power domains Power on sequence requirement Package & Ball Assignments Chip Package Ball Map BM1680 Signal Descriptions DDR Memory Interface Signals SerDes Interface Signals UART Interface Signals IIC Interface Signals SPI Flash Interface Signals JTAG Interface Signals Miscellaneous(MISC)Interface Signals Clock Interface Signals Power & Ground Signals Copyright 2017 BITMIAN TECHNOLOGIES LIMITED. All rights reserved.

4 1 Overview BM1680 is the accelerated ASIC solution for Deep Learning. All the popular CNN / RNN / DNN network topologies can be greatly accelerated when executing on BM1680 based acceleration platform. BM1680 is designed not only for network inference, but also optimized for network training. Equipped with total 64 NPUs in a single chip, BM1680 can provide 2TFLOPs peak performance for single precision floating point operation. The special designed NPU scheduling engine is the powerful heart which can supply extremely high bandwidth data flow efficiently to all the neuron processor cores. 32MB on chip memory resource enables best programing flexibility for performance optimization and data reuse. Through highly customized BMDNN Chip link technology, it provides stable, flexible, low latency link over the high speed SerDes which can make multiple BM1680 chips work together as a unified system that can provide greater processing capability. We also provide powerful software SDK to end-users. All the applications developed based on the mainstream deep learning frameworks (such as Caffe etc.) could be ported to BM1680 platform easily. For those users who are willing to get maximum optimization by deep customization, please contact us about FW level programing capability and guidance. The functional block diagram is shown below. Previous BM1680 or FPGA Next BM1680 NPU SUBSYSTEM MCU SUBSYSTEM CHIP_LINK SUBSYSTEM NPU0 NPU1 NPU2 NPU63 ARM CDMA HUB ITCM DTCM Data Hub MAC GLOBAL DMA NPU Schedule Engine VFP9 SERDES SYSTEM FABRIC DDR SUBSYSTEM DDR CH0 DDR CH1 DDR CH2 DDR CH3 BM1680 Peripheral SUBSYSTEM UART SPI IIC GPIO 72bit DDR 72bit DDR 72bit DDR 72bit DDR PC SPI Flash

5 2 Key Features Embedded Micro Controller 32b MCU 8KB L1 I Cache and D Cache With ITCM 512KB and DTCM 128KB JTAG debug support Co-processor: VPFv2 Boot method: Boot from SPI Flash and Boot from ITCM NP Subsystem 64 NPUs in a single chip 512KB local memory for each NPU Total computing power is 2TFLOPs for single precision. 64 NPUs in a single chip Memory Interface DDR3/DDR4 Highest data rate: DDR4(2667Mbps) / DDR3(1866Mbps) Memory data bus width: 64bit, 72bit (64bit + 8bit ECC) 4 independent DDR channels Rank number supported: Single CS# Maximum memory capacity up to 16GB SerDes SerDes max speed 12.5Gbps 40 SerDes lanes in total, grouped into 10 sets Reference clock: MHz or data rate/160 Special customized low latency MAC MCU in-cooperated for calibration purpose Chip Link Configurable link width. Support by channel disable Asymmetric downstream / upstream link width support Flow control back pressure Packet based data communication, max data payload size 8KB Typical system scenarios supported 1) Host enumerate chip and config chip ID 2) Host send FW and do MCU bootup 3) Host do register or memory access, all node chip 4) Host send task or do API call 5) FPGA Node DMA read from host to get image data and then distribute to all chip node. 6) BN layer data communication 7) Backward param gradient update Hardware mailbox for message exchange between host and chip. SPI Flash Controller

6 Synchronous, serial, full duplex transfer SPI mode 0,1,2,3 supported Configurable frame length 2 ~ 16 bits LSB or MSB First Tx/Rx Dual/Quad I/O read/write Flash supported Direct Memory Mapping Read supported Boot from SPI Flash support DMA transfer supported UART FIFO mode and register mode Fractional Baud rate generator; supports a wide range of target baud rates from 2400 to 230.4K Independent RX and TX DMA requests IIC Two-wire I2C serial interface Three speeds: 1) Standard mode (0 to 100 Kb/s) 2) Fast mode ( 400 Kb/s) 3) High-speed mode ( 3.4 Mb/s) Master or slave I2C operation 7- or 10-bit addressing Bulk transmit mode supported Handles Bit and Byte waiting at all bus speeds Electrical TSMC 28nm HPC+ Digital core voltage: 0.90V +/- 5% targeted Analog core voltage: 1.8V +/-5% I/O voltage: 1.8V +/-5% TDP: 41W when fully operated Operating temperature: 0~125 C

7 3 Typical System BM1680 provides great flexibility and scalability to build different scale of computing clusters to support end-user needs. Following functional block diagram illustrates the PCIE acceleration card typical structure based on BM1680: PCIE GEN3 Chiplink PCIE HOST Control Node0 Node1 DDR DDR The demonstrated system consists of 2 nodes. Each node is one BM1680 ASIC. Host control unit can be implemented with FPGA, it provides PCIE GEN3 link between host sever and the accelerator system. The host control unit and nodes are all connected through Chiplink. The data to be processed can be sent from host server to the acceleration card through the host interface downstream link. The processing result will be returned to the server through the upstream link. By this topology, more than two node chips could be linked together to form a bigger system if necessary. If more nodes need to be implemented on a single board, following factors needs to be taken into consideration: The form factor of the card. Power consumption and thermal dissipation the board can sustain. PCIE link bandwidth. Based on current computing power of BM1680 chip, use 4GB/s per node as PCIE bandwidth requirement for system design. For example, 2 node chip requires 8GB/s PCIE bandwidth. Each Node chip has DDR4 memory attached. The main purpose is to store network parameter and neuron data. The maximum memory capacity of each node is 16GB. ECC feature is provided which ensures server level data integrity for the system. The DDR4 memory is organized as 4 independent channels which can operate at 2667Mbps peak rate. Together with the high performance X86 or ARM server, the Sophon SC1 is suitable to be used to build Deep Learning Server like below.

8 Sophon SC1 High Performance X86 / ARM Server PCIE Sophon SC1 Sophon SC1 Sophon SC1 Deep Learning Server Most of the popular AI applications can be accelerated with this system, such as public security, transportation, intelligent retail, intelligence finance, intelligent video advertising and promoting, video content examination, radio and television video analysis, medical images, etc. The end application itself can be run on the high performance server, all the CNN/RNN/DNN workloads can be dispatched to the Sophon SC1 array. A complete host software stack should be run on the Server Machine. The host software stack provide interface between end-user s application and the acceleration hardware. The application API call will be served by the BM core and transferred to the acceleration hardware as requests through the PCIE Card Device driver reside on the host side. The Host Control Unit then convert these requests into Chiplink packets and send to corresponding node. The Sophon SC1 SDK is the powerful tools and libraries for designing, training, fine-tuning, and deploying deep learning algorithms and applications based on BM1680. It includes BMDNN, BMBLAS, BMCAFFE, and BMDEPLOY. For more detail, please refer to the Software SDK spec of BM1680.

9 4 BM1680 Power Specs 4.1 Power domains BM1680 power domains have been listed in the table below. The estimated current capability is also provided. Power/Ground Ref Ground Descriptions Current (ma) VAA_S VSS_S 1.5V power supply for analog 2500 VSS_S Ground VDD_P_T VSS_P_T 0.9V supply for PLL on the TOP 50 VSS_P_T Ground for PLL on the TOP VDD_P_B VSS_P_B 0.9V supply for PLL on the Bottom 50 VSS_P_B Ground for PLL on the Bottom VQPS_E VSS_IO_T High voltage (1.8V) for fuse programming 83 VDD_IO_T VSS_IO_T 1.8V supply for IO post-drive on the TOP 100 VSS_IO_T 0V supply for IO post-drive on the TOP VDD_IO_B VSS_IO_B 1.8V supply for IO post-drive on the Bottom 100 VSS_IO_B 0V supply for IO post-drive on the Bottom VREF_M Reference voltage of DDR 8 VDDP_M VSSP_M DDR postdrive power (1.2V for DDR4) 3000 VSSP_M DDR postdrive ground AVDD_M AVSS_M DDR analog power 1.8V 80 AVSS_M DDR analog ground VDD_C VSS_C 0.9v core power 40,000 VSS_C Core ground

10 4.2 Power on sequence requirement IO and Core: It is suggested to power up VDD_C before VDDIO SerDes: Core power VDD_C needs to be up earlier than VAA_S. Efuse: VQPS_E ramp-up slew rate MUST be slower than 1.8V/30us to avoid unintentional program. DDR:

11 5 Package & Ball Assignments 5.1 Chip Package The BM1680 use the FCBGA for the chip package design, figure 2-1 shows the package information. Figure 5-1 Package Information

12 5.2 Ball Map This chapter provides the signal/ball assignments (pinout) for the BM1680 of the deep learning processors. Figure 5-2 shows the BM1680 signal map. Figure 5-2 BGA Signal Map (Top View) The BM1680 signal map with the associated names is shown in six parts: Figure 5-3 shows the upper left sextant. Figure 5-4 shows the upper middle sextant.

13 Figure 5-5 shows the upper right sextant. Figure 5-6 shows the lower left sextant. Figure 5-7 shows the lower middle sextant. Figure 5-8 shows the lower right sextant A DDR3_DQS_N[1] DDR3_DQ[11] DDR3_DQ[13] DDR3_DQ[26] DDR3_DQ[28] VDDP_M DDR2_DQ[42] DDR2_DQS[5] DDR2_DQS_N[5] DDR2_DQS[7] B VSS_C DDR3_DQS[1] DDR3_DQ[9] VSS_C DDR3_DQ[27] DDR3_DQ[24] DDR2_DQ[44] DDR2_DQ[40] AVDD_M3 DDR2_DQS[6] DDR2_DQS_N[7] C DDR3_DQS[2] DDR3_DQS_N[2] DDR3_DQ[15] DDR3_DQS[3] DDR3_DQ[30] VSS_C DDR3_DM[3] DDR2_DQS_N[4] DDR2_DQS[4] DDR2_DQS_N[6] VDDP_M D DDR3_DQ[8] DDR3_DQ[10] VDD_C DDR3_DQS_N[3] DDR3_DQ[16] DDR3_DQ[31] DDR3_DQ[25] AVSS_M3 DDR2_DQ[47] DDR2_DQ[41] DDR2_DQ[45] E DDR3_DQ[19] DDR3_DM[2] DDR3_DQ[12] DDR3_DQ[14] VSS_C DDR3_DQ[20] DDR3_DQ[29] DDR2_DM[5] DDR2_DQ[46] VSS_C DDR2_DQ[43] F DDR3_DM[0] VSS_C DDR3_DQ[17] DDR3_DM[1] DDR3_DQ[18] DDR3_DQ[22] VREF_M3 VSS_C VDD_C DDR2_DM[4] DDR2_DM[6] G DDR3_DQS_N[0] DDR3_DQS[0] DDR3_DQ[3] VDD_C DDR3_DQ[21] DDR3_DQ[23] DDR2_DQ[38] DDR2_DQ[34] VSS_C DDR2_DQ[33] DDR2_DQ[49] H DDR3_DQ[4] VDDP_M DDR3_DQ[2] DDR3_DQ[1] DDR3_DQ[5] VSS_C DDR2_DQ[32] DDR2_DQ[36] DDR2_DQ[35] DDR2_DQ[37] VSS_C J DDR3_DQ[48] DDR3_DQ[52] VSS_C DDR3_DQ[6] DDR3_DQ[0] DDR3_DQ[7] DDR3_DQS_N[8] DDR3_DQS[8] DDR2_DQ[39] DDR3_DQ[68] DDR2_DQ[53] K DDR3_DQS[6] DDR3_DQS_N[6] DDR3_DQ[54] DDR3_DQ[56] VSS_C DDR3_DM[7] VDDP_M VSS_C DDR3_DQ[66] DDR3_DQ[70] DDR3_DQ[64] L DDR3_DQ[51] VDD_C DDR3_DQ[49] DDR3_DQ[53] DDR3_DQ[59] DDR3_DQ[58] VDD_C DDR3_DQ[60] DDR3_DM[8] DDR3_DQ[65] DDR3_DQ[69] M DDR3_DM[6] DDR3_DQ[50] DDR3_DQS[7] VSS_C DDR3_DQ[62] DDR3_DQ[63] DDR3_DQ[61] VSS_C DDR3_DQ[67] DDR3_DQ[71] VDD_C N VSS_C DDR3_DQ[55] DDR3_DQS_N[7] DDR3_DQ[57] DDR3_DQ[47] VSS_C DDR3_DQ[35] DDR3_DQ[37] DDR3_DQ[39] VDD_C VDD_C P DDR3_DQS[5] DDR3_DQS_N[5] VDDP_M DDR3_DQ[43] DDR3_DQ[45] DDR3_DM[4] DDR3_DQ[33] DDR3_ZQ1 VDD_C VSS_C VDD_C R DDR3_DQ[40] DDR3_DQ[42] DDR3_DQ[46] DDR3_DQ[41] VSS_C DDR3_DQ[34] DDR3_DQ[38] DDR3_ZQ0 VSS_C VDD_C VSS_C T DDR3_CKE VSS_C DDR3_DQS[4] DDR3_DQS_N[4] DDR3_DQ[44] DDR3_DM[5] DDR3_ADDR[14] VSS_C VDD_C VSS_C VDD_C U DDR3_WE_N DDR3_ODT DDR3_BANK[2] VDD_C DDR3_BANK[1] DDR3_CS_N DDR3_DQ[32] VDD_C DDR3_ADDR[6] DDR3_RESET_N VSS_C V DDR3_CLK_P DDR3_CLK_N DDR3_BANK[0] DDR3_ADDR[12] DDR3_ADDR[0] DDR3_DQ[36] DDR3_ADDR[8] DDR3_ADDR[7] VDD_C DDR3_ADDR[15] VSS_C W DDR3_ADDR[10] DDR3_CAS_N VSS_C DDR3_ADDR[3] DDR3_ADDR[1] DDR3_ADDR[9] VSS_C DDR3_ADDR[13] DDR3_ALERT_N VDD_C VSS_C Y DDR3_RAS_N DDR3_ADDR[4] DDR3_TEN DDR3_ADDR[2] VSS_C VDDP_M DDR3_PAR DDR3_ADDR[11] DDR3_ADDR[5] VSS_C VDD_C Figure 5-3 BM1680 Signal Map, Upper Left Sextant (Top View) A DDR2_DQ[58] DDR2_DQ[62] DDR2_DQ[4] DDR2_DQ[3] DDR2_DQS_N[0] DDR2_DQ[70] DDR2_DQ[68] DDR2_DQ[64] DDR2_DQS[2] DDR2_CLK_N DDR2_CLK_P DDR2_DQS_N[3] B DDR2_DQ[59] DDR2_DQ[56] VDDP_M DDR2_DQ[21] DDR2_DQS[0] DDR2_DQS[1] DDR2_DM[8] VSS_C DDR2_DQS_N[2] VREF_M2 VSS_C DDR2_DQS[3] C DDR2_DQ[63] DDR2_DM[7] DDR2_DQ[6] DDR2_DQ[67] AVSS_M2 DDR2_DQS_N[1] DDR2_DQS[8] DDR2_DQS_N[8] DDR2_DQ[22] DDR2_ADDR[4] DDR2_WE_N DDR2_CS_N D DDR2_DQ[60] VSS_C DDR2_DQ[0] DDR2_DQ[2] DDR2_DM[0] DDR2_DQ[1] VSS_C DDR2_DM[2] DDR2_DQ[16] DDR2_TEN DDR2_ODT VDDP_M E DDR2_DQ[57] DDR2_DQ[61] DDR2_DQ[52] VSS_C DDR2_DQ[8] DDR2_DQ[17] DDR2_DQ[19] DDR2_DQ[18] VDDP_M DDR2_ADDR[2] VSS_C DDR2_BANK[0] F VSS_C DDR2_DQ[54] DDR2_DQ[48] VDD_C DDR2_DQ[14] VSS_C DDR2_DQ[29] DDR2_DQ[25] DDR2_DQ[31] DDR2_PAR DDR2_ADDR[14] DDR2_ADDR[6] G DDR2_DQ[50] VSS_C DDR2_DQ[71] DDR2_DQ[5] DDR2_DQ[10] DDR2_DQ[23] DDR2_DQ[27] DDR2_DQ[20] DDR2_ADDR[11] VSS_C DDR2_ADDR[15] DDR2_DQ[24] H DDR2_DQ[51] VDD_C DDR2_DQ[12] DDR2_DQ[7] DDR2_DQ[65] DDR2_DQ[9] DDR2_DQ[26] DDR2_RAS_N DDR2_ADDR[5] DDR2_ALERT_N DDR2_DQ[30] DDR2_ZQ1 J DDR2_DQ[55] VSS_C VDD_C DDR2_DM[1] DDR2_DQ[11] AVDD_M2 VDD_C DDR2_DQ[66] DDR2_DQ[69] DDR2_CKE DDR2_DQ[28] DDR2_RESET_N K VSS_C VDD_C VSS_C VDD_C DDR2_DQ[15] DDR2_DQ[13] VSS_C VDD_C VSS_C VDD_C VSS_C VDD_C L VDD_C VSS_C VDD_C VSS_C VDD_C VSS_C VDD_C VSS_C VDD_C VSS_C VDD_C VSS_C M VSS_C VSS_C VSS_C VSS_C VDD_C VSS_C VSS_C VSS_C VDD_C VSS_C VSS_C VSS_C N VSS_C VDD_C VDD_C VDD_C VSS_C VDD_C VDD_C VDD_C VSS_C VDD_C VDD_C VQPS_E P VSS_C VDD_C VSS_C VDD_C VSS_C VDD_C VSS_C VDD_C VSS_C VDD_C VMON_N VDD_C R VDD_C VSS_C VSS_C VSS_C VDD_C VSS_C VSS_C VSS_C VDD_C VSS_C VMON_P VSS_C T VSS_C VDD_C VDD_C VDD_C VSS_C VSS_C VDD_C VSS_C VSS_C VSS_C VSS_C VSS_C U VSS_C VSS_C VDD_C VSS_C VDD_C VSS_C VDD_C VDD_C VDD_C VDD_C VDD_C VSS_C V VSS_C VDD_C VDD_C VSS_C VSS_C VDD_C VSS_C VDD_C VSS_C VDD_C VDD_C VSS_C W VDD_C VSS_C VSS_C VDD_C VSS_C VDD_C VDD_C VSS_C VSS_C VDD_C VSS_C VSS_C Y VSS_C VDD_C VDD_C VSS_C VSS_C VDD_C VDD_C VSS_C VSS_C VDD_C VSS_C VSS_C Figure 5-4 BM1680 Signal Map, Upper Middle Sextant (Top View)

14 A DDR2_ADDR[3] DDR2_ADDR[12] VDD_C IP_1[0] VDD_C IP_2[0] VAA_S IP_3[0] VDD_C IP_4[0] VDD_C IP_1[1] VAA_S IP_2[1] VDD_C VAA_S VSS_C B VDD_C DDR2_CAS_N VSS_C IN_1[0] VSS_C IN_2[0] VSS_C IN_3[0] VSS_C IN_4[0] VSS_C IN_1[1] VSS_C IN_2[1] VSS_C IN_3[1] IP_3[1] C DDR2_BANK[2] DDR2_BANK[1] VDD_C VAA_S VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VAA_S D DDR2_ADDR[10] VDD_C VSS_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VSS_C IN_4[1] IP_4[1] E DDR2_ADDR[0] DDR2_ADDR[1] VDD_C OP_1[0] VDD_C OP_2[0] VDD_C OP_3[0] VDD_C OP_4[0] VDD_C VSS_C VDD_C ON_1[1] OP_1[1] VSS_C VDD_C F DDR2_ADDR[9] DDR2_ADDR[8] VSS_C ON_1[0] VSS_C ON_2[0] VSS_C ON_3[0] VSS_C ON_4[0] VSS_C ON_1[2] OP_1[2] VDD_C VSS_C IN_1[2] IP_1[2] G DDR2_DM[3] DDR2_ADDR[7] VDD_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VDD_C ON_2[1] OP_2[1] VSS_C VAA_S H DDR2_ZQ0 DDR2_ADDR[13] VSS_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C ON_2[2] OP_2[2] VDD_C VSS_C IN_2[2] IP_2[2] J VDD_C VSS_C VDD_C CKIN[0] VDD_C CKIP[1] VDD_C VSS_C VDD_C GPIO27 VDD_C VSS_C VDD_C ON_3[1] OP_3[1] VSS_C VAA_S K VSS_C VDD_C VSS_C CKIP[0] VSS_C CKIN[1] VSS_C GPIO31 GPIO29 GPIO28 VSS_C ON_3[2] OP_3[2] VDD_C VSS_C IN_3[2] IP_3[2] L VDD_C VSS_C JTAGTMS VSS_C GPIO11 VSS_C SF_SCK GPIO9 UART_TX UART_RX VDD_C VSS_C VDD_C ON_4[1] OP_4[1] VSS_C VDD_C M VSS_C VSS_C JTAGTRST_X JTAGTDO GPIO10 VDD_C SF_SDO GPIO7 GPIO30 VDD_C VSS_C ON_4[2] OP_4[2] VDD_C VAA_S IN_4[2] IP_4[2] N TEMP_P VDD_C VDD_C JTAGTCK GPIO8 SF_CS_X SF_SDI VSS_C VDD_C ON_1[3] OP_1[3] VSS_C VDD_C IN_1[3] IP_1[3] VSS_C VAA_S P TEMP_N VDD_C MPLL_LOCKO JTAGTDI VSS_C SF_WP_X VSS_C CKIN[2] CKIP[2] VDD_C VSS_C ON_1[4] OP_1[4] VDD_C VSS_C IN_1[4] IP_1[4] R VDD_C VSS_C MPLL_BYP VSS_C VDD_C SF_HOLD_X SPI_CK_SEL0 VSS_C VDD_C ON_2[3] OP_2[3] VSS_C VDD_C IN_2[3] IP_2[3] VSS_C VDD_C T VDD_C VSS_C MPLL_CK_IN VSS_C DPLL1_LOCKO VDD_C VSS_C CKIN[3] CKIP[3] VDD_C VSS_C ON_2[4] OP_2[4] VDD_C VSS_C IN_2[4] IP_2[4] U VDD_C VDD_C VDD_C SPLL_LOCKO DPLL1_BYP EXT_RCVD_CLK GPIO0 VSS_C VDD_C ON_3[3] OP_3[3] VSS_C VDD_C IN_3[3] IP_3[3] VSS_C VDD_C V VDD_C VSS_C MODE_SEL1 SPLL_BYP DPLL1_CK_IN MODE_SEL2 VSS_C CKIN[4] CKIP[4] VDD_C VSS_C ON_3[4] OP_3[4] VDD_C VSS_C IN_3[4] IP_3[4] W VDD_C VSS_C IICS_SDA1 SPLL_CK_IN VDD_C GPIO17 SPI_CK_SEL1 VSS_C VDD_C ON_4[3] OP_4[3] VSS_C VDD_C IN_4[3] IP_4[3] VSS_C VAA_S Y VDD_C VSS_C IICS_SCL1 VSS_C VSS_C VDD_C VSS_C CKIN[5] CKIP[5] VDD_C VSS_C ON_4[4] OP_4[4] VDD_C VSS_C IN_4[4] IP_4[4] Figure 5-5 BM1680 Signal Map, Upper Right Sextant (Top View) AA DDR1_ADDR[12] VSS_C DDR1_ADDR[0] DDR1_ADDR[9] DDR1_ADDR[8] VSS_C VSS_C DDR1_RESET_N DDR1_ADDR[15] VSS_C VDD_C AB DDR1_BANK[2] DDR1_ADDR[3] DDR1_BANK[1] VSS_C DDR1_PAR DDR1_ADDR[7] DDR1_ADDR[13] DDR1_ADDR[2] DDR1_ADDR[5] VSS_C VDD_C AC VDDP_M DDR1_ADDR[4] DDR1_TEN DDR1_BANK[0] DDR1_ADDR[1] VDD_C DDR1_ADDR[6] DDR1_CAS_N DDR1_ALERT_N VDD_C VSS_C AD DDR1_CLK_P DDR1_CLK_N VDD_C DDR1_CS_N DDR1_ADDR[10] DDR1_WE_N VSS_C DDR1_ADDR[11] VDD_C VSS_C VDD_C AE DDR1_DM[5] DDR1_DQ[44] DDR1_DQ[47] DDR1_DQ[45] VSS_C DDR1_ODT DDR1_CKE DDR1_ADDR[14] VSS_C VDD_C VSS_C AF DDR1_DQ[46] VSS_C DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[32] DDR1_DQ[36] VSS_C DDR1_RAS_N VDD_C DDR1_ZQ1 VDD_C AG DDR1_DQS[4] DDR1_DQS_N[4] DDR1_DQ[42] VSS_C DDR1_DQ[34] DDR1_DQ[33] DDR1_DQ[38] VDD_C DDR1_ZQ0 VDD_C VSS_C AH DDR1_DQ[43] DDR1_DQS[5] DDR1_DQS_N[5] DDR1_DM[4] DDR1_DQ[35] VDD_C DDR1_DQ[39] DDR1_DQ[70] DDR1_DQ[68] VSS_C VSS_C AJ DDR1_DM[6] DDR1_DQ[54] VDDP_M DDR1_DQ[63] DDR1_DQ[61] DDR1_DQ[59] DDR1_DQ[37] VSS_C VDD_C VDD_C VDD_C AK DDR1_DQ[49] DDR1_DQ[51] DDR1_DQ[53] DDR1_DQ[55] VSS_C DDR1_DQ[57] DDR1_DQ[64] DDR1_DQ[67] DDR1_DQ[69] VSS_C VDD_C AL DDR1_DQ[50] VSS_C DDR1_DQS_N[7] DDR1_DQ[62] DDR1_DQ[58] DDR1_DQ[60] DDR1_DQS_N[8] DDR1_DQ[66] DDR1_DQ[71] VSS_C VDD_C AM DDR1_DQ[52] DDR1_DQ[48] DDR1_DQS[7] AVSS_M1 DDR1_DQ[56] DDR1_DM[7] DDR1_DQS[8] VSS_C DDR1_DQ[65] DDR0_DQ[46] DDR0_DM[5] AN VDDP_M DDR1_DQS_N[6] DDR1_DQS[6] DDR1_DQ[7] DDR1_DQ[6] VREF_M1 DDR1_DM[3] DDR1_DM[8] DDR0_DQ[40] DDR0_DQ[45] VSS_C AP DDR1_DQ[3] DDR1_DQ[1] AVDD_M1 DDR1_DQ[5] DDR1_DQ[0] DDR1_DQ[21] DDR1_DQ[28] VSS_C DDR0_DQ[44] DDR0_DQ[43] DDR0_DQ[47] AR DDR1_DQ[20] DDR1_DM[0] DDR1_DQ[2] DDR1_DQ[16] VSS_C DDR1_DQ[23] DDR1_DQ[24] VDD_C VSS_C VDDP_M DDR0_DQ[41] AT DDR1_DQ[22] VSS_C DDR1_DQ[4] DDR1_DQ[18] DDR1_DM[2] DDR1_DQ[30] VSS_C DDR0_DQ[36] DDR0_DQ[39] DDR0_DQ[37] DDR0_DQ[42] AU DDR1_DQS[0] DDR1_DQS_N[0] DDR1_DQ[13] VDD_C DDR1_DQ[19] DDR1_DQ[26] DDR1_DQ[27] DDR0_DQ[34] VSS_C DDR0_DQ[55] DDR0_DQ[49] AV DDR1_DQS[2] DDR1_DQS_N[2] DDR1_DQ[11] DDR1_DQ[15] DDR1_DQ[8] VSS_C DDR1_DQS[3] DDR0_DQ[32] DDR0_DM[4] DDR0_DQ[53] VDD_C AW DDR1_DQS_N[1] DDR1_DQ[9] VSS_C DDR1_DQ[12] DDR1_DQ[17] DDR1_DQ[31] DDR1_DQS_N[3] VSS_C DDR0_DQS_N[4] DDR0_DQ[33] DDR0_DQS[6] AY DDR1_DQS[1] DDR1_DQ[14] DDR1_DQ[10] DDR1_DM[1] VDDP_M DDR1_DQ[29] DDR1_DQ[25] DDR0_DQ[38] DDR0_DQS[4] DDR0_DQ[35] DDR0_DQS_N[6] Figure 5-6 BM1680 Signal Map, Lower Left Sextant (Top View)

15 AA VSS_C VSS_C VDD_C VSS_C VDD_C VSS_C VSS_C VDD_C VSS_C VDD_C VDD_C VSS_C AB VSS_C VDD_C VDD_C VSS_C VSS_C VDD_C VDD_C VSS_C VSS_C VDD_C VDD_C VSS_C AC VDD_C VSS_C VSS_C VDD_C VSS_C VDD_C VSS_C VSS_C VDD_C VSS_C VSS_C VSS_C AD VSS_C VDD_C VDD_C VSS_C VSS_C VDD_C VDD_C VSS_C VSS_C VDD_C VDD_C VSS_C AE VSS_C VSS_C VDD_C VSS_C VDD_C VSS_C VSS_C VDD_C VSS_C VDD_C VDD_C VSS_P AF VSS_C VDD_C VDD_C VSS_C VSS_C VDD_C VDD_C VSS_C VSS_C VSS_C VDD_C VDD_P AG VDD_C VSS_C VSS_C VDD_C VSS_C VDD_C VDD_C VSS_C VDD_C VSS_C VSS_C VSS_C AH VSS_C VDD_C VDD_C VSS_C VSS_C VSS_C VDD_C VSS_C VDD_C VDD_C VSS_C VDD_P AJ VSS_C VSS_C VDD_C VSS_C VDD_C VDD_C VDD_C VSS_C VDD_C VDD_C VSS_C VSS_P AK VSS_C VDD_C VSS_C VDD_C VSS_C VSS_C VDD_C VSS_C DDR0_DQ[0] VDD_C VDD_C VSS_C AL VSS_C VDD_C DDR0_DQ[5] VDD_C VDD_C VSS_C DDR0_DQ[4] VSS_C DDR0_DQ[28] DDR0_DQ[24] DDR0_ADDR[6] VSS_C AM VSS_C DDR0_DQ[61] VDD_C DDR0_DM[0] DDR0_ZQ0 DDR0_DQ[6] DDR0_DQ[21] VSS_C DDR0_DM[3] DDR0_DQ[26] DDR0_ADDR[13] VDD_C AN DDR0_DQ[59] VSS_C DDR0_DQ[7] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQS[0] DDR0_DQS_N[0] VSS_C DDR0_ZQ1 DDR0_RESET_N VSS_C DDR0_ALERT_N AP DDR0_DQS_N[7] VDD_C DDR0_DQ[57] DDR0_DQ[3] DDR0_DM[1] DDR0_DQ[20] VDD_C DDR0_DQ[17] DDR0_DQ[23] DDR0_ADDR[7] DDR0_ADDR[8] DDR0_DQ[30] AR DDR0_DQS[7] DDR0_DQ[63] DDR0_DQ[62] VSS_C DDR0_DQ[12] DDR0_DQ[16] DDR0_DM[2] DDR0_DQ[19] DDR0_ADDR[15] DDR0_ADDR[9] DDR0_ADDR[1] DDR0_TEN AT VSS_C DDR0_DQ[58] DDR0_DQ[60] DDR0_DQ[22] DDR0_DQ[8] VSS_C DDR0_DQ[18] DDR0_DQ[68] DDR0_DQ[69] DDR0_WE_N DDR0_BANK[1] DDR0_ADDR[4] AU DDR0_DM[6] DDR0_DQ[51] VSS_C DDR0_DQ[14] DDR0_DQ[10] DDR0_DQS_N[2] DDR0_DQ[71] AVSS_M0 DDR0_DQ[66] DDR0_CS_N DDR0_BANK[2] DDR0_ADDR[3] AV DDR0_DQS[5] DDR0_DQ[56] DDR0_DM[7] DDR0_DQ[11] VDD_C DDR0_DQS[2] DDR0_DQ[64] DDR0_DQ[70] DDR0_DM[8] VSS_C DDR0_ADDR[14] DDR0_DQ[27] AW DDR0_DQS_N[5] VDDP_M DDR0_DQ[52] DDR0_DQ[9] DDR0_DQ[15] DDR0_DQS[1] AVDD_M0 DDR0_DQS[8] DDR0_DQ[65] DDR0_ODT DDR0_CLK_P VSS_C AY DDR0_DQ[50] DDR0_DQ[48] DDR0_DQ[54] VSS_C DDR0_DQ[13] DDR0_DQS_N[1] DDR0_DQ[67] DDR0_DQS_N[8] VREF_M0 DDR0_CKE DDR0_CLK_N DDR0_DQS[3] Figure 5-7 BM1680 Signal Map, Lower Middle Sextant (Top View) AA VDD_C VDD_C VDD_C GPIO2 GPIO3 GPIO4 VDD_C VSS_C VDD_C ON_1[6] OP_1[6] VSS_C VDD_C IN_1[6] IP_1[6] VSS_C VAA_S AB VDD_C VDD_C GPIO19 MODE_SEL0 IICM_SCL IICM_SDA VSS_C CKIN[6] CKIP[6] VDD_C VSS_C ON_1[5] OP_1[5] VDD_C VSS_C IN_1[5] IP_1[5] AC VDD_C VSS_C TEST_EN GPIO1 GPIO15 GPIO16 GPIO24 VSS_C VDD_C ON_2[6] OP_2[6] VSS_C VDD_C IN_2[6] IP_2[6] VSS_C VDD_C AD VDD_C VSS_C GPIO20 VSS_C BOOT_SEL VDD_C VSS_C CKIN[7] CKIP[7] VDD_C VSS_C ON_2[5] OP_2[5] VDD_C VSS_C IN_2[5] IP_2[5] AE VDD_C VSS_C VDD_C SYS_RST_X VDD_C GPIO23 MDC VSS_C VDD_C ON_3[6] OP_3[6] VSS_C VDD_C IN_3[6] IP_3[6] VSS_C VDD_C AF VSS_C VSS_IO GPIO26 GPIO21 GPIO22 MDIO VSS_C CKIN[8] CKIP[8] VDD_C VSS_C ON_3[5] OP_3[5] VDD_C VSS_C IN_3[5] IP_3[5] AG VDD_C VDD_IO GPIO6 GPIO18 GPIO12 GPIO13 GPIO25 VSS_C VDD_C ON_4[6] OP_4[6] VSS_C VDD_C IN_4[6] IP_4[6] VSS_C VAA_S AH VSS_C VDD_IO GPIO5 VDD_C GPIO14 VDD_C VSS_C CKIN[9] CKIP[9] VDD_C VSS_C ON_4[5] OP_4[5] VDD_C VSS_C IN_4[5] IP_4[5] AJ VSS_C VSS_IO VSS_C VSS_C VSS_C DPLL2_LOCKO DPLL2_BYP VSS_C VDD_C TSTOUT VDD_C VSS_C VDD_C VDD_C VSS_C VSS_C VAA_S AK VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C DPLL2_CK_IN VDD_C VSS_C VDD_C VSS_C ON_1[8] OP_1[8] VDD_C VSS_C IN_1[7] IP_1[7] AL VDD_C VDD_C VDD_C VDD_C DPLL3_LOCKO DPLL3_BYP VDD_C VDD_C VDD_C VSS_C VDD_C VSS_C VDD_C ON_1[7] OP_1[7] VSS_C VDD_C AM DDR0_DQ[29] VSS_C VSS_C VSS_C VSS_C DPLL3_CK_IN VSS_C VSS_C VSS_C VDD_C VSS_C ON_2[8] OP_2[8] VDD_C VSS_C IN_2[7] IP_2[7] AN DDR0_ADDR[5] DDR0_ADDR[11] VDD_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VDD_C ON_2[7] OP_2[7] VSS_C VDD_C AP DDR0_DQ[31] DDR0_PAR VSS_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C ON_3[8] OP_3[8] VDD_C VAA_S IN_3[7] IP_3[7] AR DDR0_DQ[25] DDR0_ADDR[2] VDD_C ON_4[9] VDD_C ON_3[9] VDD_C ON_2[9] VDD_C ON_1[9] VDD_C VSS_C VDD_C ON_3[7] OP_3[7] VSS_C VDD_C AT DDR0_BANK[0] DDR0_ADDR[0] VSS_C OP_4[9] VSS_C OP_3[9] VSS_C OP_2[9] VSS_C OP_1[9] VSS_C ON_4[8] OP_4[8] VDD_C VSS_C IN_4[7] IP_4[7] AU VDDP_M VSS_C VDD_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VSS_C VDD_C ON_4[7] OP_4[7] VSS_C VAA_S AV DDR0_ADDR[12] DDR0_ADDR[10] VSS_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VDD_C VSS_C VDD_C VSS_C IN_1[8] IP_1[8] AW VDD_C DDR0_CAS_N VDD_C IN_4[9] VSS_C IN_3[9] VDD_C IN_2[9] VDD_C IN_1[9] VSS_C IN_4[8] VDD_C IN_3[8] VDD_C VSS_C VAA_S AY DDR0_DQS_N[3] DDR0_RAS_N VSS_C IP_4[9] VAA_S IP_3[9] VSS_C IP_2[9] VSS_C IP_1[9] VAA_S IP_4[8] VSS_C IP_3[8] VSS_C IN_2[8] IP_2[8] Figure 5-8 BM1680 Signal Map, Lower Right Sextant (Top View)

16 6 BM1680 Signal Descriptions This chapter provides functional descriptions of the BM1680 I/O signals. The signals are grouped according to the I/O interfaces. 6.1 DDR Memory Interface Signals Each of the four BM1680 DRAM interfaces communicates with up to four ranks across a 72-bit data bus (64 bits for data and 8 bits for ECC). Table 6-1 DDR Channel [0/1/2/3] interface signals Interface Name Signal Name I/O Description DDR Channel? DDR?_ADDR[13:0] O Memory Address Bus DDR?_BG[1] / DDR?_ADDR[15] O Memory Bank Group select bit 1 / pin share with DDR_ADDR[15] DDR?_BG[0] / DDR?_BANK[2] O Memory Bank Group select bit 0 / pin share with DDR_BANK[2] DDR?_BANK[1:0] O Memory Bank Address DDR?_DM[8:0] O Data Mask for byte and Data Bus Invertion pin share, active-low DDR?_CKE[1:0] O Memory Clock Enables DDR?_CLK_P[1:0] O Memory Clocks (+) DDR?_CLK_N[1:0] O Memory Clocks (-) DDR?_CS_N O Memory Chip Selects, active-low DDR?_ACT_N / DDR?_ADDR[14] O Memory Activation Command, active-low / pin share with DDR_ADDR[14] DDR?_DQ[71:0] IO External Memory Data Bus DDR?_DQS_P[8:0] IO Memory Data Strobe for byte DDR?_DQS_N[8:0] IO Memory Data Strobe for byte DDR?_ZQ[1:0] IO ZQ calibration reference input DDR?_RESET_N O Memory reset signal, active low DDR?_PAR O Parity for command and address DDR?_ALERT_N IO Alert status signal DDR?_TEN O Connectivity test mode DDR?_ODT O On-Die Termination DDR?_RAS_N O DDR Row Address RAS, active-low DDR?_CAS_N O DDR Column Address CAS, active-low DDR?_WE_N O DDR Write Enable, active-low

17 6.2 SerDes Interface Signals The BM1680 contains ten SerDes quad-lane modules that are as shown in the below table. Table 6-2 SerDes interface signals Interface Name Signal Name I/O Description SerDes OP_0[9:0] O TX differentioal signal pair, data plus 0 for SerDes 9-0 ON_09:0] O TX differentioal signal pair, data minus 0 for SerDes 9-0 IP_0[9:0] I RX differentioal signal pair, data plus 0 for SerDes 9-0 IN_0[9:0] I RX differentioal signal pair, data minus 0 for SerDes 9-0 OP_1[9:0] O TX differentioal signal pair, data plus 1 for SerDes 9-0 ON_1[9:0] O TX differentioal signal pair, data minus 1 for SerDes 9-0 IP_1[9:0] I RX differentioal signal pair, data plus 1 for SerDes 9-0 IN_1[9:0] I RX differentioal signal pair, data minus 1 for SerDes 9-0 OP_2[9:0] O TX differentioal signal pair, data plus 2 for SerDes 9-0 ON_2[9:0] O TX differentioal signal pair, data minus 2 for SerDes 9-0 IP_2[9:0] I RX differentioal signal pair, data plus 2 for SerDes 9-0 IN_2[9:0] I RX differentioal signal pair, data minus 2 for SerDes 9-0 OP_3[9:0] O TX differentioal signal pair, data plus 3 for SerDes 9-0 ON_3[9:0] O TX differentioal signal pair, data minus 3 for SerDes 9-0 IP_3[9:0] I RX differentioal signal pair, data plus 3 for SerDes 9-0 IN_3[9:0] I RX differentioal signal pair, data minus 3 for SerDes 9-0 CKIP[9:0] I Reference clock plus for SerDes 9-0 CKIN[9:0] I Reference clock minus for SerDes 9-0 TSTOUT O Anolog testpoint output ranging from 0V to VAA Ext_Rcvd_Clk I Backup ref clock from external MDC I MDIO clock input MDIO I/O MDIO serial data signal 6.3 UART Interface Signals Table 6-3 UART interface signals Interface Name Signal Name I/O Description UART UART_TX O UART Transmit Data UART_RX I UART Receive Data 6.4 IIC Interface Signals

18 Table 6-4 IIC interface signals Interface Name Signal Name I/O Description IIC IICM_SDA/IICS_SDA0 I/O IIC master data wire / IIC slave0 data wire IICM_SCL/IICS_SCL0 O IIC master clock output / IIC slave0 clock input IICS_SDA1 I/O IIC slave1 data wire (for DDR PHY config) IICS_SCL1 O IIC slave1 clock input (for DDR PHY config) 6.5 SPI Flash Interface Signals Table 6-5 SPI Flash interface signals Interface Name Signal Name I/O Description SPI Flash SF_CS_X O SPI Flash Chip Selects, active-low SF_HOLD_X O QSPI Data Hold, active-low SF_WP_X O QSPI write protect signal, active-low SF_SDI I SPI Flash Serial Data Input SF_SDO O SPI Flash Serial Data Output SF_SCK O SPI Flash Clock 6.6 JTAG Interface Signals Table 6-6 JTAG interface signals Interface Name Signal Name I/O Description JTAG JTAGTDO O JTAG Test Data Output JTAGTCK I JTAG Clock JTAGTDI I JTAG Test Data Input JTAGTMS I JTAG Test Mode Select JTAGTRST# I JTAG Test Reset, active-low 6.7 Miscellaneous(MISC)Interface Signals Table 6-7 MISC interface signals Interface Name Signal Name I/O Description MISC GPIO[31:0] I/O General Purpose Input/Output [31:0]. BOOT_SEL I Boot method select, low boot from flash, high boot from ITCM SYS_RST# I System Reset, active-low

19 TEST_EN I TEST Mode Enable MODE_SEL[2:0] I Mode Select VMON_P A Voltage monitor signal anode VMON_N A Voltage monitor signal cathode TEMP_P A Thermal diode anode TEMP_N A Thermal diode cathode SPI_CK_SEL[1:0] I SPI flash default clock selection bit 6.8 Clock Interface Signals Table 6-8 clock interface signals Interface Name Signal Name I/O Description Clocks MPLL_CK_IN I Main PLL base clock source input MPLL_BYP I Bypass Main PLL and use the clock from MPLL_CK_IN directly. MPLL_LOCKO O Main PLL Lock output for testing purpose SPLL_CK_IN I Secondary PLL base clock source input (for DDR channel 0) SPLL_BYP I Bypass Secondary PLL and use the clock from SPLL_CK_IN directly. SPLL_LOCKO O Secondary PLL Lock output for testing purpose DPLL0_CK_IN I DDR PLL0 base clock source input (for DDR channel 1) DPLL0_BYP I Bypass DDR PLL0 and use the clock from DPLL0_CK_IN directly. DPLL0_LOCKO O DDR PLL0 Lock output for testing purpose DPLL1_CK_IN I DDR PLL1 base clock source input (for DDR channel 2) DPLL1_BYP I Bypass DDR PLL1 and use the clock from DPLL1_CK_IN directly. DPLL1_LOCKO O DDR PLL1 Lock output for testing purpose DPLL2_CK_IN I DDR PLL2 base clock source input (for DDR channel 3) DPLL2_BYP I Bypass DDR PLL2 and use the clock from DPLL2_CK_IN directly. DPLL2_LOCKO O DDR PLL2 Lock output for testing purpose 6.9 Power & Ground Signals Table 6-9 power & ground interface signals

20 Interface Name Signal Name I/O Description VAA_S P 1.5V power supply for analog & CTLE Power & Ground VAA_AGC_S P 1.5V power supply for CTLE VDD_P_T[4:1] P 0.9V supply for PLL reference rate circuits VDD_P_B P 0.9V supply for PLL reference rate circuits VSS_P_T[4:1] G 0V supply and substrate connection VSS_P_B G 0V supply and substrate connection VDD_IO_T[4:1] P 1.8V supply for IO post-drive VDD_IO_B[2:1] P 1.8V supply for IO post-drive VSS_IO_T[4:1] G 0V supply for IO post-drive VSS_IO_B[2:1] G 0V supply for IO post-drive VREF_M[3:0] P Reference voltage of DDR (0.5*VDDP_M) VDDP_M P DDR postdrive power (1.2V for DDR4) AVDD_M[3:0] P DDR analog power for PLL, 1.8V AVSS_M[3:0] G DDR analog ground VDD_C P 0.9v core power VDD_S P 0.9V power supply for core VDD_M P DDR core power, 0.9V VSS_C G Core ground VSS_S G Ground VSS_M G DDR core ground VSSP_M G DDR postdrive ground VQPS_E P High voltage (1.8V) for fuse programming