description x412 and x413 devices F415 and F417 devices

Transcription

1 Low Supply-Voltage Range,.8 V V Ultralow-Power Consumption: Active Mode: 2 µa at MHz, 2.2 V Standby Mode:.7 µa Off Mode (RAM Retention):. µa Five Power-Saving Modes Wake-Up From Standby Mode in less than 6 µs Frequency-Locked Loop, FLL+ 6-Bit RISC Architecture, 25-ns Instruction Cycle Time 6-Bit Timer_A With Three or Five Capture/Compare Registers Integrated LCD Driver for 96 Segments On-Chip Comparator Brownout Detector Supply Voltage Supervisor/Monitor - Programmable Level Detection on MSP43F45/47 devices only x42 and x43 devices F45 and F47 devices Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse Bootstrap Loader in Flash Devices Family Members Include: MSP43C42: 4KB ROM, 256B RAM MSP43C43: 8KB ROM, 256B RAM MSP43F42: 4KB + 256B Flash 256B RAM MSP43F43: 8KB + 256B Flash 256B RAM MSP43F45: 6KB + 256B Flash 52B RAM MSP43F47: 32KB + 256B Flash KB RAM Available in 64-Pin Quad Flat Pack (QFP) and 64-pin QFN For Complete Module Descriptions, Refer to the MSP43x4xx Family User s Guide, Literature Number SLAU56 description The Texas Instruments MSP43 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 6-bit RISC CPU, 6-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs. The MSP43x4x series are microcontroller configurations with one or two built-in 6-bit timers, a comparator, 96 LCD segment drive capability, and 48 I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and process the data and transmit them to a host system. The comparator and timer make the configurations ideal for industrial meters, counter applications, handheld meters, etc. TA 4 C to 85 C Preliminary AVAILABLE OPTIONS PACKAGED DEVICES PLASTIC 64-PIN QFP (PM) PLASTIC 64-PIN QFN (RTD) MSP43C42IPM MSP43C43IPM MSP43F42IPM MSP43F43IPM MSP43F45IPM MSP43F47IPM MSP43C42IRTD MSP43C43IRTD MSP43F42IRTD MSP43F43IRTD MSP43F45IRTD MSP43F47IRTD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2 24, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS 75265

2 pin designation, MSP43x42, MSP43x43 P6.2 P6. P6. RST/NMI TCK TMS TDI/TCLK TDO/TDI P./TA P./TA/MCLK P.2/TA P.3/SVSOUT P.4 DV CC P6.3 P6.4 P6.5 P6.6 P6.7 NC XIN XOUT NC NC P5./S P5./S P4.7/S2 P4.6/S3 P4.5/S MSP43x MSP43x P.5/TACLK/ACLK P.6/CA P.7/CA P2./TA2 P2. P5.7/R33 P5.6/R23 P5.5/R3 R3 P5.4/COM3 P5.3/COM2 P5.2/COM COM P2.2/S23 P2.3/S22 P2.4/S2 P4.4/S5 P4.3/S6 P4.2/S7 P4./S8 P4./S9 P3.7/S P3.6/S P3.5/S2 P3.4/S3 P3.3/S4 P3.2/S5 P3./S6 P3./S7 P2.7/S8 P2.6/CAOUT/S9 P2.5/S2 AV CC DV SS AV SS NC No internal connection. External connection to VSS recommended. 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 pin designation, MSP43x45, MSP43x47 P6.2 P6. P6. RST/NMI TCK TMS TDI/TCLK TDO/TDI P./TA. P./TA./MCLK P.2/TA. P.3/TA./SVSOUT P.4/TA. DV CC P6.3 P6.4 P6.5 P6.6 P6.7 NC XIN XOUT AV SS2 NC P5./S P5./S P4.7/S2 P4.6/S3 P4.5/S MSP43x MSP43x P.5/TACLK/ACLK P.6/CA P.7/CA P2./TA.2 P2./TA. P5.7/R33 P5.6/R23 P5.5/R3 R3 P5.4/COM3 P5.3/COM2 P5.2/COM COM P2.2/TA.2/S23 P2.3/TA.3/S22 P2.4/TA.4/S2 P4.4/S5 P4.3/S6 P4.2/S7 P4./S8 P4./S9 P3.7/S P3.6/S P3.5/S2 P3.4/S3 P3.3/S4 P3.2/S5 P3./S6 P3./S7 P2.7/S8 P2.6/CAOUT/S9 P2.5/TACLK/S2 AV CC DV SS AV SS NC No internal connection. External connection to VSS recommended. POST OFFICE BOX DALLAS, TEXAS

4 functional block diagram, MSP43x42, MSP43x43 XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P P2 P3 P4 P5 P Oscillator FLL+ ACLK SMCLK 4KB/8KB Flash-F4x ROM-C4x 256B RAM I/O Port /2 6 I/Os, with Interrupt Capability I/O Port 3/4 6 I/Os I/O Port 5/6 6 I/Os MCLK CPU Incl. 6 Reg. Test JTAG Emulation Module MAB, MAB, 6 Bit6-Bit MDB, MDB, 6 6-Bit MAB, 4 Bit MCB Bus Conv MDB, 8 Bit 4 TMS TCK TDI/TCLK TDO/TDI Watchdog Timer 5/6-Bit Timer_A3 3 CC Reg POR/ SVS/ Brownout Comparator A Basic Timer Interrupt Vector LCD 96 Segments,2,3,4 MUX flcd functional block diagram, MSP43x45, MSP43x47 XIN XOUT DVCC DVSS AVCC AVSS AVSS2 RST/NMI P P2 P3 P4 P5 P Oscillator FLL+ ACLK SMCLK 6KB Flash 32KB Flash 52B RAM KB RAM I/O Port /2 6 I/Os, with Interrupt Capability I/O Port 3/4 6 I/Os I/O Port 5/6 6 I/Os MCLK CPU Incl. 6 Reg. Test JTAG Emulation Module MAB, MAB, 6 Bit6-Bit MDB, MDB, 6 6-Bit MAB, 4 Bit MCB Bus Conv MDB, 8 Bit 4 TMS TCK TDI/TCLK TDO/TDI Watchdog Timer 5/6-Bit Timer_A3 3 CC Reg Timer_A5 5 CC Reg POR/ Multilevel SVS/ Brownout Comparator A Basic Timer Interrupt Vector LCD 96 Segments,2,3,4 MUX flcd 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 Terminal Functions MSP43x42, MSP43x43 TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Positive terminal that supplies SVS, brownout, oscillator, FLL+, comparator_a, port, and LCD resistive divider circuitry; must not power up prior to DVCC. AVSS 62 Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_a. Needs to be externally connected to DVSS. DVCC Digital supply voltage, positive terminal. Supplies all parts, except those which are supplied via AVCC. DVSS 63 Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via AVCC/AVSS. NC 7,, Not internally connected. Connection to VSS recommended. P./TA 53 I/O General-purpose digital I/O/Timer_A. Capture: CCIA input, compare: Out output/bsl transmit P./TA/MCLK 52 I/O General-purpose digital I/O/Timer_A. Capture: CCIB input/mclk output. Note: TA is only an input on this pin/bsl receive P.2/TA 5 I/O General-purpose digital I/O/Timer_A, capture: CCIA input, compare: Out output P.3/SVSOUT 5 I/O General-purpose digital I/O/SVS: output of SVS comparator P.4 49 I/O General-purpose digital I/O P.5/TACLK/ ACLK 48 I/O General-purpose digital I/O/input of Timer_A clock/output of ACLK P.6/CA 47 I/O General-purpose digital I/O/Comparator_A input P.7/CA 46 I/O General-purpose digital I/O/Comparator_A input P2./TA2 45 I/O General-purpose digital I/O/ Timer_A capture: CCI2A input, compare: Out2 output P2. 44 I/O General-purpose digital I/O P2.2/S23 35 I/O General-purpose digital I/O/LCD segment output 23 (see Note ) P2.3/S22 34 I/O General-purpose digital I/O/LCD segment output 22 (see Note ) P2.4/S2 33 I/O General-purpose digital I/O/LCD segment output 2 (see Note ) P2.5/S2 32 I/O General-purpose digital I/O/LCD segment output 2 (see Note ) P2.6/CAOUT/S9 3 I/O General-purpose digital I/O/Comparator_A output/lcd segment output 9 (see Note ) P2.7/S8 3 I/O General-purpose digital I/O/LCD segment output 8 (see Note ) P3./S7 29 I/O General-purpose digital I/O/ LCD segment output 7 (see Note ) P3./S6 28 I/O General-purpose digital I/O/ LCD segment output 6 (see Note ) P3.2/S5 27 I/O General-purpose digital I/O/ LCD segment output 5 (see Note ) P3.3/S4 26 I/O General-purpose digital I/O/ LCD segment output 4 (see Note ) P3.4/S3 25 I/O General-purpose digital I/O/LCD segment output 3 (see Note ) P3.5/S2 24 I/O General-purpose digital I/O/LCD segment output 2 (see Note ) P3.6/S 23 I/O General-purpose digital I/O/LCD segment output (see Note ) P3.7/S 22 I/O General-purpose digital I/O/LCD segment output (see Note ) NOTE : LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits. POST OFFICE BOX DALLAS, TEXAS

6 Terminal Functions (Continued) MSP43x42, MSP43x43 (continued) TERMINAL NAME NO. I/O DESCRIPTION P4./S9 2 I/O General-purpose digital I/O/LCD segment output 9 (see Note ) P4./S8 2 I/O General-purpose digital I/O/LCD segment output 8 (see Note ) P4.2/S7 9 I/O General-purpose digital I/O/LCD segment output 7 (see Note ) P4.3/S6 8 I/O General-purpose digital I/O/LCD segment output 6 (see Note ) P4.4/S5 7 I/O General-purpose digital I/O/LCD segment output 5 (see Note ) P4.5/S4 6 I/O General-purpose digital I/O/LCD segment output 4 (see Note ) P4.6/S3 5 I/O General-purpose digital I/O/LCD segment output 3 (see Note ) P4.7/S2 4 I/O General-purpose digital I/O/LCD segment output 2 (see Note ) P5./S 3 I/O General-purpose digital I/O/LCD segment output (see Note ) P5./S 2 I/O General-purpose digital I/O/LCD segment output (see Note ) COM 36 O Common output. COM 3 are used for LCD backplanes P5.2/COM 37 I/O General-purpose digital I/O/common output. COM 3 are used for LCD backplanes P5.3/COM2 38 I/O General-purpose digital I/O/common output. COM 3 are used for LCD backplanes P5.4/COM3 39 I/O General-purpose digital I/O/common output. COM 3 are used for LCD backplanes R3 4 I Input port of fourth positive (lowest) analog LCD level (V5) P5.5/R3 4 I/O General-purpose digital I/O/input port of third most positive analog LCD level (V4 or V3) P5.6/R23 42 I/O General-purpose digital I/O/input port of second most positive analog LCD level (V2) P5.7/R33 43 I/O General-purpose digital I/O/output port of most positive analog LCD level (V) P6. 59 I/O General-purpose digital I/O P6. 6 I/O General-purpose digital I/O P6.2 6 I/O General-purpose digital I/O P6.3 2 I/O General-purpose digital I/O P6.4 3 I/O General-purpose digital I/O P6.5 4 I/O General-purpose digital I/O P6.6 5 I/O General-purpose digital I/O P6.7 6 I/O General-purpose digital I/O RST/NMI 58 I Reset input or nonmaskable interrupt input port TCK 57 I Test clock. TCK is the clock input port for device programming and test. TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI. TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal. TMS 56 I Test mode select. TMS is used as an input port for device programming and test. XIN 8 I Input port for crystal oscillator XT. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT. QFN Pad NA NA QFN package pad connection to VSS recommended. NOTE : LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits. 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 Terminal Functions (Continued) MSP43x45, MSP43x47 TERMINAL NAME NO. I/O DESCRIPTION AVCC 64 Positive terminal that supplies SVS, brownout, oscillator, FLL+, comparator_a, port, and LCD resistive divider circuitry; must not power up prior to DVCC. AVSS 62 Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_a. Needs to be externally connected to DVSS. DVCC Digital supply voltage, positive terminal. Supplies all parts, except those which are supplied via AVCC. DVSS 63 Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via AVCC/AVSS. AVSS2 Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_a. Needs to be externally connected to DVSS. NC 7, Not internally connected. Connection to VSS recommended. P./TA. 53 I/O General-purpose digital I/O/Timer_A. Capture: CCIA input, compare: Out output/bsl transmit P./TA./MCLK 52 I/O General-purpose digital I/O/Timer_A. Capture: CCIB input/mclk output. Note: TA is only an input on this pin/bsl receive P.2/TA. 5 I/O General-purpose digital I/O/Timer_A, capture: CCIA input, compare: Out output P.3/TA./ 5 I/O General-purpose digital I/O/Timer_A, capture: CCIB input/svs: output of SVS comparator SVSOUT P.4/TA. 49 I/O General-purpose digital I/O/Timer_A, capture: CCIA input, compare: Out output P.5/TACLK/ 48 I/O General-purpose digital I/O/input of Timer_A clock/output of ACLK ACLK P.6/CA 47 I/O General-purpose digital I/O/Comparator_A input P.7/CA 46 I/O General-purpose digital I/O/Comparator_A input P2./TA.2 45 I/O General-purpose digital I/O/ Timer_A capture: CCI2A input, compare: Out2 output P2./TA. 44 I/O General-purpose digital I/O/Timer_A, capture: CCIA input, compare: Out output P2.2/TA.2/S23 35 I/O General-purpose digital I/O/Timer_A, capture: CCI2A input, compare: Out2 output/lcd segment output 23 (see Note ) P2.3/TA.3/S22 34 I/O General-purpose digital I/O/Timer_A, capture: CCI3A input, compare: Out3 output/lcd segment output 22 (see Note ) P2.4/TA.4/S2 33 I/O General-purpose digital I/O/Timer_A, capture: CCI4A input, compare: Out4 output/lcd segment output 2 (see Note ) P2.5/TACLK/S2 32 I/O General-purpose digital I/O/input of Timer_A clock/lcd segment output 2 (see Note ) P2.6/CAOUT/S9 3 I/O General-purpose digital I/O/Comparator_A output/lcd segment output 9 (see Note ) P2.7/S8 3 I/O General-purpose digital I/O/LCD segment output 8 (see Note ) P3./S7 29 I/O General-purpose digital I/O/ LCD segment output 7 (see Note ) P3./S6 28 I/O General-purpose digital I/O/ LCD segment output 6 (see Note ) P3.2/S5 27 I/O General-purpose digital I/O/ LCD segment output 5 (see Note ) P3.3/S4 26 I/O General-purpose digital I/O/ LCD segment output 4 (see Note ) P3.4/S3 25 I/O General-purpose digital I/O/LCD segment output 3 (see Note ) P3.5/S2 24 I/O General-purpose digital I/O/LCD segment output 2 (see Note ) P3.6/S 23 I/O General-purpose digital I/O/LCD segment output (see Note ) P3.7/S 22 I/O General-purpose digital I/O/LCD segment output (see Note ) NOTE : LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits. POST OFFICE BOX DALLAS, TEXAS

8 Terminal Functions (Continued) MSP43x45, MSP43x47 (continued) TERMINAL NAME NO. I/O DESCRIPTION P4./S9 2 I/O General-purpose digital I/O/LCD segment output 9 (see Note ) P4./S8 2 I/O General-purpose digital I/O/LCD segment output 8 (see Note ) P4.2/S7 9 I/O General-purpose digital I/O/LCD segment output 7 (see Note ) P4.3/S6 8 I/O General-purpose digital I/O/LCD segment output 6 (see Note ) P4.4/S5 7 I/O General-purpose digital I/O/LCD segment output 5 (see Note ) P4.5/S4 6 I/O General-purpose digital I/O/LCD segment output 4 (see Note ) P4.6/S3 5 I/O General-purpose digital I/O/LCD segment output 3 (see Note ) P4.7/S2 4 I/O General-purpose digital I/O/LCD segment output 2 (see Note ) P5./S 3 I/O General-purpose digital I/O/LCD segment output (see Note ) P5./S 2 I/O General-purpose digital I/O/LCD segment output (see Note ) COM 36 O Common output. COM 3 are used for LCD backplanes P5.2/COM 37 I/O General-purpose digital I/O/common output. COM 3 are used for LCD backplanes P5.3/COM2 38 I/O General-purpose digital I/O/common output. COM 3 are used for LCD backplanes P5.4/COM3 39 I/O General-purpose digital I/O/common output. COM 3 are used for LCD backplanes R3 4 I Input port of fourth positive (lowest) analog LCD level (V5) P5.5/R3 4 I/O General-purpose digital I/O/input port of third most positive analog LCD level (V4 or V3) P5.6/R23 42 I/O General-purpose digital I/O/input port of second most positive analog LCD level (V2) P5.7/R33 43 I/O General-purpose digital I/O/output port of most positive analog LCD level (V) P6. 59 I/O General-purpose digital I/O P6. 6 I/O General-purpose digital I/O P6.2 6 I/O General-purpose digital I/O P6.3 2 I/O General-purpose digital I/O P6.4 3 I/O General-purpose digital I/O P6.5 4 I/O General-purpose digital I/O P6.6 5 I/O General-purpose digital I/O P6.7/SVSIN 6 I/O General-purpose digital I/O/SVS, analog input RST/NMI 58 I Reset input or nonmaskable interrupt input port TCK 57 I Test clock. TCK is the clock input port for device programming and test. TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI. TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal. TMS 56 I Test mode select. TMS is used as an input port for device programming and test. XIN 8 I Input port for crystal oscillator XT. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT. QFN Pad NA NA QFN package pad connection to VSS recommended. NOTE : LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits. 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 short-form description CPU The MSP43 CPU has a 6-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 6 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 5 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table shows examples of the three types of instruction formats; the address modes are listed in Table 2. Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R SP/R SR/CG/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R R R2 R3 R4 R5 Table. Instruction Word Formats Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 > R5 Single operands, destination only e.g. CALL R8 PC >(TOS), R8 > PC Relative jump, un/conditional e.g. JNE Jump-on-equal bit = Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX EXAMPLE OPERATION Register MOV Rs,Rd MOV R,R R > R Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) > M(6+R6) Symbolic (PC relative) MOV EDE,TONI M(EDE) > M(TONI) Absolute MOV &MEM,&TCDAT M(MEM) > M(TCDAT) Indirect M(R) > M(Tab+R6) Indirect autoincrement M(R) > R R + 2 > R Immediate MOV #X,TONI MOV #45,TONI #45 > M(TONI) NOTE: S = source D = destination POST OFFICE BOX DALLAS, TEXAS

10 operating modes The MSP43 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: Active mode AM; All clocks are active Low-power mode (LPM); CPU is disabled ACLK and SMCLK remain active, MCLK is available to modules FLL+ Loop control remains active Low-power mode (LPM); CPU is disabled ACLK and SMCLK remain active, MCLK is available to modules FLL+ Loop control is disabled Low-power mode 2 (LPM2); CPU is disabled MCLK and FLL+ loop control and DCOCLK are disabled DCO s dc-generator remains enabled ACLK remains active Low-power mode 3 (LPM3); CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO s dc-generator is disabled ACLK remains active Low-power mode 4 (LPM4); CPU is disabled ACLK is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO s dc-generator is disabled Crystal oscillator is stopped POST OFFICE BOX DALLAS, TEXAS 75265

11 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the ROM with an address range FFFFh FFEh. The vector contains the 6-bit address of the appropriate interrupt-handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External Reset Watchdog Flash memory WDTIFG KEYV (see Note ) Reset FFFEh 5, highest NMI Oscillator Fault Flash memory access violation NMIIFG (see Notes and 3) OFIFG (see Notes and 3) ACCVIFG (see Notes and 3) (Non)maskable (Non)maskable (Non)maskable FFFCh 4 Timer_A5 (see Note 4) TACCR CCIFG (see Note 2) Maskable FFFAh 3 Timer_A5 (see Note 4) TACCR to TACCR4 CCIFGs and TACTL TAIFG Maskable FFF8h 2 (see Notes and 2) Comparator_A CMPAIFG Maskable FFF6h Watchdog Timer WDTIFG Maskable FFF4h FFF2h 9 FFFh 8 FFEEh 7 Timer_A3/Timer_A3 TACCR/TACCR CCIFG Maskable FFECh 6 (see Note 2) Timer_A3/Timer_A3 TACCR/TACCR and TACCR2/TACCR2 CCIFGs, and TACLT/TACTL TAIFG Maskable FFEAh 5 (see Notes and 2) I/O port P (eight flags) PIFG. to PIFG.7 (see Notes and 2) Maskable FFE8h 4 FFE6h 3 FFE4h 2 I/O port P2 (eight flags) P2IFG. to P2IFG.7 (see Notes and 2) Maskable FFE2h Basic Timer BTIFG Maskable FFEh, lowest NOTES:. Multiple source flags 2. Interrupt flags are located in the module. 3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot. 4. Implemented in MSP43x45 and MSP43x47 devices only. POST OFFICE BOX DALLAS, TEXAS 75265

12 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable and 2 Address h ACCVIE NMIIE OFIE WDTIE rw- rw- rw- rw- Address h BTIE rw- WDTIE: OFIE: NMIIE: ACCVIE: BTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. Oscillator-fault-interrupt enable Nonmaskable-interrupt enable Flash access violation interrupt enable Basic Timer interrupt enable interrupt flag register and 2 Address 2h NMIIFG OFIFG WDTIFG rw- rw- rw-() Address 3h BTIFG rw- WDTIFG: OFIFG: NMIIFG: BTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with V CC power-up, or a reset condition at the RST/NMI pin in reset mode. Flag set on oscillator fault Set via RST/NMI pin Basic Timer interrupt flag module enable registers and 2 Address 4h/5h Legend: rw: rw-: Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset by PUC. SFR Bit Not Present in Device 2 POST OFFICE BOX DALLAS, TEXAS 75265

13 memory organization Memory Interrupt vector Code memory Information memory Boot memory Size Flash Flash Size Flash Size ROM MSP43F42 MSP43F43 MSP43F45 MSP43F47 4KB FFFFh FFEh FFFFh Fh 256 Byte FFh h KB FFFh Ch RAM Size 256 Byte 2FFh 2h Peripherals 6-bit 8-bit 8-bit SFR FFh h FFh h Fh h 8KB FFFFh FFEh FFFFh Eh 256 Byte FFh h KB FFFh Ch 256 Byte 2FFh 2h FFh h FFh h Fh h 6KB FFFFh FFEh FFFFh Ch 256 Byte FFh h KB FFFh Ch 52 Byte 3FFh 2h FFh h FFh h Fh h 32KB FFFFh FFEh FFFFh 8h 256 Byte FFh h KB FFFh Ch KB 5FFh 2h FFh h FFh h Fh h MSP43C42 MSP43C43 Memory Interrupt vector Code memory Size ROM ROM 4KB FFFFh FFEh FFFFh Fh 8KB FFFFh FFEh FFFFh Eh Information memory Size NA NA Boot memory Size NA NA RAM Size 256 Byte 2FFh 2h Peripherals 6-bit 8-bit 8-bit SFR FFh h FFh h Fh h 256 Byte 2FFh 2h FFh h FFh h Fh h bootstrap loader (BSL) The MSP43 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP43 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP43 Bootstrap Loader, Literature Number SLAA89. BSL Function PM, RTD Package Pins Data Transmit 53 - P. Data Receive 52 - P. POST OFFICE BOX DALLAS, TEXAS

14 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: Flash memory has n segments of main memory and two segments of information memory (A and B) of 28 bytes each. Each segment in main memory is 52 bytes in size. Segments to n may be erased in one step, or each segment may be individually erased. Segments A and B can be erased individually, or as a group with segments n. Segments A and B are also called information memory. New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. 4KB 8KB 6KB 32KB FFFFh FEh FDFFh FCh FBFFh FAh F9FFh FFFFh FEh FDFFh FCh FBFFh FAh F9FFh FFFFh FEh FDFFh FCh FBFFh FAh F9FFh FFFFh FEh FDFFh FCh FBFFh FAh F9FFh Segment With Interrupt Vectors Segment Segment 2 Main Memory F4h F3FFh F2h FFFh Fh FFh 8h 7Fh h E4h E3FFh E2h EFFh Eh FFh 8h 7Fh h C4h C3FFh C2h CFFh Ch FFh 8h 7Fh h 84h 83FFh 82h 8FFh 8h FFh 8h 7Fh h Segment n Segment n Segment A Segment B Information Memory 4 POST OFFICE BOX DALLAS, TEXAS 75265

15 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP43x4xx Family User s Guide, literature number SLAU56. oscillator and system clock The clock system in the MSP43x4x family of devices is supported by the FLL+ module that includes support for a Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The FLL+ module provides the following clock signals: Auxiliary clock (ACLK), sourced from a Hz watch crystal or a high frequency crystal. Main clock (MCLK), the system clock used by the CPU. Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8. brownout, supply voltage supervisor The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a fixed level or user selectable level (MSP43x45 & MSP43x47 only) and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, V CC may not have ramped to V CC(min) at that time. The user must insure the default FLL+ settings are not changed until V CC reaches V CC(min). If desired, the SVS circuit can be used to determine when V CC reaches V CC(min). digital I/O There are six 8-bit I/O ports implemented ports P through P6: All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of ports P and P2. Read/write access to port-control registers is supported by all instructions. Basic Timer The Basic Timer has two independent 8-bit timers which can be cascaded to form a 6-bit timer/counter. Both timers can be read and written by software. The Basic Timer can be used to generate periodic interrupts and clock for the LCD module. LCD drive The LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral. POST OFFICE BOX DALLAS, TEXAS

16 watchdog timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. comparator_a The primary function of the comparator_a module is to support precision slope analog to digital conversions, battery voltage supervision, and monitoring of external analog signals. timer_a3/timer_a3 Timer_A3/Timer_A3 is a 6-bit timer/counter with three capture/compare registers. Timer_A3/Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3/Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A3/Timer_A3 Signal Connections Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number 48 - P.5 TACLK/TACLK TACLK ACLK ACLK SMCLK SMCLK Timer NA 48 - P.5 TACLK/TACLK INCLK 53 - P. TA/TA. CCIA 53 - P P. TA/TA. CCIB DVSS GND CCR TA/TA. DVCC VCC 5 - P.2 TA/TA. CCIA 5 - P.2 CAOUT (internal) CCIB DVSS GND CCR TA/TA. DVCC VCC 45 - P2. TA2/TA.2 CCI2A 45 - P2. ACLK (internal) CCI2B DVSS GND CCR2 TA2/TA.2 DVCC VCC 6 POST OFFICE BOX DALLAS, TEXAS 75265

17 timer_a5 (MSP43x45 and MSP43x47 only) Timer_A5 is a 6-bit timer/counter with five capture/compare registers. Timer_A5 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A5 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A5 Signal Connections Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number 32 - P2.5 TACLK TACLK ACLK ACLK SMCLK SMCLK Timer NA 32 - P2.5 TACLK INCLK 49 - P.4 TA. CCIA 49 - P P.3 TA. CCIB DVSS GND CCR TA. DVCC VCC 44 - P2. TA. CCIA 44 - P2. CAOUT (internal) CCIB DVSS GND CCR TA. DVCC VCC 35 - P2.2 TA.2 CCI2A 35 - P2.2 Not Connected CCI2B DVSS GND CCR2 TA.2 DVCC VCC 34 - P2.3 TA.3 CCI3A 34 - P2.3 Not Connected CCI3B DVSS GND CCR3 TA.3 DVCC VCC 33 - P2.4 TA.4 CCI4A 33 - P2.4 Not Connected CCI4B DVSS GND CCR4 TA.4 DVCC VCC POST OFFICE BOX DALLAS, TEXAS

18 peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog Timer control WDTCTL 2h Timer_A5 Timer_A interrupt vector TAIV Eh (MSP43x45 and Timer_A control TACTL 8h MSP43x47 only) Capture/compare control TACCTL 82h Capture/compare control TACCTL 84h Capture/compare control 2 TACCTL2 86h Capture/compare control 3 TACCTL3 88h Capture/compare control 4 TACCTL4 8Ah Reserved Reserved 8Ch 8Eh Timer_A register TAR 9h Capture/compare register TACCR 92h Capture/compare register TACCR 94h Capture/compare register 2 TACCR2 96h Capture/compare register 3 TACCR3 98h Capture/compare register 4 TACCR4 9Ah Reserved Reserved 9Ch 9Eh Timer_A3/Timer_A3 Timer_A/Timer_A interrupt vector TAIV/TAIV 2Eh Timer_A/Timer_A control TACTL/TACTL 6h Capture/compare control TACCTL/TACCTL 62h Capture/compare control TACCTL/TACCTL 64h Capture/compare control 2 TACCTL2/TACCTL2 66h Reserved Reserved Reserved Reserved 68h 6Ah 6Ch 6Eh Timer_A/Timer_A register TAR/TAR 7h Capture/compare register TACCR/TACCR 72h Capture/compare register TACCR/TACCR 74h Capture/compare register 2 TACCR2/TACCR2 76h Reserved Reserved Reserved Reserved 78h 7Ah 7Ch 7Eh Flash Flash control 3 FCTL3 2Ch Flash control 2 FCTL2 2Ah Flash control FCTL 28h 8 POST OFFICE BOX DALLAS, TEXAS 75265

19 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS LCD LCD memory 2 LCDM2 A4h : : : LCD memory 6 LCDM6 Ah LCD memory 5 LCDM5 9Fh : : : LCD memory LCDM 9h LCD control and mode LCDCTL 9h Comparator_A Comparator_A port disable CAPD 5Bh Comparator_A control2 CACTL2 5Ah Comparator_A control CACTL 59h Brownout, SVS SVS control register SVSCTL 56h FLL+ Clock FLL+ Control FLL_CTL 54h FLL+ Control FLL_CTL 53h System clock frequency control SCFQCTL 52h System clock frequency integrator SCFI 5h System clock frequency integrator SCFI 5h Basic Timer BT counter2 BTCNT2 47h BT counter BTCNT 46h BT control BTCTL 4h Port P6 Port P6 selection P6SEL 37h Port P6 direction P6DIR 36h Port P6 output P6OUT 35h Port P6 input P6IN 34h Port P5 Port P5 selection P5SEL 33h Port P5 direction P5DIR 32h Port P5 output P5OUT 3h Port P5 input P5IN 3h Port P4 Port P4 selection P4SEL Fh Port P4 direction P4DIR Eh Port P4 output P4OUT Dh Port P4 input P4IN Ch Port P3 Port P3 selection P3SEL Bh Port P3 direction P3DIR Ah Port P3 output P3OUT 9h Port P3 input P3IN 8h Port P2 Port P2 selection P2SEL 2Eh Port P2 interrupt enable P2IE 2Dh Port P2 interrupt-edge select P2IES 2Ch Port P2 interrupt flag P2IFG 2Bh Port P2 direction P2DIR 2Ah Port P2 output P2OUT 29h Port P2 input P2IN 28h POST OFFICE BOX DALLAS, TEXAS

20 peripheral file map (continued) absolute maximum ratings PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P Port P selection PSEL 26h Port P interrupt enable PIE 25h Port P interrupt-edge select PIES 24h Port P interrupt flag PIFG 23h Port P direction PDIR 22h Port P output POUT 2h Port P input PIN 2h Special Functions SFR module enable 2 ME2 5h SFR module enable ME 4h SFR interrupt flag2 IFG2 3h SFR interrupt flag IFG 2h SFR interrupt enable2 IE2 h SFR interrupt enable IE h Voltage applied at V CC to V SS V to + 4. V Voltage applied to any pin (see Note) V to V CC +.3 V Diode current at any device terminal ±2 ma Storage temperature (unprogrammed device) C to 5 C Storage temperature (programmed device) C to 85 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse. 2 POST OFFICE BOX DALLAS, TEXAS 75265

21 recommended operating conditions Supply voltage during program execution, SVS disabled VCC (AVCC = DVCC = VCC) Supply voltage during program execution, SVS enabled (see Note ), VCC (AVCC = DVCC = VCC) Supply voltage during programming of flash memory, VCC (AVCC = DVCC = VCC) PARAMETER MIN NOM MAX UNITS MSP43x4x V MSP43x4x V MSP43F4x V Supply voltage, VSS (AVSS//2 = DVSS = VSS) V Operating free-air temperature range, TA MSP43x4x 4 85 C LFXT crystal frequency, f(lfxt) (see Note 2) Processor frequency (signal MCLK), f(system) NOTES: LF selected, XTS_FLL= Watch crystal Hz XT selected, XTS_FLL= Ceramic resonator 45 8 khz XT selected, XTS_FLL= Crystal 8 khz VCC =.8 V DC 4.5 VCC = 3.6 V DC 8. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage. POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry. 2. The LFXT oscillator in LF-mode requires a watch crystal. MHz f(system) Maximum Processor Frequency MHz f (MHz) 8 MHz 4.5 MHz Supply Voltage Range, x4x During Program Execution Supply Voltage Range During Programming of the Flash Memory ÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ.8 V 2.7 V 3 V 3.6 V VCC Supply Voltage V Figure. Frequency vs Supply Voltage POST OFFICE BOX DALLAS, TEXAS

22 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into AV CC + DV CC excluding external current, (see Note ) I (AM) I (LPM) I (LPM) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Active mode, f (MCLK) = f (SMCLK) = MHz, f (ACLK) = 32,768 Hz, XTS_FLL = (F4x: Program executes in flash) Low-power mode, (LPM) f (MCLK) = f (SMCLK) =.5 MHz, f (ACLK) = 32,768 Hz, XTS_FLL = FN_8=FN_4=FN_3=FN_2= Low-power mode, (LPM) f (MCLK) = f (SMCLK) = MHz, f (ACLK) = 32,768 Hz, XTS_FLL = FN_8=FN_4=FN_3=FN_2= C4x F4x C4x F4x T A = 4 C to 85 C T A = 4 C to 85 C T A = 4 C to 85 C I (LPM2) Low-power mode, (LPM2) T A = 4 C to 85 C I (LPM3) Low-power mode, (LPM3) (see Note 2) V CC = 2.2 V 6 2 V CC = 3 V 24 3 V CC = 2.2 V 2 25 V CC = 3 V 3 35 V CC = 2.2 V V CC = 3 V 55 7 V CC = 2.2 V 57 7 V CC = 3 V 92 V CC = 2.2 V 4 V CC = 3 V 7 22 T A = 4 C.95.4 T A = C.8.3 T A = 25 C V CC = 2.2 V.7.2 T A = 6 C.95.4 T A = 85 C T A = 4 C..7 T A = C..6 T A = 25 C V CC = 3 V.9.5 T A = 6 C..7 T A = 85 C T A = 4 C..5 I (LPM4) Low-power mode, (LPM4) T A = 25 C V CC = 2.2 V/3 V..5 µa T A = 85 C NOTES:. All inputs are tied to V or V CC. Outputs do not source or sink any current. The current consumption is measured with active Basic Timer and LCD (ACLK selected). The current consumption of the Comparator_A and the SVS module are specified in the respective sections. 2. The LPM3 currents are characterized with a KDS Daishinku DT 38 (6 pf) crystal. current consumption of active mode versus system frequency, F version I (AM) = I (AM) [ MHz] f (System) [MHz] current consumption of active mode versus supply voltage, F version I (AM) = I (AM) [3 V] + 4 µa/v (V CC 3 V) µa µa µa µa µa 22 POST OFFICE BOX DALLAS, TEXAS 75265

23 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs Ports P, P2, P3, P4, P5, and P6 VIT+ VIT Vhys Positive-going input threshold voltage Negative-going input threshold voltage Input voltage hysteresis (VIT+ VIT ) PARAMETER VCC MIN TYP MAX UNIT standard inputs RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI VIL VIH Low-level input voltage High-level input voltage inputs Px.x, TAx/TAx.x 2.2 V..5 3 V V V V.3. 3 V.45 PARAMETER VCC MIN TYP MAX UNIT V V V VSS VSS+.6 V 2.2 V/3 V.8 V CC VCC V PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Port P, P2: P.x to P2.x, External 2.2 V/3 V.5 cycle t(int) External interrupt timing trigger signal for the interrupt flag, 2.2 V 62 (see Note ) ns 3 V 5 t(cap) Timer_A, capture timing TAx/TAx.y f(taext) Timer_A clock frequency externally applied to pin TACLK/TAxCLK, INCLK t(h) = t(l) f(taint) Timer_A clock frequency SMCLK or ACLK signal selected NOTES: 2.2 V 62 3 V V 8 3 V 2.2 V 8 3 V. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles. leakage current (see Note ) PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT Ilkg(P.x) Ilkg(P6.x) NOTES: Leakage current Port P V(P.x) (see Note 2) Port P6 V(P6.x) (see Note 2) 2.2 V/3 V. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The port pin must be selected as an input. ±5 ±5 ns MHz MHz na POST OFFICE BOX DALLAS, TEXAS

24 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs Ports P, P2, P3, P4, P5, and P6 VOH VOL NOTES: PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High-level output voltage Low-level output voltage IOH(max) =.5 ma, VCC = 2.2 V, See Note VCC.25 VCC IOH(max) = 6 ma, VCC = 2.2 V, See Note 2 VCC.6 VCC IOH(max) =.5 ma, VCC = 3 V, See Note VCC.25 VCC IOH(max) = 6 ma, VCC = 3 V, See Note 2 VCC.6 VCC IOL(max) =.5 ma, VCC = 2.2 V, See Note VSS VSS+.25 IOL(max) = 6 ma, VCC = 2.2 V, See Note 2 VSS VSS+.6 IOL(max) =.5 ma, VCC = 3 V, See Note VSS VSS+.25 IOL(max) = 6 ma, VCC = 3 V, See Note 2 VSS VSS+.6. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±2 ma to satisfy the maximum specified voltage drop. 2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±24 ma to satisfy the maximum specified voltage drop. output frequency PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fpx.y ( x 6, y 7) CL = 2 pf, VCC = 2.2 V DC IL = ±.5mA VCC = 3 V DC 2 MHz V V faclk, fmclk, P./TA/MCLK, P.5/TACLK/ACLK CL = 2 pf fsmclk txdc Duty cycle of output frequency VCC = 2.2 V 8 VCC = 3 V 2 P.5/TACLK/ACLK, faclk = flfxt = fxt 4% 6% CL = 2 pf faclk = flfxt = flf 3% 7% VCC = 2.2 V / 3 V faclk = flfxt/n 5% P./TA/MCLK, CL = 2 pf, VCC = 2.2 V / 3 V fmclk = flfxt/n fmclk = fdcoclk 5% 5 ns 5% 5 ns 5% 5% 5%+ 5 ns 5%+ 5 ns MHz 24 POST OFFICE BOX DALLAS, TEXAS 75265

25 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) MSP43x42, MSP43x43 outputs Ports P, P2, P3, P4, P5, and P6 (see Note) IOL Typical Low-Level Output Current ma TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE VCC = 2.2 V P. TA = 25 C TA = 85 C IOL Typical Low-Level Output Current ma TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE VCC = 3 V P. TA = 25 C TA = 85 C VOL Low-Level Output Voltage V Figure VOL Low-Level Output Voltage V Figure 3 IOH Typical High-Level Output Current ma TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE VCC = 2.2 V P. TA = 85 C TA = 25 C VOH High-Level Output Voltage V Figure 4 NOTE A: One output loaded at a time IOH Typical High-Level Output Current ma TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE VCC = 3 V P. TA = 85 C TA = 25 C VOH High-Level Output Voltage V Figure 5 POST OFFICE BOX DALLAS, TEXAS

26 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) MSP43x45, MSP43x47 outputs Ports P, P2, P3, P4, P5, and P6 (see Note) IOL Typical Low-Level Output Current ma TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE VCC = 2.2 V P2.4 TA = 25 C TA = 85 C IOL Typical Low-Level Output Current ma TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE VCC = 3 V P2.4 TA = 85 C TA = 25 C VOL Low-Level Output Voltage V Figure VOL Low-Level Output Voltage V Figure 7 IOH Typical High-Level Output Current ma TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE VCC = 2.2 V P2.4 TA = 85 C 25 TA = 25 C VOH High-Level Output Voltage V Figure 8 NOTE B: One output loaded at a time IOH Typical High-Level Output Current ma TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE VCC = 3 V P2.4 TA = 85 C 45 TA = 25 C VOH High-Level Output Voltage V Figure 9 26 POST OFFICE BOX DALLAS, TEXAS 75265

27 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up LPM3 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f = MHz 6 td(lpm3) Delay time f = 2 MHz VCC = 2.2 V/3 V 6 µs f = 3 MHz 6 RAM (see Note ) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRAMh CPU halted (see Note ).6 V NOTE : This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program execution should take place during this supply voltage condition. LCD PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(33) Voltage at P5.7/R VCC +.2 V(23) Voltage at P5.6/R23 (V33 V3) 2/3 + V3 Analog voltage V(3) Voltage at P5.5/R3 VCC = 3 V (V(33) V(3)) /3 + V(3) V(33) V(3) Voltage at R33/R3 2.5 VCC +.2 I(R3) R3 = VSS No load at all ±2 I(R3) Input leakage P5.5/R3 = VCC/3 segment and common lines, ±2 na I(R23) P5.6/R23 = 2 VCC/3 VCC = 3 V ±2 V(Sxx) V(3) V(3). V(Sxx) Segment line V(3) V(3). V(Sxx2) voltage I(Sxx) = 3 µa, VCC = 3 V V(23) V(23). V(Sxx3) V(33) V(33) +. V V POST OFFICE BOX DALLAS, TEXAS

28 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Comparator_A (see Note ) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(CC) CAON =, CARSEL =, CAREF = VCC = 2.2 V 25 4 VCC = 3 V 45 6 CAON =, CARSEL =, VCC = 2.2 V 3 5 I(Refladder/RefDiode) CAREF = /2/3, No load at P.6/CA and P.7/CA VCC = 3 V 45 7 µaa µaa V(Ref25) V CC node PCA =, CARSEL =, CAREF =, No load at P.6/CA and P.7/CA V CC VCC = 2.2 V / 3 V V(Ref5) V(RefVT) V(IC) V CC node PCA =, CARSEL =, CAREF = 2, V No load at P.6/CA and P.7/CA CC (see Figure and Figure ) Common-mode input voltage range VCC = 2.2V / 3 V PCA =, CARSEL =, CAREF = 3, VCC = 2.2 V No load at P.6/CA and P.7/CA; TA = 85 C VCC = 3. V CAON = VCC = 2. 2V/3 V VCC. V V(offset) Offset voltage See Note 2 VCC = 2.2 V/3 V 3 3 mv Vhys Input hysteresis CAON = VCC = 2.2 V / 3 V.7.4 mv t(response LH) t(response HL) NOTES: TA = 25 C, VCC = 2.2 V Overdrive mv, without filter: CAF = VCC = 3 V TA = 25 C VCC = 2.2 V Overdrive mv, with filter: CAF = VCC = 3 V TA = 25 C VCC = 2.2 V Overdrive mv, without filter: CAF = VCC = 3 V TA = 25 C, VCC = 2.2 V Overdrive mv, with filter: CAF = VCC = 3. V The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. mv ns µss ns µss 28 POST OFFICE BOX DALLAS, TEXAS 75265

29 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 65 REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE 65 REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE VCC = 3 V VCC = 2.2 V V(RefVT) Reference Voltage mv Typical V(RefVT) Reference Voltage mv Typical TA Free-Air Temperature C Figure TA Free-Air Temperature C Figure V VCC CAF CAON Low Pass Filter To Internal Modules V+ V + _ CAOUT Set CAIFG Flag τ 2 µs Figure 2. Block Diagram of Comparator_A Module V Overdrive VCAOUT 4 mv V+ t(response) Figure 3. Overdrive Definition POST OFFICE BOX DALLAS, TEXAS

30 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) POR brownout, reset (see Notes and 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(bor) 2 µs VCC(start) dvcc/dt 3 V/s (see Figure 4).7 V(B_IT ) V V(B_IT ) Vhys(B_IT ) t(reset) NOTES: Brownout dvcc/dt 3 V/s (see Figure 4, Figure 5, Figure 6).7 V dvcc/dt 3 V/s (see Figure 4) mv Pulse length needed at RST/NMI pin to accepted reset internally, VCC = 2.2 V/3 V 2 µs. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT ) + Vhys(B_IT ) is.8 V. 2. During power up, the CPU begins code execution following a period of td(bor) after VCC = V(B_IT ) + Vhys(B_IT ). The default FLL+ settings must not be changed until VCC VCC(min). See the MSP43x4xx Family User s Guide (SLAU56) for more information on the brownout/svs circuit. VCC Vhys(B_IT ) V(B_IT ) VCC(start) td(bor) Figure 4. POR/Brownout Reset (BOR) vs Supply Voltage 3 POST OFFICE BOX DALLAS, TEXAS 75265

31 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) VCC (min) V V cc = 3 V Typical Conditions VCC 3 V VCC(min) tpw. tpw Pulse Width µs ns ns tpw Pulse Width µs Figure 5. V CC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC (min) V V cc = 3 V Typical Conditions VCC 3 V VCC(min) tpw tf = tr. tf tr tpw Pulse Width µs tpw Pulse Width µs Figure 6. V CC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal SVS (supply voltage supervisor/monitor, see Notes and 2) MSP43x42, MSP43x43 only td(svsr) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT dvcc/dt > 3V/ms (see Note 2) 5 5 µs dvcc/dt 3V/ms (see Note 2) 2 µs td(svson) SVSon, switch from to, VCC = 3 V (see Note 2) 2 5 µs V(SVSstart) dvcc/dt 3 V/s (see Figure 7).55.7 V SVS V(SVS_IT ) dvcc/dt 3 V/s (see Figure 7) V Vhys(SVS_IT ) dvcc/dt 3 V/s (see Figure 7) 7 55 mv ICC(SVS) (see Note ) NOTES: VLD (VLD bits are in SVSCTL register), VCC = 2.2V/ 3V 5 µa. The current consumption of the SVS module is not included in the ICC current consumption data. 2. The SVS is not active at power up. POST OFFICE BOX DALLAS, TEXAS

32 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SVS (supply voltage supervisor/monitor, see Notes and 2) MSP43x45, MSP43x47 only PARAMETER TEST CONDITIONS MIN NOM MAX UNIT td(svsr) dvcc/dt > 3 V/ms (see Figure 7) 5 5 µs dvcc/dt 3 V/ms 2 µs td(svson) SVSon, switch from VLD= to VLD, VCC = 3 V 2 5 µs tsettle VLD 2 µs V(SVSstart) VLD, VCC/dt 3 V/s (see Figure 7).55.7 V VLD = mv VCC/dt 3 V/s (see Figure 7) VLD = V(SVS_IT ) V(SVS_IT ) Vhys(SVS_IT ) x.4 x.8 VCC/dt 3 V/s (see Figure 7), external voltage applied on SVSIN VLD = mv VLD = VLD = VLD = VLD = VLD = VLD = VLD = VCC/dt 3 V/s (see Figure 7) VLD = V(SVS_IT ) V VLD = VLD = VLD = VLD = VLD = VLD = VCC/dt 3 V/s (see Figure 7), external voltage applied on SVSIN VLD = ICC(SVS) (see Note ) VLD, VCC = 2.2 V/3 V 5 µa The recommended operating voltage range is limited to 3.6 V. tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD to a different VLD value somewhere between 2 and 5. The overdrive is assumed to be > 5 mv. NOTES:. The current consumption of the SVS module is not included in the ICC current consumption data. 2. The SVS is not active at power up. 32 POST OFFICE BOX DALLAS, TEXAS 75265