description I2C is a registered trademark of Philips Incorporated.

Transcription

1 Low Supply-Voltage Range,.8 V V Ultralow-Power Consumption: Active Mode: 33 µa at MHz, 2.2 V Standby Mode:. µa Off Mode (RAM Retention):.2 µa Five Power-Saving Modes Wake-Up From Standby Mode in less than 6 µs 6-Bit RISC Architecture, 25-ns Instruction Cycle Time Three-Channel Internal DMA 2-Bit A/D Converter With Internal Reference, Sample-and-Hold and Autoscan Feature Dual 2-Bit D/A Converters With Synchronization 6-Bit Timer_A With Three Capture/Compare Registers 6-Bit Timer_B With Three or Seven Capture/Compare-With-Shadow Registers On-Chip Comparator Serial Communication Interface (USART), Functions as Asynchronous UART or Synchronous SPI or I 2 C TM Interface Serial Communication Interface (USART), Functions as Asynchronous UART or Synchronous SPI Interface Supply Voltage Supervisor/Monitor With Programmable Level Detection Brownout Detector Bootstrap Loader I2C is a registered trademark of Philips Incorporated. description Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse Family Members Include: MSP43F55: 6KB+256B Flash Memory 52B RAM MSP43F56: 24KB+256B Flash Memory KB RAM MSP43F57: 32KB+256B Flash Memory, KB RAM MSP43F67: 32KB+256B Flash Memory, KB RAM MSP43F68: 48KB+256B Flash Memory, 2KB RAM MSP43F69: 6KB+256B Flash Memory, 2KB RAM MSP43F6: 32KB+256B Flash Memory 5KB RAM MSP43F6: 48KB+256B Flash Memory KB RAM MSP43F62: 55KB+256B Flash Memory 5KB RAM Available in 64-Pin Quad Flat Pack (QFP) For Complete Module Descriptions, See the MSP43xxx Family User s Guide, Literature Number SLAU49 The Texas Instruments MSP43 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 6-bit RISC CPU, 6-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs. The MSP43x5x/6x/6x series are microcontroller configurations with two built-in 6-bit timers, a fast 2-bit A/D converter, dual 2-bit D/A converter, one or two universal serial synchronous/asynchronous communication interfaces (USART), I 2 C, DMA, and 48 I/O pins. In addition, the MSP43x6x series offers extended RAM addressing for memory-intensive applications and large C-stack requirements. Typical applications include sensor systems, industrial control applications, hand-held meters, etc. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 22 24, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS 75265

2 TA 4 C to 85 C AVAILABLE OPTIONS PACKAGED DEVICES PLASTIC 64-PIN QFP (PM) MSP43F55IPM MSP43F56IPM MSP43F57IPM MSP43F67IPM MSP43F68IPM MSP43F69IPM MSP43F6IPM MSP43F6IPM MSP43F62IPM pin designation, MSP43F55, MSP43F56, and MSP43F57 PM PACKAGE (TOP VIEW) DV CC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6/DAC P6.7/A7/DAC/SVSIN V REF+ XIN XOUT Ve REF+ V REF /Ve REF P./TACLK P./TA P.2/TA P.3/TA2 P.4/SMCLK P5.4/MCLK P5.3 P5.2 P5. P5. P4.7/TBCLK P4.6 P4.5 P4.4 P4.3 P4.2/TB2 P4./TB P4./TB P3.7 P3.6 P3.5/URXD P.5/TA P.6/TA P.7/TA2 P2./ACLK P2./TAINCLK P2.2/CAOUT/TA P2.3/CA/TA P2.4/CA/TA2 P2.5/R OSC P2.6/ADC2CLK/DMAE P2.7/TA P3./STE P3./SIMO/SDA P3.2/SOMI P3.3/UCLK/SCL P3.4/UTXD AV CC DV SS AV SS P6.2/A2 P6./A P6./A RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 pin designation, MSP43F67, MSP43F68, MSP43F69 PM PACKAGE (TOP VIEW) DV CC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6/DAC P6.7/A7/DAC/SVSIN V REF+ XIN XOUT Ve REF+ V REF /Ve REF P./TACLK P./TA P.2/TA P.3/TA2 P.4/SMCLK P5.4/MCLK P5.3/UCLK P5.2/SOMI P5./SIMO P5./STE P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4./TB P4./TB P3.7/URXD P3.6/UTXD P3.5/URXD P.5/TA P.6/TA P.7/TA2 P2./ACLK P2./TAINCLK P2.2/CAOUT/TA P2.3/CA/TA P2.4/CA/TA2 P2.5/R OSC P2.6/ADC2CLK/DMAE P2.7/TA P3./STE P3./SIMO/SDA P3.2/SOMI P3.3/UCLK/SCL P3.4/UTXD AV CC DV SS AV SS P6.2/A2 P6./A P6./A RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK POST OFFICE BOX DALLAS, TEXAS

4 pin designation, MSP43F6, MSP43F6, MSP43F62 PM PACKAGE (TOP VIEW) DV CC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6/DAC P6.7/A7/DAC/SVSIN V REF+ XIN XOUT Ve REF+ V REF /Ve REF P./TACLK P./TA P.2/TA P.3/TA2 P.4/SMCLK P5.4/MCLK P5.3/UCLK P5.2/SOMI P5./SIMO P5./STE P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4./TB P4./TB P3.7/URXD P3.6/UTXD P3.5/URXD P.5/TA P.6/TA P.7/TA2 P2./ACLK P2./TAINCLK P2.2/CAOUT/TA P2.3/CA/TA P2.4/CA/TA2 P2.5/R OSC P2.6/ADC2CLK/DMAE P2.7/TA P3./STE P3./SIMO/SDA P3.2/SOMI P3.3/UCLK/SCL P3.4/UTXD AV CC DV SS AV SS P6.2/A2 P6./A P6./A RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 functional block diagrams MSP43x5x XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P P2 P3 P4 P5 P ROSC XT2IN XT2OUT Oscillator System Clock ACLK SMCLK 32KB Flash 24KB Flash 6KB Flash KB RAM KB RAM 52B RAM ADC2 2-Bit 8 Channels <µs Conv. DAC2 2-Bit 2 Channels Voltage out I/O Port /2 6 I/Os, with Interrupt Capability I/O Port 3/4 6 I/Os I/O Port 5/6 6 I/Os MCLK CPU Incl. 6 Reg. Test JTAG Emulation Module MAB, MAB, 6 Bit6-Bit MDB, MDB, 6 6-Bit MAB, 4 Bit MCB Bus Conv MDB, 8 Bit 4 TMS TCK TDI/TCLK TDO/TDI DMA Controller 3 Channels Watchdog Timer 5/6-Bit Timer_B3 3 CC Reg Shadow Reg Timer_A3 3 CC Reg POR SVS Brownout Comparator A USART UART Mode SPI Mode I2C Mode MSP43x6x XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P P2 P3 P4 P5 P ROSC XT2IN XT2OUT Oscillator System Clock ACLK SMCLK 6KB Flash 48KB Flash 32KB Flash 2KB RAM 2KB RAM KB RAM ADC2 2-Bit 8 Channels <µs Conv. DAC2 2-Bit 2 Channels Voltage out I/O Port /2 6 I/Os, with Interrupt Capability I/O Port 3/4 6 I/Os I/O Port 5/6 6 I/Os MCLK CPU Incl. 6 Reg. Test JTAG Emulation Module MAB, MAB, 6 Bit6-Bit MDB, MDB, 6 6-Bit MAB, 4 Bit MCB Bus Conv MDB, 8 Bit 4 TMS TCK TDI/TCLK TDO/TDI Hardware Multiplier MPY, MPYS MAC,MACS DMA Controller 3 Channels Watchdog Timer 5/6-Bit Timer_B7 7 CC Reg Shadow Reg Timer_A3 3 CC Reg POR SVS Brownout Comparator A USART UART Mode SPI Mode I2C Mode USART UART Mode SPI Mode POST OFFICE BOX DALLAS, TEXAS

6 functional block diagrams (continued) MSP43x6x XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P P2 P3 P4 P5 P ROSC XT2IN XT2OUT Oscillator System Clock ACLK SMCLK 55KB Flash 48KB Flash 32KB Flash 5KB RAM KB RAM 5KB RAM ADC2 2-Bit 8 Channels <µs Conv. DAC2 2-Bit 2 Channels Voltage out I/O Port /2 6 I/Os, with Interrupt Capability I/O Port 3/4 6 I/Os I/O Port 5/6 6 I/Os MCLK CPU Incl. 6 Reg. Test JTAG Emulation Module MAB, MAB, 6 Bit6-Bit MDB, MDB, 6 6-Bit MAB, 4 Bit MCB Bus Conv MDB, 8 Bit 4 TMS TCK TDI/TCLK TDO/TDI Hardware Multiplier MPY, MPYS MAC,MACS DMA Controller 3 Channels Watchdog Timer 5/6-Bit Timer_B7 7 CC Reg Shadow Reg Timer_A3 3 CC Reg POR SVS Brownout Comparator A USART UART Mode SPI Mode I2C Mode USART UART Mode SPI Mode 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 TERMINAL NAME NO. I/O Terminal Functions DESCRIPTION AVCC 64 Analog supply voltage, positive terminal. Supplies only the analog portion of ADC2 and DAC2. AVSS 62 Analog supply voltage, negative terminal. Supplies only the analog portion of ADC2 and DAC2. DVCC Digital supply voltage, positive terminal. Supplies all digital parts. DVSS 63 Digital supply voltage, negative terminal. Supplies all digital parts. P./TACLK 2 I/O General-purpose digital I/O pin/timer_a, clock signal TACLK input P./TA 3 I/O General-purpose digital I/O pin/timer_a, capture: CCIA input, compare: Out output/bsl transmit P.2/TA 4 I/O General-purpose digital I/O pin/timer_a, capture: CCIA input, compare: Out output P.3/TA2 5 I/O General-purpose digital I/O pin/timer_a, capture: CCI2A input, compare: Out2 output P.4/SMCLK 6 I/O General-purpose digital I/O pin/smclk signal output P.5/TA 7 I/O General-purpose digital I/O pin/timer_a, compare: Out output P.6/TA 8 I/O General-purpose digital I/O pin/timer_a, compare: Out output P.7/TA2 9 I/O General-purpose digital I/O pin/timer_a, compare: Out2 output P2./ACLK 2 I/O General-purpose digital I/O pin/aclk output P2./TAINCLK 2 I/O General-purpose digital I/O pin/timer_a, clock signal at INCLK P2.2/CAOUT/TA 22 I/O General-purpose digital I/O pin/timer_a, capture: CCIB input/comparator_a output/bsl receive P2.3/CA/TA 23 I/O General-purpose digital I/O pin/timer_a, compare: Out output/comparator_a input P2.4/CA/TA2 24 I/O General-purpose digital I/O pin/timer_a, compare: Out2 output/comparator_a input P2.5/Rosc 25 I/O General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency P2.6/ADC2CLK/ 26 I/O General-purpose digital I/O pin/conversion clock 2-bit ADC/DMA channel external trigger DMAE P2.7/TA 27 I/O General-purpose digital I/O pin/timer_a, compare: Out output P3./STE 28 I/O General-purpose digital I/O pin/slave transmit enable USART/SPI mode P3./SIMO/SDA 29 I/O General-purpose digital I/O pin/slave in/master out of USART/SPI mode, I2C data USART/I2C mode P3.2/SOMI 3 I/O General-purpose digital I/O pin/slave out/master in of USART/SPI mode P3.3/UCLK/SCL 3 I/O General-purpose digital I/O pin/external clock input USART/UART or SPI mode, clock output USART/SPI mode, I2C clock USART/I2C mode P3.4/UTXD 32 I/O General-purpose digital I/O pin/transmit data out USART/UART mode P3.5/URXD 33 I/O General-purpose digital I/O pin/receive data in USART/UART mode P3.6/UTXD 34 I/O General-purpose digital I/O pin/transmit data out USART/UART mode P3.7/URXD 35 I/O General-purpose digital I/O pin/receive data in USART/UART mode P4./TB 36 I/O General-purpose digital I/O pin/timer_b, capture: CCIA/B input, compare: Out output P4./TB 37 I/O General-purpose digital I/O pin/timer_b, capture: CCIA/B input, compare: Out output P4.2/TB2 38 I/O General-purpose digital I/O pin/timer_b, capture: CCI2A/B input, compare: Out2 output P4.3/TB3 39 I/O General-purpose digital I/O pin/timer_b, capture: CCI3A/B input, compare: Out3 output P4.4/TB4 4 I/O General-purpose digital I/O pin/timer_b, capture: CCI4A/B input, compare: Out4 output P4.5/TB5 4 I/O General-purpose digital I/O pin/timer_b, capture: CCI5A/B input, compare: Out5 output P4.6/TB6 42 I/O General-purpose digital I/O pin/timer_b, capture: CCI6A input, compare: Out6 output P4.7/TBCLK 43 I/O General-purpose digital I/O pin/timer_b, clock signal TBCLK input P5./STE 44 I/O General-purpose digital I/O pin/slave transmit enable USART/SPI mode P5./SIMO 45 I/O General-purpose digital I/O pin/slave in/master out of USART/SPI mode P5.2/SOMI 46 I/O General-purpose digital I/O pin/slave out/master in of USART/SPI mode P5.3/UCLK 47 I/O General-purpose digital I/O pin/external clock input USART/UART or SPI mode, clock output USART/SPI mode 6x, 6x devices only POST OFFICE BOX DALLAS, TEXAS

8 TERMINAL NAME NO. I/O Terminal Functions (Continued) DESCRIPTION P5.4/MCLK 48 I/O General-purpose digital I/O pin/main system clock MCLK output P5.5/SMCLK 49 I/O General-purpose digital I/O pin/submain system clock SMCLK output P5.6/ACLK 5 I/O General-purpose digital I/O pin/auxiliary clock ACLK output P5.7/TBOUTH/ SVSOUT 5 I/O General-purpose digital I/O pin/switch all PWM digital output ports to high impedance Timer_B TB to TB6/SVS comparator output P6./A 59 I/O General-purpose digital I/O pin/analog input a 2-bit ADC P6./A 6 I/O General-purpose digital I/O pin/analog input a 2-bit ADC P6.2/A2 6 I/O General-purpose digital I/O pin/analog input a2 2-bit ADC P6.3/A3 2 I/O General-purpose digital I/O pin/analog input a3 2-bit ADC P6.4/A4 3 I/O General-purpose digital I/O pin/analog input a4 2-bit ADC P6.5/A5 4 I/O General-purpose digital I/O pin/analog input a5 2-bit ADC P6.6/A6/DAC 5 I/O General-purpose digital I/O pin/analog input a6 2-bit ADC/DAC2. output P6.7/A7/DAC/ 6 I/O General-purpose digital I/O pin/analog input a7 2-bit ADC/DAC2. output/svs input SVSIN RST/NMI 58 I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices). TCK 57 I Test clock. TCK is the clock input port for device programming test and bootstrap loader start TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal TMS 56 I Test mode select. TMS is used as an input port for device programming and test. VeREF+ I Input for an external reference voltage VREF+ 7 O Output of positive terminal of the reference voltage in the ADC2 VREF /VeREF I Negative terminal for the reference voltage for both sources, the internal reference voltage, or an external applied reference voltage XIN 8 I Input port for crystal oscillator XT. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT XT2IN 53 I Input port for crystal oscillator XT2. Only standard crystals can be connected. XT2OUT 52 O Output terminal of crystal oscillator XT2 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 short-form description CPU The MSP43 CPU has a 6-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 6 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 5 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table shows examples of the three types of instruction formats; the address modes are listed in Table 2. Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R SP/R SR/CG/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R R R2 R3 R4 R5 Table. Instruction Word Formats Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 > R5 Single operands, destination only e.g. CALL R8 PC >(TOS), R8 > PC Relative jump, un/conditional e.g. JNE Jump-on-equal bit = Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX EXAMPLE OPERATION Register MOV Rs,Rd MOV R,R R > R Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) > M(6+R6) Symbolic (PC relative) MOV EDE,TONI M(EDE) > M(TONI) Absolute MOV &MEM,&TCDAT M(MEM) > M(TCDAT) Indirect M(R) > M(Tab+R6) Indirect autoincrement M(R) > R R + 2 > R Immediate MOV #X,TONI MOV #45,TONI #45 > M(TONI) NOTE: S = source D = destination POST OFFICE BOX DALLAS, TEXAS

10 operating modes The MSP43 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: Active mode AM; All clocks are active Low-power mode (LPM); CPU is disabled ACLK and SMCLK remain active. MCLK is disabled Low-power mode (LPM); CPU is disabled ACLK and SMCLK remain active. MCLK is disabled DCO s dc-generator is disabled if DCO not used in active mode Low-power mode 2 (LPM2); CPU is disabled MCLK and SMCLK are disabled DCO s dc-generator remains enabled ACLK remains active Low-power mode 3 (LPM3); CPU is disabled MCLK and SMCLK are disabled DCO s dc-generator is disabled ACLK remains active Low-power mode 4 (LPM4); CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO s dc-generator is disabled Crystal oscillator is stopped POST OFFICE BOX DALLAS, TEXAS 75265

11 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range FFFFh FFEh. The vector contains the 6-bit address of the appropriate interrupt-handler instruction sequence. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External Reset Watchdog Flash memory WDTIFG KEYV (see Note ) Reset FFFEh 5, highest NMI Oscillator Fault Flash memory access violation Timer_B7 (see Note 5) Timer_B7 (see Note 5) NMIIFG (see Notes & 3) OFIFG (see Notes & 3) ACCVIFG (see Notes & 3) TBCCR CCIFG (see Note 2) TBCCR to TBCCR6 CCIFGs, TBIFG (see Notes & 2) (Non)maskable (Non)maskable (Non)maskable FFFCh 4 Maskable FFFAh 3 Maskable FFF8h 2 Comparator_A CAIFG Maskable FFF6h Watchdog timer WDTIFG Maskable FFF4h USART receive URXIFG Maskable FFF2h 9 USART transmit UTXIFG Maskable FFFh 8 I2C transmit/receive/others I2CIFG (see Note 4) ADC2 ADC2IFG Maskable FFEEh 7 (see Notes & 2) Timer_A3 TACCR CCIFG Maskable FFECh 6 (see Note 2) Timer_A3 TACCR and TACCR2 CCIFGs, TAIFG Maskable FFEAh 5 (see Notes & 2) I/O port P (eight flags) PIFG. to PIFG.7 (see Notes & 2) Maskable FFE8h 4 USART receive URXIFG Maskable FFE6h 3 USART transmit UTXIFG Maskable FFE4h 2 I/O port P2 (eight flags) P2IFG. to P2IFG.7 (see Notes & 2) Maskable FFE2h NOTES: DAC2 DMA DAC2_IFG, DAC2_IFG DMAIFG, DMAIFG, DMA2IFG (see Notes & 2) Maskable FFEh, lowest. Multiple source flags 2. Interrupt flags are located in the module. 3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. 4. I2C interrupt flags located in the module 5. Timer_B7 in MSP43x6x/6x family has 7 CCRs; Timer_B3 in MSP43x5x family has 3 CCRs; in Timer_B3 there are only interrupt flags TBCCR, and 2 CCIFGs and the interrupt-enable bits TBCCR, and 2 CCIEs. POST OFFICE BOX DALLAS, TEXAS 75265

12 special function registers Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access. interrupt enable and 2 Address h UTXIE URXIE ACCVIE NMIIE OFIE WDTIE rw- rw- rw- rw- rw- rw- WDTIE: OFIE: NMIIE: ACCVIE: URXIE: UTXIE: Address h Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as general-purpose timer. Oscillator-fault-interrupt enable Nonmaskable-interrupt enable Flash memory access violation interrupt enable USART: UART and SPI receive-interrupt enable USART: UART and SPI transmit-interrupt enable UTXIE URXIE rw- rw- URXIE : USART: UART and SPI receive-interrupt enable UTXIE : USART: UART and SPI transmit-interrupt enable URXIE and UTXIE are not present in MSP43x5x devices. interrupt flag register and 2 Address h UTXIFG URXIFG NMIIFG OFIFG WDTIFG rw- rw- rw- rw- rw-() WDTIFG: OFIFG: NMIIFG: URXIFG: UTXIFG: Address 3h Set on watchdog-timer overflow (in watchdog mode) or security key violation Reset on V CC power-on, or a reset condition at the RST/NMI pin in reset mode Flag set on oscillator fault Set via RST/NMI pin USART: UART and SPI receive flag USART: UART and SPI transmit flag UTXIFG URXIFG rw- rw- URXIFG : USART: UART and SPI receive flag UTXIFG : USART: UART and SPI transmit flag URXIFG and UTXIFG are not present in MSP43x5x devices. 2 POST OFFICE BOX DALLAS, TEXAS 75265

13 module enable registers and 2 Address 4h UTXE URXE USPIE rw- rw- URXE: UTXE: USPIE: Address 5h USART: UART mode receive enable USART: UART mode transmit enable USART: SPI mode transmit and receive enable UTXE URXE USPIE rw- rw- URXE : USART: UART mode receive enable UTXE : USART: UART mode transmit enable USPIE : USART: SPI mode transmit and receive enable URXE, UTXE, and USPIE are not present in MSP43x5x devices. Legend: rw: rw-: Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset by PUC. SFR Bit Not Present in Device POST OFFICE BOX DALLAS, TEXAS

14 memory organization (MSP43F5x) Memory Main: interrupt vector Main: code memory Information memory Boot memory Size Flash Flash Size Flash Size ROM MSP43F55 MSP43F56 MSP43F57 6KB FFFFh FFEh FFFFh Ch 256 Byte FFh h KB FFFh Ch RAM Size 52B 3FFh 2h Peripherals 6-bit 8-bit 8-bit SFR FFh h FFh h Fh h 24KB FFFFh FFEh FFFFh Ah 256 Byte FFh h KB FFFh Ch KB 5FFh 2h FFh h FFh h Fh h 32KB FFFFh FFEh FFFFh 8h 256 Byte FFh h KB FFFh Ch KB 5FFh 2h FFh h FFh h Fh h memory organization (MSP43F6x) Memory Main: interrupt vector Main: code memory Information memory Boot memory Size Flash Flash Size Flash Size ROM MSP43F67 MSP43F68 MSP43F69 32KB FFFFh FFEh FFFFh 8h 256 Byte FFh h KB FFFh Ch RAM Size KB 5FFh 2h Peripherals 6-bit 8-bit 8-bit SFR FFh h FFh h Fh h 48KB FFFFh FFEh FFFFh 4h 256 Byte FFh h KB FFFh Ch 2KB 9FFh 2h FFh h FFh h Fh h 6KB FFFFh FFEh FFFFh h 256 Byte FFh h KB FFFh Ch 2KB 9FFh 2h FFh h FFh h Fh h memory organization (MSP43F6x) Memory Main: interrupt vector Main: code memory Size Flash Flash MSP43F6 MSP43F6 MSP43F62 32KB FFFFh FFEh FFFFh 8h RAM (Total) Size 5KB 24FFh h Extended Size 3KB 24FFh 9h Mirrored Size 2KB 8FFh h Information memory Boot memory RAM (mirrored at 8FFh - h) Peripherals Size Flash Size ROM Size 6-bit 8-bit 8-bit SFR 256 Byte FFh h KB FFFh Ch 2KB 9FFh 2h FFh h FFh h Fh h 48KB FFFFh FFEh FFFFh 4h KB 38FFh h 8KB 38FFh 9h 2KB 8FFh h 256 Byte FFh h KB FFFh Ch 2KB 9FFh 2h FFh h FFh h Fh h 55KB FFFFh FFEh FFFFh 25h 5KB 24FFh h 3KB 24FFh 9h 2KB 8FFh h 256 Byte FFh h KB FFFh Ch 2KB 9FFh 2h FFh h FFh h Fh h 4 POST OFFICE BOX DALLAS, TEXAS 75265

15 bootstrap loader (BSL) The MSP43 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP43 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP43 Bootstrap Loader, Literature Number SLAA89. flash memory BSL Function PM Package Pins Data Transmit 3 - P. Data Receive 22 - P2.2 The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: Flash memory has n segments of main memory and two segments of information memory (A and B) of 28 bytes each. Each segment in main memory is 52 bytes in size. Segments to n may be erased in one step, or each segment may be individually erased. Segments A and B can be erased individually, or as a group with segments n. Segments A and B are also called information memory. New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. MSP43F5x and MSP43F6x MSP43F6x 6KB 24KB 32KB 48KB 6KB 32KB 48KB 55KB FFFFh FEh FDFFh FFFFh FEh FDFFh FFFFh FEh FDFFh FFFFh FEh FDFFh FFFFh FEh FDFFh FFFFh FEh FDFFh FFFFh FEh FDFFh FFFFh FEh FDFFh Segment w/ Interrupt Vectors Segment FCh FBFFh FCh FBFFh FCh FBFFh FCh FBFFh FCh FBFFh FCh FBFFh FCh FBFFh FCh FBFFh Segment 2 FAh F9FFh FAh F9FFh FAh F9FFh FAh F9FFh FAh F9FFh FAh F9FFh FAh F9FFh FAh F9FFh Main Memory C4h C3FFh C2h CFFh Ch FFh 8h 7Fh h A4h A3FFh A2h AFFh Ah FFh 8h 7Fh h 84h 83FFh 82h 8FFh 8h FFh 8h 7Fh h 44h 43FFh 42h 4FFh 4h FFh 8h 7Fh h 4h 3FFh 2h FFh h FFh 8h 7Fh h 84h 83FFh 82h 8FFh 8h 24FFh h FFh 8h 7Fh h 44h 43FFh 42h 4FFh 4h 38FFh h FFh 8h 7Fh h 28h 27FFh 26h 25FFh 25h 24FFh h FFh 8h 7Fh h Segment n- Segment n Segment A Segment B RAM ( F6x only) Info Memory MSP43F69 and MSP43F62 flash segment n = 256 bytes. POST OFFICE BOX DALLAS, TEXAS

16 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the MSP43xxx Family User s Guide, literature number SLAU49. DMA controller The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC2 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral. oscillator and system clock The clock system in the MSP43x5x and MSP43x6x(x) family of devices is supported by the basic clock module that includes support for a Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the following clock signals: Auxiliary clock (ACLK), sourced from a Hz watch crystal or a high frequency crystal. Main clock (MCLK), the system clock used by the CPU. Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. brownout, supply voltage supervisor The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, V CC may not have ramped to V CC(min) at that time. The user must insure the default DCO settings are not changed until V CC reaches V CC(min). If desired, the SVS circuit can be used to determine when V CC reaches V CC(min). digital I/O There are six 8-bit I/O ports implemented ports P through P6: All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of ports P and P2. Read/write access to port-control registers is supported by all instructions. watchdog timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. hardware multiplier (MSP43x6x/6x Only) The multiplication operation is supported by a dedicated peripheral module. The module performs 6 6, 6 8, 8 6, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required. 6 POST OFFICE BOX DALLAS, TEXAS 75265

17 USART The MSP43x5x and the MSP43x6x(x) have one hardware universal synchronous/asynchronous receive transmit (USART) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin), asynchronous UART and I2C communication protocols using double-buffered transmit and receive channels. The I 2 C support is compliant with the Philips I 2 C specification version 2. and supports standard mode (up to kbps) and fast mode (up to 4 kbps). In addition, 7-bit and -bit device addressing modes are supported, as well as master and slave modes. The USART also supports 6-bit-wide I 2 C data transfers and has two dedicated DMA channels to maximize bus throughput. Extensive interrupt capability is also given in the I 2 C mode. USART (MSP43x6x/6x Only) The MSP43x6x(x) devices have a second hardware universal synchronous/asynchronous receive transmit (USART) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. With the exception of I2C support, operation of USART is identical to USART. timer_a3 Timer_A3 is a 6-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A3 Signal Connections Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number 2 - P. TACLK TACLK ACLK ACLK SMCLK SMCLK Timer NA 2 - P2. TAINCLK INCLK 3 - P. TA CCIA 3 - P P2.2 TA CCIB 7 - P.5 CCR TA DVSS GND 27 - P2.7 DVCC VCC 4 - P.2 TA CCIA 4 - P.2 CAOUT (internal) CCIB 8 - P.6 CCR TA DVSS GND 23 - P2.3 DVCC VCC ADC2 (internal) 5 - P.3 TA2 CCI2A 5 - P.3 ACLK (internal) CCI2B 9 - P.7 CCR2 TA2 DVSS GND 24 - P2.4 DVCC VCC timer_b3 (MSP43x5x Only) Timer_B3 is a 6-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. POST OFFICE BOX DALLAS, TEXAS

18 timer_b7 (MSP43x6x/6x Only) Timer_B7 is a 6-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_B3/B7 Signal Connections Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number 43 - P4.7 TBCLK TBCLK ACLK ACLK SMCLK SMCLK Timer NA 43 - P4.7 TBCLK INCLK 36 - P4. TB CCIA 36 - P P4. TB CCIB ADC2 (internal) CCR TB DVSS GND DVCC VCC 37 - P4. TB CCIA 37 - P P4. TB CCIB ADC2 (internal) CCR TB DVSS GND DVCC VCC 38 - P4.2 TB2 CCI2A 38 - P P4.2 TB2 CCI2B DVSS GND CCR2 TB2 DVCC VCC 39 - P4.3 TB3 CCI3A 39 - P P4.3 TB3 CCI3B DVSS GND CCR3 TB3 DVCC VCC 4 - P4.4 TB4 CCI4A 4 - P P4.4 TB4 CCI4B DVSS GND CCR4 TB4 DVCC VCC 4 - P4.5 TB5 CCI5A 4 - P P4.5 TB5 CCI5B DVSS GND CCR5 TB5 DVCC VCC 42 - P4.6 TB6 CCI6A 42 - P4.6 ACLK (internal) CCI6B DVSS GND CCR6 TB6 DVCC VCC Timer_B3 implements three capture/compare blocks (CCR, CCR and CCR2 only). 8 POST OFFICE BOX DALLAS, TEXAS 75265

19 comparator_a The primary function of the comparator_a module is to support precision slope analog to digital conversions, battery voltage supervision, and monitoring of external analog signals. ADC2 The ADC2 module supports fast, 2-bit analog-to-digital conversions. The module implements a 2-bit SAR core, sample select control, reference generator and a 6 word conversion-and-control buffer. The conversion-and-control buffer allows up to 6 independent ADC samples to be converted and stored without any CPU intervention. DAC2 The DAC2 module is a 2-bit, R-ladder, voltage output DAC. The DAC2 may be used in 8- or 2-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC2 modules are present, they may be grouped together for synchronous operation. POST OFFICE BOX DALLAS, TEXAS

20 peripheral file map PERIPHERAL FILE MAP DMA DMA channel 2 transfer size DMA2SZ F6h DMA channel 2 destination address DMA2DA F4h DMA channel 2 source address DMA2SA F2h DMA channel 2 control DMA2CTL Fh DMA channel transfer size DMASZ EEh DMA channel destination address DMADA ECh DMA channel source address DMASA EAh DMA channel control DMACTL E8h DMA channel transfer size DMASZ E6h DMA channel destination address DMADA E4h DMA channel source address DMASA E2h DMA channel control DMACTL Eh DMA module control DMACTL 24h DMA module control DMACTL 22h DAC2 DAC2_ data DAC2_DAT CAh DAC2_ control DAC2_CTL C2h DAC2_ data DAC2_DAT C8h DAC2_ control DAC2_CTL Ch ADC2 Interrupt-vector-word register ADC2IV A8h Inerrupt-enable register ADC2IE A6h Inerrupt-flag register ADC2IFG A4h Control register ADC2CTL A2h Control register ADC2CTL Ah Conversion memory 5 ADC2MEM5 5Eh Conversion memory 4 ADC2MEM4 5Ch Conversion memory 3 ADC2MEM3 5Ah Conversion memory 2 ADC2MEM2 58h Conversion memory ADC2MEM 56h Conversion memory ADC2MEM 54h Conversion memory 9 ADC2MEM9 52h Conversion memory 8 ADC2MEM8 5h Conversion memory 7 ADC2MEM7 4Eh Conversion memory 6 ADC2MEM6 4Ch Conversion memory 5 ADC2MEM5 4Ah Conversion memory 4 ADC2MEM4 48h Conversion memory 3 ADC2MEM3 46h Conversion memory 2 ADC2MEM2 44h Conversion memory ADC2MEM 42h Conversion memory ADC2MEM 4h 2 POST OFFICE BOX DALLAS, TEXAS 75265

21 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) ADC2 ADC memory-control register5 ADC2MCTL5 8Fh (continued) ADC memory-control register4 ADC2MCTL4 8Eh ADC memory-control register3 ADC2MCTL3 8Dh ADC memory-control register2 ADC2MCTL2 8Ch ADC memory-control register ADC2MCTL 8Bh ADC memory-control register ADC2MCTL 8Ah ADC memory-control register9 ADC2MCTL9 89h ADC memory-control register8 ADC2MCTL8 88h ADC memory-control register7 ADC2MCTL7 87h ADC memory-control register6 ADC2MCTL6 86h ADC memory-control register5 ADC2MCTL5 85h ADC memory-control register4 ADC2MCTL4 84h ADC memory-control register3 ADC2MCTL3 83h ADC memory-control register2 ADC2MCTL2 82h ADC memory-control register ADC2MCTL 8h ADC memory-control register ADC2MCTL 8h Timer_B7/ Capture/compare register 6 TBCCR6 9Eh Timer_B3 Capture/compare register 5 TBCCR5 9Ch (see Note ) Capture/compare register 4 TBCCR4 9Ah Capture/compare register 3 TBCCR3 98h Capture/compare register 2 TBCCR2 96h Capture/compare register TBCCR 94h Capture/compare register TBCCR 92h Timer_B register TBR 9h Capture/compare control 6 TBCCTL6 8Eh Capture/compare control 5 TBCCTL5 8Ch Capture/compare control 4 TBCCTL4 8Ah Capture/compare control 3 TBCCTL3 88h Capture/compare control 2 TBCCTL2 86h Capture/compare control TBCCTL 84h Capture/compare control TBCCTL 82h Timer_B control TBCTL 8h Timer_B interrupt vector TBIV Eh Timer_A3 Reserved 7Eh NOTE : Reserved Reserved Reserved 7Ch 7Ah 78h Capture/compare register 2 TACCR2 76h Capture/compare register TACCR 74h Capture/compare register TACCR 72h Timer_A register TAR 7h Reserved Reserved Reserved Reserved 6Eh 6Ch 6Ah 68h Timer_B7 in MSP43x6x/6x family has 7 CCRs, Timer_B3 in MSP43x5x family has 3 CCRs. POST OFFICE BOX DALLAS, TEXAS

22 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) Timer_A3 Capture/compare control 2 TACCTL2 66h (continued) Capture/compare control TACCTL 64h Capture/compare control TACCTL 62h Timer_A control TACTL 6h Timer_A interrupt vector TAIV 2Eh Hardware Sum extend SUMEXT 3Eh Multiplier Result high word RESHI 3Ch (MSP43x6x and Result low word RESLO 3Ah MSP43x6x only) Second operand OP2 38h Multiply signed +accumulate/operand MACS 36h Multiply+accumulate/operand MAC 34h Multiply signed/operand MPYS 32h Multiply unsigned/operand MPY 3h Flash Flash control 3 FCTL3 2Ch Flash control 2 FCTL2 2Ah Flash control FCTL 28h Watchdog Watchdog Timer control WDTCTL 2h USART Transmit buffer UTXBUF 7Fh (MSP43x6x and Receive buffer URXBUF 7Eh MSP43x6x Baud rate UBR 7Dh only) Baud rate UBR 7Ch Modulation control UMCTL 7Bh Receive control URCTL 7Ah Transmit control UTCTL 79h USART control UCTL 78h USART Transmit buffer UTXBUF 77h (UART or Receive buffer URXBUF 76h SPI mode) Baud rate UBR 75h Baud rate UBR 74h Modulation control UMCTL 73h Receive control URCTL 72h Transmit control UTCTL 7h USART control UCTL 7h USART I2C interrupt vector I2CIV Ch (I2C 2 mode) I2C slave address I2CSA Ah I2C own address I2COA 8h I2C data I2CDR 76h I2C SCLL I2CSCLL 75h I2C SCLH I2CSCLH 74h I2C PSC I2CPSC 73h I2C data control I2CDCTL 72h I2C transfer control I2CTCTL 7h USART control UCTL 7h I2C data count I2CNDAT 52h I2C interrupt flag I2CIFG 5h I2C interrupt enable I2CIE 5h 22 POST OFFICE BOX DALLAS, TEXAS 75265

23 peripheral file map (continued) PERIPHERAL FILE MAP (CONTINUED) Comparator_A Comparator_A port disable CAPD 5Bh Comparator_A control2 CACTL2 5Ah Comparator_A control CACTL 59h Basic Clock Basic clock system control2 BCSCTL2 58h Basic clock system control BCSCTL 57h DCO clock frequency control DCOCTL 56h BrownOUT, SVS SVS control register (reset by brownout signal) SVSCTL 55h Port P6 Port P6 selection P6SEL 37h Port P6 direction P6DIR 36h Port P6 output P6OUT 35h Port P6 input P6IN 34h Port P5 Port P5 selection P5SEL 33h Port P5 direction P5DIR 32h Port P5 output P5OUT 3h Port P5 input P5IN 3h Port P4 Port P4 selection P4SEL Fh Port P4 direction P4DIR Eh Port P4 output P4OUT Dh Port P4 input P4IN Ch Port P3 Port P3 selection P3SEL Bh Port P3 direction P3DIR Ah Port P3 output P3OUT 9h Port P3 input P3IN 8h Port P2 Port P2 selection P2SEL 2Eh Port P2 interrupt enable P2IE 2Dh Port P2 interrupt-edge select P2IES 2Ch Port P2 interrupt flag P2IFG 2Bh Port P2 direction P2DIR 2Ah Port P2 output P2OUT 29h Port P2 input P2IN 28h Port P Port P selection PSEL 26h Port P interrupt enable PIE 25h Port P interrupt-edge select PIES 24h Port P interrupt flag PIFG 23h Port P direction PDIR 22h Port P output POUT 2h Port P input PIN 2h Special Functions SFR module enable 2 ME2 5h SFR module enable ME 4h SFR interrupt flag2 IFG2 3h SFR interrupt flag IFG 2h SFR interrupt enable2 IE2 h SFR interrupt enable IE h POST OFFICE BOX DALLAS, TEXAS

24 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Voltage applied at V CC to V SS V to 4. V Voltage applied to any pin (see Note) V to V CC +.3 V Diode current at any device terminal ±2 ma Storage temperature, T stg : (unprogrammed device) C to 5 C (programmed device) C to 85 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse. recommended operating conditions Supply voltage during program execution, VCC (AVCC = DVCC = VCC) Supply voltage during flash memory programming, VCC (AVCC = DVCC = VCC) Supply voltage during program execution, SVS enabled (see Note ), VCC (AVCC = DVCC = VCC) MSP43F5x/6x/ 6x MSP43F5x/6x/ 6x MSP43F5x/6x/ 6x MIN NOM MAX UNITS V V V Supply voltage, VSS (AVSS = DVSS = VSS) V Operating free-air temperature range, TA LFXT crystal frequency, f(lfxt) (see Notes 2 and 3) XT2 crystal frequency, f(xt2) Processor frequency (signal MCLK), f(system) NOTES: MSP43F5x/6x/ 6x 4 85 C LF selected, XTS= Watch crystal khz XT selected, XTS= Ceramic resonator 45 8 khz XT selected, XTS= Crystal 8 khz Ceramic resonator 45 8 Crystal 8 VCC =.8 V DC 4.5 VCC = 3.6 V DC 8. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply voltage. POR is going inactive when the VCC is raised above the minimum supply voltage plus the hysteresis of the SVS circuitry. 2. In LF mode, the LFXT oscillator requires a watch crystal. A 5.MΩ resistor from XOUT to VSS is recommended when VCC < 2.5 V. In XT mode, the LFXT and XT2 oscillators accept a ceramic resonator or crystal up to 4.5MHz at VCC 2.2 V. In XT mode, the LFXT and XT2 oscillators accept a ceramic resonator or crystal up to 8MHz at VCC 2.8 V. 3. In LF mode, the LFXT oscillator requires a watch crystal. In XT mode, LFXT accepts a ceramic resonator or a crystal. khz MHz f (MHz) 8. MHz 4.5 MHz Supply voltage range, F5x/6x/6x, during program execution ÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Supply voltage range, F5x/6x/6x, during flash memory programming.8 V 2.7 V 3 V 3.6 V Supply Voltage V Figure. Frequency vs Supply Voltage, MSP43F5x/6x/6x 24 POST OFFICE BOX DALLAS, TEXAS 75265

25 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) MSP43F5x/6x supply current into AV CC + DV CC excluding external current (AV CC = DV CC = V CC ) I(AM) I(LPM) I(LPM2) I(LPM3) I(LPM4) NOTES: PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Active mode, (see Note ) f(mclk) = f(smclk) = MHz, f(aclk) = 32,768 Hz XTS=, SELM=(,) Active mode, (see Note ) f(mclk) = f(smclk) = 4,96 Hz, f(aclk) = 4,96 Hz XTS=, SELM=3 TA = 4 C to 85 C TA = 4 C to 85 C Low-power mode, (LPM) f(mclk) = MHz, f(smclk) = MHz, f(aclk) = 32,768 Hz TA = 4 C to 85 C XTS=, SELM=(,) (see Note ) Low-power mode, (LPM2), f(mclk) = f(smclk) = MHz, TA = 4 C to 85 C f(aclk) = Hz, SCG = VCC = 2.2 V 33 4 VCC = 3 V 5 6 VCC = 2.2 V VCC = 3 V 9 2 VCC = 2.2 V 5 6 VCC = 3 V 75 9 VCC = 2.2 V 4 VCC = 3 V 7 22 TA = 4 C..6 TA = 25 C..6 Low-power mode, (LPM3) VCC = 2.2 V TA = 85 C f(mclk) = f(smclk) = MHz, f(aclk) = 32,768 Hz, SCG = TA = 4 C (see Note 2) TA = 25 C VCC = 3 V TA = 85 C Low-power mode, (LPM4) TA = 4 C f(mclk) = MHz, f(smclk) = MHz, TA = 25 C f(aclk) = Hz, SCG = TA = 85 C VCC = 2.2V / 3 V µaa µaa µaa µaa µaa.2.5 µa Timer_B is clocked by f(dcoclk) = MHz. All inputs are tied to V or to VCC. Outputs do not source or sink any current. 2. WDT is clocked by f(aclk) = 32,768 Hz. All inputs are tied to V or to VCC. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured with ACLK selected. Current consumption of active mode versus system frequency, F-version I(AM) = I(AM) [ MHz] f(system) [MHz] Current consumption of active mode versus supply voltage, F-version I (AM) = I (AM) [3 V] + 2 µa/v (V CC 3 V) POST OFFICE BOX DALLAS, TEXAS

26 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) MSP43F6x supply current into AV CC + DV CC excluding external current (AV CC = DV CC = V CC ) I(AM) I(LPM) I(LPM2) I(LPM3) I(LPM4) NOTES: PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Active mode, (see Note ) f(mclk) = f(smclk) = MHz, f(aclk) = 32,768 Hz XTS=, SELM=(,) Active mode, (see Note ) f(mclk) = f(smclk) = 4,96 Hz, f(aclk) = 4,96 Hz XTS=, SELM=3 TA = 4 C to 85 C TA = 4 C to 85 C Low-power mode, (LPM) f(mclk) = MHz, f(smclk) = MHz, f(aclk) = 32,768 Hz TA = 4 C to 85 C XTS=, SELM=(,) (see Note ) Low-power mode, (LPM2), f(mclk) = f(smclk) = MHz, TA = 4 C to 85 C f(aclk) = Hz, SCG = VCC = 2.2 V 33 4 VCC = 3 V 5 6 VCC = 2.2 V VCC = 3 V 9 2 VCC = 2.2 V 5 6 VCC = 3 V VCC = 2.2 V 4 VCC = 3 V 7 22 TA = 4 C.3.6 TA = 25 C.3.6 Low-power mode, (LPM3) VCC = 2.2 V TA = 85 C f(mclk) = f(smclk) = MHz, f(aclk) = 32,768 Hz, SCG = TA = 4 C (see Note 2) TA = 25 C VCC = 3 V TA = 85 C Low-power mode, (LPM4) TA = 4 C f(mclk) = MHz, f(smclk) = MHz, TA = 25 C f(aclk) = Hz, SCG = TA = 85 C VCC = 2.2V / 3 V µaa µaa µaa µaa µaa.2.5 µa Timer_B is clocked by f(dcoclk) = MHz. All inputs are tied to V or to VCC. Outputs do not source or sink any current. 2. WDT is clocked by f(aclk) = 32,768 Hz. All inputs are tied to V or to VCC. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured with ACLK selected. Current consumption of active mode versus system frequency, F-version I(AM) = I(AM) [ MHz] f(system) [MHz] Current consumption of active mode versus supply voltage, F-version I (AM) = I (AM) [3 V] + 2 µa/v (V CC 3 V) 26 POST OFFICE BOX DALLAS, TEXAS 75265

27 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) SCHMITT-trigger inputs Ports P, P2, P3, P4, P5, P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI VIT+ VIT Vhys Positive-going input threshold voltage Negative-going input threshold voltage Input voltage hysteresis (VIT+ VIT ) inputs Px.x, TAx, TBx t(int) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC = 2.2 V..5 VCC = 3 V.5.98 VCC = 2.2 V.4.9 VCC = 3 V.9.3 VCC = 2.2 V.3. VCC = 3 V.5 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT External interrupt timing Port P, P2: P.x to P2.x, external trigger signal 2.2 V 62 for the interrupt flag, (see Note ) 3 V 5 V V V ns t(cap) Timer_A, Timer_B capture timing TA, TA, TA2 2.2 V 62 TB, TB, TB2, TB3, TB4, TB5, TB6 (see Note 2) 3 V 5 ns f(taext) f(tbext) f(taint) f(tbint) NOTES: Timer_A, Timer_B clock frequency externally applied to pin Timer_A, Timer_B clock frequency TACLK, TBCLK, INCLK: t(h) = t(l) SMCLK or ACLK signal selected 2.2 V 8 3 V 2.2 V 8 3 V. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals shorter than t(int). 2. Seven capture/compare registers in x6x/6x and three capture/compare registers in x5x. leakage current Ports P, P2, P3, P4, P5 and P6 (see Note ) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Leakage Ilkg(Px.y) current Port Px V(Px.y) (see Note 2) VCC = 2.2 V/3 V ±5 na NOTES:. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The port pin must be selected as input. MHz MHz POST OFFICE BOX DALLAS, TEXAS

28 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs Ports P, P2, P3, P4, P5, and P6 VOH VOL NOTES: PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High-level output voltage Low-level output voltage IOH(max) =.5 ma, VCC = 2.2 V, See Note VCC.25 VCC IOH(max) = 6 ma, VCC = 2.2 V, See Note 2 VCC.6 VCC IOH(max) =.5 ma, VCC = 3 V, See Note VCC.25 VCC IOH(max) = 6 ma, VCC = 3 V, See Note 2 VCC.6 VCC IOL(max) =.5 ma, VCC = 2.2 V, See Note VSS VSS+.25 IOL(max) = 6 ma, VCC = 2.2 V, See Note 2 VSS VSS+.6 IOL(max) =.5 ma, VCC = 3 V, See Note VSS VSS+.25 IOL(max) = 6 ma, VCC = 3 V, See Note 2 VSS VSS+.6. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±2 ma to satisfy the maximum specified voltage drop. 2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 ma to satisfy the maximum specified voltage drop. output frequency PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f(px.y) ( x 6, y 7) f(aclk) f(mclk) f(smclk) CL = 2 pf, IL = ±.5 ma P2./ACLK, P5.6/ACLK P5.4/MCLK, CL = 2 pf VCC = 2.2 V / 3 V P.4/SMCLK, P5.5/SMCLK VCC = 2.2 V / 3 V DC fsystem MHz fsystem P./TACLK f(aclk) = f(lfxt) = f(xt) 4% 6% CL = 2 pf f(aclk) = f(lfxt) = f(lf) 3% 7% VCC = 2.2 V / 3 V f(aclk) = f(lfxt) 5% V V MHz t(xdc) Duty cycle of output frequency P./TA/MCLK, f(mclk) = f(xt) 4% 6% CL = 2 pf, 5% 5%+ VCC = 2.2 V / 3 V f(mclk) = f(dcoclk) 5% 5 ns 5 ns P.4/TBCLK/SMCLK, f(smclk) = f(xt2) 4% 6% CL = 2 pf, VCC = 2.2 V / 3 V f(smclk) = f(dcoclk) 5% 5 ns 5% 5%+ 5 ns 28 POST OFFICE BOX DALLAS, TEXAS 75265

29 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) outputs Ports P, P2, P3, P4, P5, and P6 (continued) I OL Low-Level Output Current ma TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE VCC = 2.2 V P3.5 TA = 25 C TA = 85 C I OL Low-Level Output Current ma TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE VCC = 3 V P3.5 TA = 25 C TA = 85 C VOL Low-Level Output Voltage V VOL Low-Level Output Voltage V Figure 2 Figure 3 I OH High-Level Output Current ma TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE VCC = 2.2 V P3.5 TA = 85 C I OH High-Level Output Current ma TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE VCC = 3 V P3.5 TA = 85 C TA = 25 C VOH High-Level Output Voltage V Figure 4 TA = 25 C VOH High-Level Output Voltage V Figure 5 POST OFFICE BOX DALLAS, TEXAS

30 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) wake-up LPM3 t(lpm3) Delay time PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC = 2.2 V/3 V, fdco fdco43 6 µs RAM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRAMh CPU HALTED (see Note ).6 V NOTE : This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution should take place during this supply voltage condition. Comparator_A (see Note ) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(DD) CAON=, CARSEL=, CAREF= VCC = 2.2 V 25 4 VCC = 3 V 45 6 µa I(Refladder/Refdiode) V(IC) V(Ref25) V(Ref5) Common-mode input voltage V node CC V CC node CC V CC CAON=, CARSEL=, VCC = 2.2 V 3 5 CAREF=/2/3, no load at P2.3/CA/TA and P2.4/CA/TA2 VCC = 3 V 45 7 CAON = VCC = 2.2 V/3 V VCC V PCA=, CARSEL=, CAREF=, no load at P2.3/CA/TA and P2.4/CA/TA2 PCA=, CARSEL=, CAREF=2, no load at P2.3/CA/TA and P2.4/CA/TA2 VCC = 2.2 V/3 V VCC = 2.2 V/3 V PCA=, CARSEL=, CAREF=3, VCC = 2.2 V V(RefVT) (see Figure 6 and Figure 7) no load at P2.3/CA/TA and P2.4/CA/TA2 TA = 85 C VCC = 3 V V(offset) Offset voltage See Note 2 VCC = 2.2 V/3 V 3 3 mv Vhys Input hysteresis CAON= VCC = 2.2 V/3 V.7.4 mv t(response LH) t(response HL) NOTES: TA = 25 C, Overdrive mv, VCC = 2.2 V Without filter: CAF= VCC = 3 V TA = 25 C, Overdrive mv, VCC = 2.2 V With filter: CAF= VCC = 3 V TA = 25 C, Overdrive mv, VCC = 2.2 V Without filter: CAF= VCC = 3 V TA = 25 C, Overdrive mv, VCC = 2.2 V With filter: CAF= VCC = 3 V The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. µa mv ns µs ns µs 3 POST OFFICE BOX DALLAS, TEXAS 75265