description F435, F436, and F437 devices F447, F448, and F449 devices

Transcription

1 Low Supply-Voltage Range,.8 V to 3.6 V Ultralow-Power Consumption: Active Mode: 28 µa at MHz, 2.2 V Standby Mode:. µa Off Mode (RAM Retention):. µa Five Power Saving Modes Wake-Up From Standby Mode in 6 µs 6-Bit RISC Architecture, 25-ns Instruction Cycle Time 2-Bit A/D Converter With Internal Reference, Sample-and-Hold and Autoscan Feature 6-Bit Timer_B With Three or Seven Capture/Compare-With-Shadow Registers 6-Bit Timer_A With Three Capture/Compare Registers On-Chip Comparator Serial Communication Interface (USART), Select Asynchronous UART or Synchronous SPI by Software: Two USARTs (USART, USART) MSP43x44x Devices One USART (USART) MSP43x43x Devices Brownout Detector Supply Voltage Supervisor/Monitor With Programmable Level Detection description SLAS344C JANUARY 22 REVISED MARCH23 Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse Integrated LCD Driver for Up to 6 Segments Family Members Include: MSP43F435: 6KB+256B Flash Memory, 52B RAM MSP43F436: 24KB+256B Flash Memory, KB RAM MSP43F437: 32KB+256B Flash Memory, KB RAM MSP43F447: 32KB+256B Flash Memory, KB RAM MSP43F448: 48KB+256B Flash Memory, 2KB RAM MSP43F449: 6KB+256B Flash Memory, 2KB RAM For Complete Module Descriptions, See The MSP43x4xx Family User s Guide, Literature Number SLAU56 F435, F436, and F437 devices F447, F448, and F449 devices The Texas Instruments MSP43 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 6-bit RISC CPU, 6-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs. The MSP43x43x and the MSP43x44x series are microcontroller configurations with two built-in 6-bit timers, a fast 2-bit A/D converter, one or two universal serial synchronous/asynchronous communication interfaces (USART), 48 I/O pins, and a liquid crystal driver (LCD) with up to 6 segments. Typical applications include sensor systems that capture analog signals, convert them to digital values, and process and transmit the data to a host system, or process this data and displays it on a LCD panel. The timers make the configurations ideal for industrial control applications such as ripple counters, digital motor control, EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code and hardware-compatible family solution. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 22 23, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS 75265

2 SLAS344C JANUARY 22 REVISED MARCH23 TA 4 C to 85 C AVAILABLE OPTIONS PLASTIC 8-PIN QFP (PN) MSP43F435IPN MSP43F436IPN MSP43F437IPN PACKAGED DEVICES PLASTIC -PIN QFP (PZ) MSP43F435IPZ MSP43F436IPZ MSP43F437IPZ MSP43F447IPZ MSP43F448IPZ MSP43F449IPZ pin designation, MSP43x435IPN, MSP43x436IPN, MSP43x437IPN P6./A P6./A RST/NMI TCK PN PACKAGE (TOP VIEW) TMS TDI TDO/TDI XT2IN XT2OUT DV CC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7/SVSin VREF+ XIN XOUT/TCLK VeREF+ VREF /VeREF P5./S P5./S P4.7/S2 P4.6/S3 P4.5/S4 P4.4/S5 P4.3/S6 P4.2/S7 P4./S MSP43F435IPN 52 MSP43F436IPN 5 MSP43F437IPN P.7CA P2./TA2 P2./TB P2.2/TB P2.3/TB2 P2.4/UTXD P2.5/URXD DV SS2 DV CC2 P5.7/R33 P5.6/R23 P5.5/R3 R3 P5.4/COM3 P5.3/COM2 P5.2/COM COM P3./STE/S3 P3./SIMO/S3 P3.2/SOMI/S29 P4./S9 S S5 S6 S7 P2.7/ADC2CLK/S8 P2.6/CAOUT/S9 S2 S2 S22 S23 P3.7/S24 P3.6/S25 AV CC DVSS AVSS P6.2/A2 P./TA P./TA/MCLK P.2/TA P.3/TBOUTH/SVSOUT P3.5/S26 P3.4/S27 P.4/TBCLK/SMCLK P.5/TACLK/ACLK P.6/CA S S2 S3 S4 P3.3/UCLK/S28 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 pin designation, MSP43x435IPZ, MSP43x436IPZ, MSP43x437IPZ SLAS344C JANUARY 22 REVISED MARCH23 PZ PACKAGE (TOP VIEW) AV CC DV SS AV SS P6.2/A2 P6./A P6./A RST/NMI TCK TMS TDI TDO/TDI XT2IN XT2OUT P./TA P./TA/MCLK P.2/TA P.3/TBOUTH/SVSOUT P.4/TBCLK/SMCLK P.5/TACLK/ACLK P.6/CA P.7/CA P2./TA2 P2./TB P2.2/TB P2.3/TB2 DV CC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7/SVSin VREF+ XIN XOUT/TCLK VeREF+ VREF /VeREF P5./S P5./S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S MSP43F435IPZ MSP43F436IPZ MSP43F437IPZ P2.4/UTXD P2.5/URXD P2.6/CAOUT P2.7/ADC2CLK P3./STE P3./SIMO P3.2/SOMI P3.3/UCLK P3.4 P3.5 P3.6 P3.7 P4. P4. DV SS2 DV CC2 P5.7/R33 P5.6/R23 P5.5/R3 R3 P5.4/COM3 P5.3/COM2 P5.2/COM COM P4.2/S39 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 P4.7/S34 P4.6/S35 P4.5/S36 P4.4/S37 P4.3/S38 POST OFFICE BOX DALLAS, TEXAS

4 SLAS344C JANUARY 22 REVISED MARCH23 pin designation, MSP43x447IPZ, MSP43x448IPZ, MSP43x449IPZ PZ PACKAGE (TOP VIEW) AV CC DV SS AV SS P6.2/A2 P6./A P6./A RST/NMI TCK TMS TDI TDO/TDI XT2IN XT2OUT P./TA P./TA/MCLK P.2/TA P.3/TBOUTH/SVSOUT P.4/TBCLK/SMCLK P.5/TACLK/ACLK P.6/CA P.7/CA P2./TA2 P2./TB P2.2/TB P2.3/TB DV CC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7/SVSin VREF+ XIN XOUT/TCLK VeREF+ VREF /VeREF P5./S P5./S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 MSP43F447IPZ MSP43F448IPZ MSP43F449IPZ P2.4/UTXD P2.5/URXD P2.6/CAOUT P2.7/ADC2CLK P3./STE P3./SIMO P3.2/SOMI P3.3/UCLK P3.4/TB3 P3.5/TB4 P3.6/TB5 P3.7/TB6 P4./UTXD P4./URXD DV SS2 DV CC2 P5.7/R33 P5.6/R23 P5.5/R3 R3 P5.4/COM3 P5.3/COM2 P5.2/COM COM P4.2/STE/S39 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 P4.7/S34 P4.6/S35 P4.5/UCLK/S36 P4.4/SOMI/S37 4.3/SIMO/S38 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 SLAS344C JANUARY 22 REVISED MARCH23 MSP43x43x functional block diagrams XIN XOUT/TCLK DVCC DVSS AVCC AVSS RST/NMI P5 P6 P3 P4 P P2 XT2IN XT2OUT Oscillator FLL+ ACLK SMCLK 6 kb Flash 24 kb Flash 32 kb Flash 52 B RAM 2 Bit ADC I/O Port 5/6 I/O Port 3/4 kb RAM 8 Channels 6 I/Os kb RAM < µs Conv. I/O Port /2 6 I/Os, With Interrupt Capability USART UART or SPI Function MCLK CPU Incl. 6 Reg. Test JTAG Emulation Module MAB, 6 Bit MDB, 6 Bit MCB Bus Conv MAB, 4 Bit MDB, 8 Bit 4 TMS TCK TDI TDO/TDI Watchdog Timer 5 / 6 Bit Timer_B3 3 CC Reg Shadow Reg. Timer_A3 3 CC-Reg. POR SVS Brownout Comparator A Basic Timer Interrupt Vector flcd LCD 6 Segments,2,3,4 MUX MSP43x44x functional block diagrams XIN XOUT/TCLK DVCC DVSS AVCC AVSS RST/NMI P5 P6 P3 P4 P P2 XT2IN XT2OUT Oscillator FLL+ ACLK SMCLK 32 kb Flash 48 kb Flash 6 kb Flash kb RAM 2 kb RAM 2 kb RAM 2 Bit ADC 8 Channels < µs Conv. I/O Port 5/6 I/O Port 3/4 6 I/Os I/O Port /2 6 I/Os, With Interrupt Capability USART USART UART or SPI Function MCLK CPU Incl. 6 Reg. Test JTAG Emulation Module MAB, 6 Bit MDB, 6 Bit MCB Bus Conv MAB, 4 Bit MDB, 8 Bit 4 TMS TCK TDI TDO/TDI Multiply MPY, MPYS MAC,MACS 8 8 Bit 8 6 Bit 6 8 Bit 6 6 Bit Watchdog Timer 5 / 6 Bit Timer_B7 7 CC-Reg. Shadow Reg. Timer_A3 3 CC-Reg. POR SVS Brownout Comparator A Basic Timer Interrupt Vector flcd LCD 6 Segments,2,3,4 MUX POST OFFICE BOX DALLAS, TEXAS

6 SLAS344C JANUARY 22 REVISED MARCH23 NAME PN NO. TERMINAL I/O NAME MSP43x43x Terminal Functions PZ NO. I/O DESCRIPTION DVCC DVCC Digital supply voltage, positive terminal. Supplies all digital parts P6.3/A3 2 I/O P6.3/A3 2 I/O General-purpose digital I/O, analog input a3 2-bit ADC P6.4/A4 3 I/O P6.4/A4 3 I/O General-purpose digital I/O, analog input a4 2-bit ADC P6.5/A5 4 I/O P6.5/A5 4 I/O General-purpose digital I/O, analog input a5 2-bit ADC P6.6/A6 5 I/O P6.6/A6 5 I/O General-purpose digital I/O, analog input a6 2-bit ADC P6.7/A7/SVSin 6 I/O P6.7/A7/SVSin 6 I/O General-purpose digital I/O, analog input a7 2-bit ADC, analog input to brownout, supply voltage supervisor VREF+ 7 O VREF+ 7 O Output of positive terminal of the reference voltage in the ADC XIN 8 I XIN 8 I Input port for crystal oscillator XT. Standard or watch crystals can be connected. XOUT/TCLK 9 I/O XOUT/TCLK 9 I/O Output terminal of crystal oscillator XT or test clock input VeREF+ I VeREF+ I Input for an external reference voltage to the ADC VREF /VeREF I VREF /VeREF I Negative terminal for the ADC s reference voltage for both sources, the internal reference voltage, or an external applied reference voltage. P5./S 2 I/O P5./S 2 I/O General-purpose I/O / LCD segment output P5./S 3 I/O P5./S 3 I/O General-purpose I/O / LCD segment output P4.7/S2 4 I/O S2 4 O General-purpose I/O / LCD segment output 2 P4.6/S3 5 I/O S3 5 O General-purpose I/O / LCD segment output 3 P4.5/S4 6 I/O S4 6 O General-purpose I/O / LCD segment output 4 P4.4/S5 7 I/O S5 7 O General-purpose I/O / LCD segment output 5 P4.3/S6 8 I/O S6 8 O General-purpose I/O / LCD segment output 6 P4.2/S7 9 I/O S7 9 O General-purpose I/O / LCD segment output 7 P4./S8 2 I/O S8 2 O General-purpose I/O / LCD segment output 8 P4./S9 2 I/O S9 2 O General-purpose I/O / LCD segment output 9 S 22 O S 22 O LCD segment output S 23 O S 23 O LCD segment output S2 24 O S2 24 O LCD segment output 2 S3 25 O S3 25 O LCD segment output 3 S4 26 O S4 26 O LCD segment output 4 S5 27 O S5 27 O LCD segment output 5 S6 28 O S6 28 O LCD segment output 6 S7 29 O S7 29 O LCD segment output 7 P2.7/ADC2CLK/ S8 3 I/O S8 3 O General-purpose digital I/O / conversion clock 2-bit ADC LCD segment output 8 General-purpose digital I/O / Comparator_A output / LCD segment output 9 P2.6/CAOUT/S9 3 I/O S9 3 O S2 32 O S2 32 O LCD segment output 2 S2 33 O S2 33 O LCD segment output 2 S22 34 O S22 34 O LCD segment output 22 S23 35 O S23 35 O LCD segment output 23 P3.7/S24 36 I/O S24 36 O General-purpose digital I/O / LCD segment output 24 P3.6/S25 37 I/O S25 37 O General-purpose digital I/O / LCD segment output 25 P3.5/S26 38 I/O S26 38 O General-purpose digital I/O / LCD segment output 26 P3.4/S27 39 I/O S27 39 O General-purpose digital I/O / LCD segment output 27 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 NAME PN NO. TERMINAL I/O MSP43x43x Terminal Functions (Continued) NAME PZ NO. P3.3/UCLK/S28 4 I/O S28 4 O I/O SLAS344C JANUARY 22 REVISED MARCH23 DESCRIPTION General-purpose digital I/O / ext. clock i/p USART/UART or SPI mode, clock o/p USART/SPI mode / LCD segment output 28 P3.2/SOMI/S29 4 I/O S29 4 O General-purpose digital I/O / slave out/master in of USART/SPI mode / LCD segment output 29 P3./SIMO/S3 42 I/O S3 42 O General-purpose digital I/O / slave out/master out of USART/SPI mode / LCD segment output 3 P3./STE/S3 43 I/O S3 43 O General-purpose digital I/O / slave transmit enable-usart/spi mode / LCD segment output 3 S32 44 O LCD segment output 32 S33 45 O LCD segment output 33 P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34 P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35 P4.5/S36 48 I/O General-purpose digital I/O / LCD segment output 36 P4.4/S37 49 I/O General-purpose digital I/O / LCD segment output 37 P4.3/S38 5 I/O General-purpose digital I/O / LCD segment output 38 P4.2/S39 5 I/O General-purpose digital I/O / LCD segment output 39 COM 44 O COM 52 O COM 3 are used for LCD backplanes. P5.2/COM 45 I/O P5.2/COM 53 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. P5.3/COM2 46 I/O P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. P5.4/COM3 47 I/O P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. R3 48 I R3 56 I Input port of fourth positive (lowest) analog LCD level (V5) P5.5/R3 49 I/O P5.5/R3 57 I/O General-purpose digital I/O / input port of third most positive analog LCD level (V4 or V3) P5.6/R23 5 I/O P5.6/R23 58 I/O General-purpose digital I/O / input port of second most positive analog LCD level (V2) P5.7/R33 5 I/O P5.7/R33 59 I/O General-purpose digital I/O / output port of most positive analog LCD level (V) DVCC2 52 DVCC2 6 DVSS2 53 DVSS2 6 P4. 62 I/O General-purpose digital I/O P4. 63 I/O General-purpose digital I/O P I/O General-purpose digital I/O P I/O General-purpose digital I/O P I/O General-purpose digital I/O P I/O General-purpose digital I/O P3.3/UCLK 68 I/O General-purpose digital I/O / external clock input USART/UART or SPI mode, clock output USART/SPI mode P3.2/SOMI 69 I/O General-purpose digital I/O / slave out/master in of USART/SPI mode P3./SIMO 7 I/O General-purpose digital I/O / slave in/master out of USART/SPI mode P3./STE 7 I/O General-purpose digital I/O / slave transmit enable USART/SPI mode P2.7/ADC2CLK 72 I/O General-purpose digital I/O / conversion clock 2-bit ADC P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output P2.5/URXD 54 I/O P2.5/URXD 74 I/O General-purpose digital I/O / receive data in USART/UART mode POST OFFICE BOX DALLAS, TEXAS

8 SLAS344C JANUARY 22 REVISED MARCH23 NAME PN NO. TERMINAL I/O MSP43x43x Terminal Functions (Continued) NAME PZ NO. I/O DESCRIPTION P2.4/UTXD 55 I/O P2.4/UTXD 75 I/O General-purpose digital I/O / transmit data out USART/UART mode P2.3/TB2 56 I/O P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B3 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output P2.2/TB 57 I/O P2.2/TB 77 I/O General-purpose digital I/O / Timer_B3 CCR. Capture: CCIA/CCIB input, compare: Out output P2./TB 58 I/O P2./TB 78 I/O General-purpose digital I/O / Timer_B3 CCR. Capture: CCIA/CCIB input, compare: Out output P2./TA2 59 I/O P2./TA2 79 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output P.7/CA 6 I/O P.7/CA 8 I/O General-purpose digital I/O / Comparator_A input P.6/CA 6 I/O P.6/CA 8 I/O General-purpose digital I/O / Comparator_A input P.5/TACLK/ ACLK P.4/TBCLK/ SMCLK P.3/TBOUTH/ SVSOUT 62 I/O P.5/TACLK/ ACLK 63 I/O P.4/TBCLK/ SMCLK 64 I/O P.3/TBOUTH/ SVSOUT 82 I/O 83 I/O 84 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by, 2, 4, or 8) General-purpose digital I/O / input clock TBCLK Timer_B3 / submain system clock SMCLK output General-purpose digital I/O / switch all PWM digital output ports to high impedance Timer_B3 TB to TB2 / SVS: output of SVS comparator P.2/TA 65 I/O P.2/TA 85 I/O General-purpose digital I/O / Timer_A, Capture: CCIA, compare: Out output P./TA/MCLK 66 I/O P./TA/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCIB / MCLK output. Note: TA is only an input on this pin. P./TA 67 I/O P./TA 87 I/O General-purpose digital I/O / Timer_A. Capture: CCIA input, compare: Out output XT2OUT 68 O XT2OUT 88 O Output terminal of crystal oscillator XT2 XT2IN 69 I XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be connected. TDO/TDI 7 I/O TDO/TDI 9 I/O Test data output port. TDO/TDI data output or programming data input terminal TDI 7 I TDI 9 I Test data input. TDI is used as a data input port. The device protection fuse is connected to TDI. TMS 72 I TMS 92 I Test mode select. TMS is used as an input port for device programming and test. TCK 73 I TCK 93 I Test clock. TCK is the clock input port for device programming and test. RST/NMI 74 I RST/NMI 94 I General-purpose digital I/O / reset input or nonmaskable interrupt input port P6./A 75 I/O P6./A 95 I/O General-purpose digital I/O / analog input a 2-bit ADC P6./A 76 I/O P6./A 96 I/O General-purpose digital I/O / analog input a 2-bit ADC P6.2/A2 77 I/O P6.2/A2 97 I/O General-purpose digital I/O / analog input a2 2-bit ADC AVSS 78 AVSS 98 DVSS 79 DVSS 99 AVCC 8 AVCC Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_a, port, and LCD resistive divider circuitry. Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via AVCC/AVSS. Positive terminal that supplies SVS, brownout, oscillator, FLL+, comparator_a, port, and LCD resistive divider circuitry; must not power up prior to DVCC/DVCC2. 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 TERMINAL NAME MSP43x44x Terminal Functions PN I/O DESCRIPTION NO. DVCC Digital supply voltage, positive terminal. Supplies all digital parts P6.3/A3 2 I/O General-purpose digital I/O, analog input a3 2-bit ADC P6.4/A4 3 I/O General-purpose digital I/O, analog input a4 2-bit ADC P6.5/A5 4 I/O General-purpose digital I/O, analog input a5 2-bit ADC P6.6/A6 5 I/O General-purpose digital I/O, analog input a6 2-bit ADC SLAS344C JANUARY 22 REVISED MARCH23 P6.7/A7/SVSin 6 I/O General-purpose digital I/O, analog input a7 2-bit ADC, analog input to brownout, supply voltage supervisor VREF+ 7 O Output of positive terminal of the reference voltage in the ADC XIN 8 I Input port for crystal oscillator XT. Standard or watch crystals can be connected. XOUT/TCLK 9 I/O Output terminal of crystal oscillator XT or test clock input VeREF+ I Input for an external reference voltage to the ADC VREF /VeREF I Negative terminal for the ADC s reference voltage for both sources, the internal reference voltage, or an external applied reference voltage P5./S 2 O General-purpose digital I/O, LCD segment output P5./S 3 O General-purpose digital I/O, LCD segment output S2 4 O LCD segment output 2 S3 5 O LCD segment output 3 S4 6 O LCD segment output 4 S5 7 O LCD segment output 5 S6 8 O LCD segment output 6 S7 9 O LCD segment output 7 S8 2 O LCD segment output 8 S9 2 O LCD segment output 9 S 22 O LCD segment output S 23 O LCD segment output S2 24 O LCD segment output 2 S3 25 O LCD segment output 3 S4 26 O LCD segment output 4 S5 27 O LCD segment output 5 S6 28 O LCD segment output 6 S7 29 O LCD segment output 7 S8 3 O LCD segment output 8 S9 3 O LCD segment output 9 S2 32 O LCD segment output 2 S2 33 O LCD segment output 2 S22 34 O LCD segment output 22 S23 35 O LCD segment output 23 S24 36 O LCD segment output 24 S25 37 O LCD segment output 25 S26 38 O LCD segment output 26 S27 39 O LCD segment output 27 S28 4 O LCD segment output 28 POST OFFICE BOX DALLAS, TEXAS

10 SLAS344C JANUARY 22 REVISED MARCH23 TERMINAL NAME MSP43x44x Terminal Functions (Continued) PN I/O DESCRIPTION NO. S29 4 O LCD segment output 29 S3 42 O LCD segment output 3 S3 43 O LCD segment output 3 S32 44 O LCD segment output 32 S33 45 O LCD segment output 33 P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34 P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35 P4.5/UCLK/S36 48 I/O General-purpose digital I/O / external clock input USART/UART or SPI mode, clock output USART/SPI MODE / LCD segment output 36 P4.4/SOMI/S37 49 I/O General-purpose digital I/O / slave out/master in of USART/SPI mode / LCD segment output 37 P4.3/SIMO/S38 5 I/O General-purpose digital I/O / slave in/master out of USART/SPI mode / LCD segment output 38 P4.2/STE/S39 5 I/O General-purpose digital I/O / slave transmit enable USART/SPI mode / LCD segment output 39 COM 52 O COM 3 are used for LCD backplanes. P5.2/COM 53 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. R3 56 I Input port of fourth positive (lowest) analog LCD level (V5) P5.5/R3 57 I/O General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3) P5.6/R23 58 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2) P5.7/R33 59 I/O General-purpose digital I/O / Output port of most positive analog LCD level (V) DVCC2 6 DVSS2 6 P4./URXD 62 I/O General-purpose digital I/O / receive data in USART/UART mode P4./UTXD 63 I/O General-purpose digital I/O / transmit data out USART/UART mode P3.7/TB6 64 I/O General-purpose digital I/O / Timer_B7 CCR6 / Capture: CCI6A/CCI6B input, compare: Out6 output P3.6/TB5 65 I/O General-purpose digital I/O / Timer_B7 CCR5 / Capture: CCI5A/CCI5B input, compare: Out5 output P3.5/TB4 66 I/O General-purpose digital I/O / Timer_B7 CCR4 / Capture: CCI4A/CCI4B input, compare: Out4 output P3.4/TB3 67 I/O General-purpose digital I/O / Timer_B7 CCR3 / Capture: CCI3A/CCI3B input, compare: Out3 output P3.3/UCLK 68 I/O General-purpose digital I/O / external clock input USART/UART or SPI mode, clock output USART/SPI mode P3.2/SOMI 69 I/O General-purpose digital I/O / slave out/master in of USART/SPI mode P3./SIMO 7 I/O General-purpose digital I/O / slave in/master out of USART/SPI mode P3./STE 7 I/O General-purpose digital I/O / slave transmit enable USART/SPI mode P2.7/ADC2CLK 72 I/O General-purpose digital I/O / conversion clock 2-bit ADC P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output P2.5/URXD 74 I/O General-purpose digital I/O / receive data in USART/UART mode P2.4/UTXD 75 I/O General-purpose digital I/O / transmit data out USART/UART mode P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output P2.2/TB 77 I/O General-purpose digital I/O / Timer_B7 CCR. Capture: CCIA/CCIB input, compare: Out output P2./TB 78 I/O General-purpose digital I/O / Timer_B7 CCR. Capture: CCIA/CCIB input, compare: Out output P2./TA2 79 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output P.7/CA 8 I/O General-purpose digital I/O / Comparator_A input POST OFFICE BOX DALLAS, TEXAS 75265

11 TERMINAL NAME MSP43x44x Terminal Functions (Continued) PN I/O DESCRIPTION NO. P.6/CA 8 I/O General-purpose digital I/O / Comparator_A input P.5/TACLK/ ACLK P.4/TBCLK/ SMCLK P.3/TBOutH/ SVSOut SLAS344C JANUARY 22 REVISED MARCH23 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by, 2, 4, or 8) 83 I/O General-purpose digital I/O / input clock TBCLK Timer_B7 / submain system clock SMCLK output 84 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance Timer_B7 TB to TB6 / SVS: output of SVS comparator P.2/TA 85 I/O General-purpose digital I/O / Timer_A, Capture: CCIA, compare: Out output P./TA/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCIB / MCLK output. Note: TA is only an input on this pin. P./TA 87 I/O General-purpose digital I/O / Timer_A. Capture: CCIA input, compare: Out output XT2OUT 88 O Output terminal of crystal oscillator XT2 XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be connected. TDO/TDI 9 I/O Test data output port. TDO/TDI data output or programming data input terminal TDI 9 I Test data input. TDI is used as a data input port. The device protection fuse is connected to TDI. TMS 92 I Test mode select. TMS is used as an input port for device programming and test. TCK 93 I Test clock. TCK is the clock input port for device programming and test. RST/NMI 94 I Reset input or nonmaskable interrupt input port P6./A 95 I/O General-purpose digital I/O, analog input a 2-bit ADC P6./A 96 I/O General-purpose digital I/O, analog input a 2-bit ADC P6.2/A2 97 I/O General-purpose digital I/O, analog input a2 2-bit ADC AVSS 98 DVSS 99 AVCC Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_a, port, and LCD resistive divider circuitry. Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via AVCC/AVSS. Positive terminal that supplies SVS, brownout, oscillator, FLL+, comparator_a, port, and LCD resistive divider circuitry; must not power up prior to DVCC/DVCC2. POST OFFICE BOX DALLAS, TEXAS 75265

12 SLAS344C JANUARY 22 REVISED MARCH23 short-form description CPU The MSP43 CPU has a 6-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 6 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 5 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table shows examples of the three types of instruction formats; the address modes are listed in Table 2. Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R SP/R SR/CG/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R R R2 R3 R4 R5 Table. Instruction Word Formats Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 > R5 Single operands, destination only e.g. CALL R8 PC >(TOS), R8 > PC Relative jump, un/conditional e.g. JNE Jump-on-equal bit = Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX EXAMPLE OPERATION Register MOV Rs,Rd MOV R,R R > R Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) > M(6+R6) Symbolic (PC relative) MOV EDE,TONI M(EDE) > M(TONI) Absolute MOV and MEM,and TCDAT M(MEM) > M(TCDAT) Indirect M(R) > M(Tab+R6) Indirect autoincrement M(R) > R R + 2 > R Immediate MOV #X,TONI MOV #45,TONI #45 > M(TONI) NOTE: S = source D = destination 2 POST OFFICE BOX DALLAS, TEXAS 75265

13 SLAS344C JANUARY 22 REVISED MARCH23 operating modes The MSP43 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: Active mode AM; All clocks are active Low-power mode (LPM); CPU is disabled ACLK and SMCLK remain active. MCLK is disabled FLL+ Loop control remains active Low-power mode (LPM); CPU is disabled FLL+ Loop control is disabled ACLK and SMCLK remain active. MCLK is disabled Low-power mode 2 (LPM2); CPU is disabled MCLK and FLL+ loop control and DCOCLK are disabled DCO s dc-generator remains enabled ACLK remains active Low-power mode 3 (LPM3); CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO s dc-generator is disabled ACLK remains active Low-power mode 4 (LPM4); CPU is disabled ACLK is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO s dc-generator is disabled Crystal oscillator is stopped POST OFFICE BOX DALLAS, TEXAS

14 SLAS344C JANUARY 22 REVISED MARCH23 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range FFFFh FFEh. The vector contains the 6-bit address of the appropriate interrupt-handler instruction sequence. Table 3. Interrupt Sources, Flags, and Vectors of 4xx Configurations INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT Power-Up External Reset Watchdog Flash Memory NMI Oscillator Fault Flash Memory Access Violation WDTIFG KEYV (see Note ) NMIIFG (see Notes and 3) OFIFG (see Notes and 3) ACCVIFG (see Notes and 3) WORD ADDRESS PRIORITY Reset FFFEh 5, highest (Non)maskable (Non)maskable (Non)maskable FFFCh 4 Timer_B7 TBCCR CCIFG (see Note 2) Maskable FFFAh 3 TBCCR to TBCCR6 CCIFGs Timer_B7 TBIFG (see Notes and 2) Maskable FFF8h 2 Comparator_A CAIFG Maskable FFF6h Watchdog Timer WDTIFG Maskable FFF4h USART Receive URXIFG Maskable FFF2h 9 USART Transmit UTXIFG Maskable FFFh 8 ADC2 ADC2IFG (see Notes and 2) Maskable FFEEh 7 Timer_A3 TACCR CCIFG (see Note 2) Maskable FFECh 6 Timer_A3 TACCR and TACCR2 CCIFGs, TAIFG (see Notes and 2) Maskable FFEAh 5 I/O Port P (Eight Flags) PIFG. (see Notes and 2) To Maskable FFE8h 4 PIFG.7 (see Notes and 2) USART Receive URXIFG Maskable FFE6h 3 USART Transmit UTXIFG Maskable FFE4h 2 I/O Port P2 (Eight Flags) P2IFG. (see Notes and 2) To Maskable FFE2h P2IFG.7 (see Notes and 2) Basic Timer BTIFG Maskable FFEh, lowest 43x uses Timer_B3 with TBCCR, and 2 CCIFG flags, and TBIFG. 44x uses Timer_B7 with TBCCR CCIFG, TBCCR to TBCCR6 CCIFGs, and TBIFG USART is implemented in 44x only. NOTES:. Multiple source flags 2. Interrupt flags are located in the module. 3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable it. 4 POST OFFICE BOX DALLAS, TEXAS 75265

15 SLAS344C JANUARY 22 REVISED MARCH23 special function registers Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access. interrupt enable and 2 Address h UTXIE URXIE ACCVIE NMIIE OFIE WDTIE rw rw rw rw rw rw WDTIE: OFIE: NMIIE: ACCVIE: URXIE: UTXIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. Oscillator-fault-interrupt enable Nonmaskable-interrupt enable Flash access violation interrupt enable USART, UART, and SPI receive-interrupt enable USART, UART, and SPI transmit-interrupt enable Address h BTIE UTXIE URXIE rw URXIE: UTXIE: BTIE: rw rw USART, UART, and SPI receive-interrupt enable (MSP43F44x devices only) USART, UART, and SPI transmit-interrupt enable (MSP43F44x devices only) Basic timer interrupt enable interrupt flag register and 2 Address h UTXIFG URXIFG NMIIFG OFIFG WDTIFG rw rw rw rw rw WDTIFG: OFIFG: NMIIFG: URXIFG: UTXIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on V CC power up or a reset condition at the RST/NMI pin in reset mode. Flag set on oscillator fault Set via RST/NMI pin USART, UART, and SPI receive flag USART, UART, and SPI transmit flag Address 3h BTIFG UTXIFG URXIFG rw URXIFG: UTXIFG: BTIFG: rw rw USART, UART, and SPI receive flag (MSP43F44x devices only) USART, UART, and SPI transmit flag (MSP43F44x devices only) Basic timer flag POST OFFICE BOX DALLAS, TEXAS

16 SLAS344C JANUARY 22 REVISED MARCH23 module enable registers and 2 Address 4h UTXE URXE USPIE rw rw URXE: UTXE: USPIE: Address 5h URXE: UTXE: USPIE: Legend: rw: rw : USART, UART mode receive enable USART, UART mode transmit enable USART, SPI mode transmit and receive enable UTXE URXE USPIE rw rw USART, UART mode receive enable (MSP43F44x devices only) USART, UART mode transmit enable (MSP43F44x devices only) USART, SPI mode transmit and receive enable (MSP43F44x devices only) Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset by PUC. SFR Bit Not Present in Device memory organization MSP43F435 MSP43F436 MSP43F437 MSP43F447 MSP43F448 MSP43F449 Memory Main: interrupt vector Main: code memory Size Flash Flash 6KB FFFFh FFEh FFFFh Ch 24KB FFFFh FFEh FFFFh Ah 32KB FFFFh FFEh FFFFh 8h 48KB FFFFh FFEh FFFFh 4h 6KB FFFFh FFEh FFFFh h Information memory Size Flash 256 Byte FFh h 256 Byte FFh h 256 Byte FFh h 256 Byte FFh h 256 Byte FFh h Boot memory Size ROM KB FFFh Ch KB FFFh Ch KB FFFh Ch KB FFFh Ch KB FFFh Ch RAM Size 52 Byte 3FFh 2h KB 5FFh 2h KB 5FFh 2h 2KB 9FFh 2h 2KB 9FFh 2h Peripherals 6-bit 8-bit 8-bit SFR FFh h FFh h Fh h FFh h FFh h Fh h FFh h FFh h Fh h FFh h FFh h Fh h FFh h FFh h Fh h bootstrap loader (BSL) The MSP43 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP43 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP43 Bootstrap Loader, Literature Number SLAA89. 6 POST OFFICE BOX DALLAS, TEXAS 75265

17 SLAS344C JANUARY 22 REVISED MARCH23 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: Flash memory has n segments of main memory and two segments of information memory (A and B) of 28 bytes each. Each segment in main memory is 52 bytes in size. Segments to n may be erased in one step, or each segment may be individually erased. Segments A and B can be erased individually, or as a group with segments n. Segments A and B are also called information memory. New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. 6KB 24KB 32KB 48KB 6KB FFFFh FEh FDFFh FFFFh FEh FDFFh FFFFh FEh FDFFh FFFFh FEh FDFFh FFFFh FEh FDFFh Segment w/ Interrupt Vectors Segment FCh FBFFh FCh FBFFh FCh FBFFh FCh FBFFh FCh FBFFh Segment 2 FAh F9FFh FAh F9FFh FAh F9FFh FAh F9FFh FAh F9FFh Main Memory C4h C3FFh C2h CFFh Ch FFh 8h 7Fh h A4h A3FFh A2h AFFh Ah FFh 8h 7Fh h 84h 83FFh 82h 8FFh 8h FFh 8h 7Fh h 44h 43FFh 42h 4FFh 4h FFh 8h 7Fh h 4h 3FFh 2h FFh h FFh 8h 7Fh h Segment n- Segment n Segment A Segment B Information Memory peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. digital I/O There are six 8-bit I/O ports implemented ports P through P6: All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of ports P and P2. Read/write access to port-control registers is supported by all instructions. POST OFFICE BOX DALLAS, TEXAS

18 SLAS344C JANUARY 22 REVISED MARCH23 oscillator and system clock The clock system in the MSP43x43x and MSP43x44x family of devices is supported by the FLL+ module that includes support for a Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The FLL+ module provides the following clock signals: Auxiliary clock (ACLK), sourced from a Hz watch crystal or a high frequency crystal. Main clock (MCLK), the system clock used by the CPU. Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8. brownout, supply voltage supervisor The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, V CC may not have ramped to V CC(min) at that time. The user must insure the default FLL+ settings are not changed until V CC reaches V CC(min). If desired, the SVS circuit can be used to determine when V CC reaches V CC(min). multiplication (MSP43x44x Only) The multiplication operation is supported by a dedicated peripheral module. The module performs 6 6, 6 8, 8 6, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required. Basic Timer The Basic Timer has two independent 8-bit timers which can be cascaded to form a 6-bit timer/counter. Both timers can be read and written by software. The Basic Timer can be used to generate periodic interrupts and clock for the LCD module. LCD drive The LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral. 8 POST OFFICE BOX DALLAS, TEXAS 75265

19 Table 4. MSP43x43xIPN Terminal Function, Selected by Bits 5/6/7 in LCD Mode Control Register LCDM TERMINAL NAME NO I/O BITS 5/6/7 IN LCD MODE CONTROL REGISTER LCDM X XXXX X XXXX X XXX X XXXX X XXXX X XXXX X XXX X XXXX P5./S 2 I/O P5. S P5./S 3 I/O P5. S P4.7/S2 4 I/O P4.7 S2 P4.6/S3 5 I/O P4.6 S3 P4.5/S4 6 I/O P4.5 S4 P4.4/S5 7 I/O P4.4 S5 P4.3/S6 8 I/O P4.3 S6 P4.2/S7 9 I/O P4.2 S7 P4./S8 2 I/O P4. S8 P4./S9 2 I/O P4. S9 POST OFFICE BOX DALLAS, TEXAS S S O S S7 P2.7/ADCCLK/S8 3 I/O P2.7/ADCCLK P2.7/ADCCLK S8 P2.6/CAOUT/S9 3 I/O P2.6/CAOUT P2.6/CAOUT S9 S2 S O S2 S23 P3.7/S24 36 I/O P3.7 P3.7 P3.7 P3.7 S24 P3.6/S25 37 I/O P3.6 P3.6 P3.6 P3.6 S25 P3.5/S26 38 I/O P3.5 P3.5 P3.5 P3.5 S26 P3.4/S27 39 I/O P3.4 P3.4 P3.4 P3.4 S27 P3.3/UCLK/S28 4 I/O P3.3/UCLK P3.3/UCLK P3.3/UCLK P3.3/UCLK P3.3/UCLK S28 P3.2/SOMI/S29 4 I/O P3.2/SOMI P3.2/SOMI P3.2/SOMI P3.2/SOMI P3.2/SOMI S29 P3./SIMO/S3 42 I/O P3./SIMO P3./SIMO P3./SIMO P3./SIMO P3./SIMO S3 P3./STE/S3 43 I/O P3./STE P3./STE P3./STE P3./STE P3./STE S3 SLAS344B JANUARY 22 REVISED OCTOBER 22

20 2 POST OFFICE BOX DALLAS, TEXAS Table 5. MSP43x43xIPZ Terminal Functions, Selected by Bits 5/6/7 in LCD Mode Control Register LCDM TERMINAL BITS 5/6/7 IN LCD MODE CONTROL REGISTER LCDM I/O NAME NO X XXXX X XXXX X XXX X XXXX X XXXX X XXXX X XXXX X XXXX P5./S 2 I/O P5. S P5./S 3 I/O P5. S S2 S O S2 S33 P4.7/S34 46 I/O P4.7 P4.7 P4.7 P4.7 P4.7 P4.7 S34 P4.6/S35 47 I/O P4.6 P4.6 P4.6 P4.6 P4.6 P4.6 S35 P4.5/S36 48 I/O P4.5 P4.5 P4.5 P4.5 P4.5 P4.5 P4.5 S36 P4.4/S36 48 I/O P4.4 P4.4 P4.4 P4.4 P4.4 P4.4 P4.4 S37 P4.3/S36 48 I/O P4.3 P4.3 P4.3 P4.3 P4.3 P4.3 P4.3 S38 P4.2/S36 48 I/O P4.2 P4.2 P4.2 P4.2 P4.2 P4.2 P4.2 S39 Table 6. MSP43x44xIPZ Terminal Functions, Selected by Bits 5/6/7 in LCD Mode Control Register LCDM TERMINAL BITS 5/6/7 IN LCD MODE CONTROL REGISTER LCDM I/O NAME NO X XXXX X XXXX X XXX X XXXX X XXXX X XXXX X XXXX X XXXX P5./S 2 I/O P5. S P5./S 3 I/O P5. S S2 S O S2 S33 P4.7/S34 46 I/O P4.7 P4.7 P4.7 P4.7 P4.7 P4.7 S34 P4.6/S35 47 I/O P4.6 P4.6 P4.6 P4.6 P4.6 P4.6 S35 P4.5/UCLK/S36 48 I/O P4.5/UCLK P4.5UCLK P4.5/UCLK P4.5/UCLK P4.5/UCLK P4.5/UCLK P4.5/UCLK S36 P4.4/SOMI/S37 49 I/O P4.4/SOMI P4.4/SOMI P4.4/SOMI P4.4/SOMI P4.4/SOMI P4.4/SOMI P4.4/SOMI S37 SLAS344B JANUARY 22 REVISED OCTOBER 22 P4.3/SIMO/S38 5 I/O P4.3/SIMO P4.3/SIMO P4.3/SIMO P4.3/SIMO P4.3/SIMO P4.3/SIMO P4.3/SIMO S38 P4.2/STE/S39 5 I/O P4.2/STE P4.2/STE P4.2/STE P4.2/STE P4.2/STE P4.2/STE P4.2/STE S39

21 SLAS344B JANUARY 22 REVISED OCTOBER 22 watchdog timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. USART The MSP43x43x and the MSP43x44x have one hardware universal synchronous/asynchronous receive transmit (USART) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. USART (MSP43x44x Only) The MSP43x44x has a second hardware universal synchronous/asynchronous receive transmit (USART) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. Operation of USART is identical to USART. timer_a3 Timer_A3 is a 6-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. timer_b7 (MSP43x44x Only) Timer_B7 is a 6-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. timer_b3 (MSP43x43x Only) Timer_B3 is a 6-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. comparator_a The primary function of the comparator_a module is to support precision slope analog to digital conversions, battery voltage supervision, and monitoring of external analog signals. ADC2 The ADC2 module supports fast, 2-bit analog-to-digital conversions. The module implements a 2-bit SAR core, sample select control, reference generator and a 6 word conversion-and-control buffer. The conversion-and-control buffer allows up to 6 independent ADC samples to be converted and stored without any CPU intervention. POST OFFICE BOX DALLAS, TEXAS

22 SLAS344B JANUARY 22 REVISED OCTOBER 22 peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog timer control WDTCTL 2h Timer_B7 Capture/compare register 6 TBCCR6 9Eh Timer_B3 Capture/compare register 5 TBCCR5 9Ch (see Note 6) Capture/compare register 4 TBCCR4 9Ah Capture/compare register 3 TBCCR3 98h Capture/compare register 2 TBCCR2 96h Capture/compare register TBCCR 94h Capture/compare register TBCCR 92h Timer_B register TBR 9h Capture/compare control 6 TBCCTL6 8Eh Capture/compare control 5 TBCCTL5 8Ch Capture/compare control 4 TBCCTL4 8Ah Capture/compare control 3 TBCCTL3 88h Capture/compare control 2 TBCCTL2 86h Capture/compare control TBCCTL 84h Capture/compare control TBCCTL 82h Timer_B control TBCTL 8h Timer_B interrupt vector TBIV Eh Timer_A3 Reserved 7Eh Reserved 7Ch Reserved 7Ah Reserved 78h Capture/compare register 2 TACCR2 76h Capture/compare register TACCR 74h Capture/compare register TACCR 72h Timer_A register TAR 7h Reserved 6Eh Reserved 6Ch Reserved 6Ah Reserved 68h Capture/compare control 2 TACCTL2 66h Capture/compare control TACCTL 64h Capture/compare control TACCTL 62h Timer_A control TACTL 6h Timer_A interrupt vector TAIV 2Eh Multiply py Sum extend SUMEXT 3Eh (MSP43x44x only) Result high word RESHI 3Ch Result low word RESLO 3Ah Second operand OP2 38h Multiply signed + accumulate/operand MACS 36h Multiply + accumulate/operand MAC 34h Multiply signed/operand MPYS 32h Multiply unsigned/operand MPY 3h NOTE 4: Timer_B7 in the MSP43x44x family has seven CCRs; Timer_B3 in the MSP43x43x family has three CCRs. 22 POST OFFICE BOX DALLAS, TEXAS 75265

23 SLAS344B JANUARY 22 REVISED OCTOBER 22 peripheral file map (continued) PERIPHERALS WITH WORD ACCESS (CONTINUED) Flash Flash control 3 FCTL3 2Ch Flash control 2 FCTL2 2Ah Flash control FCTL 28h ADC2 Conversion memory 5 ADC2MEM5 5Eh Conversion memory 4 ADC2MEM4 5Ch Conversion memory 3 ADC2MEM3 5Ah Conversion memory 2 ADC2MEM2 58h Conversion memory ADC2MEM 56h Conversion memory ADC2MEM 54h Conversion memory 9 ADC2MEM9 52h Conversion memory 8 ADC2MEM8 5h Conversion memory 7 ADC2MEM7 4Eh Conversion memory 6 ADC2MEM6 4Ch Conversion memory 5 ADC2MEM5 4Ah Conversion memory 4 ADC2MEM4 48h Conversion memory 3 ADC2MEM3 46h Conversion memory 2 ADC2MEM2 44h Conversion memory ADC2MEM 42h Conversion memory ADC2MEM 4h Interrupt-vector-word register ADC2IV A8h Inerrupt-enable register ADC2IE A6h Inerrupt-flag register ADC2IFG A4h Control register ADC2CTL A2h Control register ADC2CTL Ah ADC memory-control register5 ADC2MCTL5 8Fh ADC memory-control register4 ADC2MCTL4 8Eh ADC memory-control register3 ADC2MCTL3 8Dh ADC memory-control register2 ADC2MCTL2 8Ch ADC memory-control register ADC2MCTL 8Bh ADC memory-control register ADC2MCTL 8Ah ADC memory-control register9 ADC2MCTL9 89h ADC memory-control register8 ADC2MCTL8 88h ADC memory-control register7 ADC2MCTL7 87h ADC memory-control register6 ADC2MCTL6 86h ADC memory-control register5 ADC2MCTL5 85h ADC memory-control register4 ADC2MCTL4 84h ADC memory-control register3 ADC2MCTL3 83h ADC memory-control register2 ADC2MCTL2 82h ADC memory-control register ADC2MCTL 8h ADC memory-control register ADC2MCTL 8h POST OFFICE BOX DALLAS, TEXAS

24 SLAS344B JANUARY 22 REVISED OCTOBER 22 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS LCD LCD memory 2 : LCD memory 6 LCD memory 5 : LCD memory LCD control and mode LCDM2 : LCDM6 LCDM5 : LCDM LCDCTL A4h : Ah 9Fh : 9h 9h USART Transmit buffer UTXBUF 7Fh (Only in x44x) Receive buffer URXBUF 7Eh Baud rate UBR 7Dh Baud rate UBR 7Ch Modulation control UMCTL 7Bh Receive control URCTL 7Ah Transmit control UTCTL 79h USART control UCTL 78h USART Transmit buffer UTXBUF 77h Receive buffer URXBUF 76h Baud rate UBR 75h Baud rate UBR 74h Modulation control UMCTL 73h Receive control URCTL 72h Transmit control UTCTL 7h USART control UCTL 7h Comparator_A Comparator_A port disable CAPD 5Bh Comparator_A control2 CACTL2 5Ah Comparator_A control CACTL 59h BrownOUT, SVS SVS control register (Reset by brownout signal) SVSCTL 56h FLL+ Clock FLL+ Control FLL_CTL 54h FLL+ Control FLL_CTL 53h System clock frequency control SCFQCTL 52h System clock frequency integrator SCFI 5h System clock frequency integrator SCFI 5h Basic Timer BT counter2 BT counter BT control BTCNT2 BTCNT BTCTL 47h 46h 4h Port P6 Port P6 selection P6SEL 37h Port P6 direction P6DIR 36h Port P6 output P6OUT 35h Port P6 input P6IN 34h Port P5 Port P5 selection P5SEL 33h Port P5 direction P5DIR 32h Port P5 output P5OUT 3h Port P5 input P5IN 3h 24 POST OFFICE BOX DALLAS, TEXAS 75265

25 peripheral file map (continued) PERIPHERALS WITH BYTE ACCESS SLAS344B JANUARY 22 REVISED OCTOBER 22 Port P4 Port P4 selection P4SEL Fh Port P4 direction P4DIR Eh Port P4 output P4OUT Dh Port P4 input P4IN Ch Port P3 Port P3 selection P3SEL Bh Port P3 direction P3DIR Ah Port P3 output P3OUT 9h Port P3 input P3IN 8h Port P2 Port P2 selection P2SEL 2Eh Port P2 interrupt enable P2IE 2Dh Port P2 interrupt-edge select P2IES 2Ch Port P2 interrupt flag P2IFG 2Bh Port P2 direction P2DIR 2Ah Port P2 output P2OUT 29h Port P2 input P2IN 28h Port P Port P selection PSEL 26h Port P interrupt enable PIE 25h Port P interrupt-edge select PIES 24h Port P interrupt flag PIFG 23h Port P direction PDIR 22h Port P output POUT 2h Port P input PIN 2h Special functions SFR module enable2 ME2 5h SFR module enable ME 4h SFR interrupt flag2 IFG2 3h SFR interrupt flag IFG 2h SFR interrupt enable2 IE2 h SFR interrupt enable IE h absolute maximum ratings over operating free-air temperature (unless otherwise noted) Voltage applied at V CC to V SS V to 4. V Voltage applied to any pin (referenced to V SS ) V to V CC +.3 V Diode current at any device terminal ±2 ma Storage temperature, T stg : (unprogrammed device) C to 5 C (programmed device) C to 85 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. POST OFFICE BOX DALLAS, TEXAS

26 SLAS344B JANUARY 22 REVISED OCTOBER 22 recommended operating conditions Supply voltage during program execution, VCC (AVCC = DVCC = DVCC2 = VCC) Supply voltage during flash memory programming, VCC (AVCC = DVCC = DVCC2 = VCC) Supply voltage during program execution, SVS enabled (see Note ), VCC (AVCC = DVCC = DVCC2 = VCC) MSP43F43x, MSP43F44x MSP43F43x, MSP43F44x MSP43F43x, MSP43F44x MIN NOM MAX UNITS V V V Supply voltage, VSS (AVSS = DVSS = DVSS2 = VSS) V Operating free-air temperature range, TA LFXT crystal frequency, f(lfxt) (see Note 2) XT2 crystal frequency, enc f(xt2) Processor frequency enc (signal MCLK), f(system) Flash-timing-generator frequency, f(ftg) Cumulative program time, t(cpt) (see Note 3) LF selected, XTS_FLL= XT selected, XTS_FLL= XT selected, XTS_FLL= Mass erase time, t(meras) (See the flash memory, timing generator, control register FCTL2 section and Note 4) MSP43x43x MSP43x44x 4 85 C Watch crystal khz Ceramic resonator 45 8 khz Crystal 8 khz Ceramic resonator 45 8 Crystal 8 VCC =.8 V DC 4.5 VCC = 3.6 V DC 8 MSP43F43x, MSP43F44x VCC = 2.7 V/3.6 V MSP43F43x MSP43F44x khz MHz khz 3 ms VCC = 2.7 V/3.6 V 2 ms Low-level input voltage (TCK, TMS, TDI, RST/NMI), VIL (excluding Xin, Xout) VCC = 2.2 V/3 V VSS VSS +.6 V High-level input voltage (TCK, TMS, TDI, RST/NMI), VIH (excluding Xin, Xout) Input levels at Xin and Xout NOTES: VCC = 2.2 V/3 V.8 VCC VCC V VIL(Xin, Xout) VCC = 2.2 V/3 V VSS.2 VCC V VIH(Xin, Xout).8 VCC VCC. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS circuitry. 2. In LF mode, the LFXT oscillator requires a watch crystal. In XT mode, LFXT accepts a ceramic resonator or a crystal. 3. The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if segment write option is used. 4. The mass erase duration generated by the flash timing generator is at least. ms. The cumulative mass erase time needed is 2 ms. This can be achieved by repeating the mass erase operation until the cumulative mass erase time is met (a minimum of 9 cycles may be required). 26 POST OFFICE BOX DALLAS, TEXAS 75265