SpaceWire Router - Status

Transcription

1 Router - Status Working Group Meeting Dr. Stephan Fischer Dr. Steve Parkes Gerald Kempf Pierre Fabry EADS Astrium GmbH University of Dundee Austrian Aerospace GmbH ESA ESA, Noordwijk 15. Sep. 004 Outline Introduction Router Description / Functionality Project Description Router Validation Approach Project Schedule

2 Introduction Network MEMORY 1 SENSOR ROUTER 1 Router P 1 P SENSOR 1 ROUTER Router P 3 P Processor Array MEMORY 3 Router Description Routing Switches Routing Switch Link Interface Link Interface Routing Matrix Link Interface Link Interface Link Interfaces connected via a routing matrix 4

3 Router Description Router (ASIC) Interfaces Port 1 Port Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Control Logic Non-blocking Crossbar Switch Routing Table Status/Error Registers Control Registers Configuration Port Status Outputs External Input/Output External Input/Output Input FIFO Output FIFO External Port Input FIFO Output FIFO External Port Tick Counter Time-Code Inputs/Outputs 5 Router Functionality Addressing Packets path addressing direct specification of the path through a network leading character of a packet gives the output port number of the router leading character is removed after output port is determined passing through several routers is done by multiple destination characters logical addressing indirect specification of the path through a network usage of routing tables in the router leading character gives logical address leading character is not removed 6

4 Router Functionality Group Adaptive Routing If or more output ports lead to the same designation, they can be configured as a group Address Port 0 Port 1 Port Port 3 Port 4 Configuration Hardware Addressing Logical Addressing Router Functionality Group Adaptive Routing Advantages: Bandwidth sharing - if or more links are organized in a group the data can take either way - this leads to twice the bandwidth of a single link Fault Tolerance - if or more links are organized in a group and one link fails, the information can flow via the other links - no network management needed - automatic and immediate fault recovery - only packet which was transmitted when the fault occurred is lost 8

5 Router Functionality Priority Packet Delivery if two input ports have to use the same output port an arbitration scheme is used the arbitration scheme can include a priority scheme no priority flag available in packet header priority scheme is included in routing table 9 Router ASIC SpW Router ASIC implemented in an Atmel MH1RT gate array (max 519kGates) package 196 pin ceramic Metric Quad Flat 5 mil pin spacing Radiation tolerance 0.35µm CMOS process: 300k rad SEU free cells up to 100MeV (for critical memory cells) latch up immunity up to 100MeV Maximum baud-rate: 00Mbit/s Power consumption: ~4Watt (at max data rate) Single supply voltage: 3.3V (+0.3V) 10

6 Validation Approach -PCI Node with SMCS33 FPGA Cascaded routers -PCI Node with SMCS33 FPGA PC PC Monitor box Logic Analyser Monitor box Software applications in PCs provide packet source, packet sink and network configuration functions. 11 Developed Validation Tools Monitor monitors traffic on a link Validation SW controls the SpW network and contains the test cases PCI- Card a fully SpW compliant node, new SMCS33SpW FPGA SpW Router FPGA Testboard Testboard containing the Router FPGA SpW Router ASIC Testboard Testboard containing the Router ASIC 1

7 Project Description Teaming: EADS Astrium GmbH (prime) University of Dundee (subco) Austrian Aerospace GmbH (subco) Work: Router Specification, Design VHDL code generation Router Verification FPGA implementation Development of Validation Tools Validation Exercise ASIC design / manufacturing ASIC Validation 13 Status: done done done done almost done running not started not started detailed Schedule Nr. Task Name 54 Group : Router FPGA Validation 55 WP 0400: Management Group 56 WP 100: Validation Exercise 57 Validation Results 58 WP 00: Analysis and Recommendation 59 WP 300: Upgrade of PCBs 60 WP 400: Recommendation for 61 WP 500: Validation Plan for ASICs 6 Group Review ESM WP 3.5 VHDL model update 65 ESM WP 3.0 Design Update 66 ESM WP 3.1 Detailed Design 67 ESM WP 3. Layout and Post-Layout Verificatio 68 ESM WP 3.3 Prototyp Manufacturing 69 ESM WP 3.4 Transfer of Design and Knowledg 70 ESM-006 Router ASIC delivery 71 7 Group 3: Router ASIC Validation 73 WP 0500: Management Group 3 74 WP 3100: Manufacture & Assembly of PCBs 75 WP 300: Upgrade of Test S/W 76 WP 3300: Validation Exercise 77 WP 3400: Analysis of Results Final Presentation 3.Q04 4.Q04 1.Q05.Q05 3.Q05 4.Q05 Jul Aug Sep Okt Nov Dez Jan Feb Mrz Apr Mai Jun Jul Aug Sep Okt Nov

8 Schedule Project KO: January 00 Router FPGA: February 004 Validation Exercise completed: October 004 Router ASIC Prototype: June