Exploring SoC Communication Architectures for Performance and Power

Transcription

1 Exploring SoC Communication Architectures for Performance and Power Nikil Dutt ACES Laboratory Center for Embedded Computer Systems Donald Bren School of Information and Computer Sciences University of California, Irvine

2 Outline Motivation CA Exploration at Transaction Level Floorplan-aware Bus Architecture Synthesis Approach SoC Power/Energy Modeling Design Drivers Summary UCSD Talk Feb # 2

3 SoC Design Complexity vs. Productivity Complexity Logic Transistors per Chip (K) 10B 1B 100M 10M 1M 100K 10K 1K 1981 Logic Transistors/Chip Transistor/Staff Month 58%/Yr. compound Complexity growth rate %/Yr. compound Productivity growth rate M 10M 1M 100K 10K 1K Productivity Transistors/Staff Month Source: SEMATECH SoC designs today are complex, characterized by more and more s being integrated on a single chip, and a shrinking time-to-market UCSD Talk Feb # 3

4 Strategies to handle SoC complexity based design and reuse design s to be reused in multiple designs requires initial investment to create reusable cores; but productivity in subsequent designs can be substantially enhanced with reuse e.g. VSIA and OCP- core interface standards Raising modeling abstraction simulating design at RTL level for verification or exploration is just not practical anymore capturing the system (hardware and software) at a higher level of abstraction is better faster to model quicker to simulate early design visibility reduces time-to-market models are typically captured in C/C++/SystemC UCSD Talk Feb # 4

5 Ideal Platform based SoC Design Flow algorithm algorithm selection selection optimization optimization application requirements HW/SW HW/SW partitioning partitioning behavior behavior mapping mapping architecture architecture exploration exploration CA CA selection/exploration selection/exploration protocol protocol generation generation topology topology synthesis synthesis functional model architecture model communication model INPUT CPU CPU CPU M S M S M M OUTPUT interface interface synthesis synthesis cycle cycle scheduling scheduling implementation model CPU S M CPU S M S CPU S Logic synthesis and physical implementation UCSD Talk Feb # 5

6 Data Flow Replacing Data Processing As Major SoC Design Challenge µp µp Mem Bus DRAMC Core 1 Core N Main Bus Core 2 µp Sub system I/O Bus SoCs Circa 2002 SoCs Circa 2005 Critical Decision Was up Choice Exploding core counts requiring more advanced Interconnects EDA cannot solve this architectural problem easily Complexity too high to hand craft (and verify!) Critical Decision Is Interconnect Choice Communication Architecture Design and Verification becoming Highest Priority in Contemporary SoC Design! UCSD Talk Feb # 6 Source: SONICS Inc.

7 Need for Communication-centric Design Flow communication architecture consumes upto 50% of total on-chip power! ever increasing number of wires, repeaters, bus components (arbiters, bridges, decoders etc.) increases system cost communication is THE most critical aspect affecting system performance communication architecture design, customization, exploration, verification and implementation takes up the largest chunk of a design cycle Communication Architectures in today s complex systems significantly affect performance, power, cost and time-to-market! UCSD Talk Feb # 7

8 Evolution of On-chip Communication Architectures custom shared bus hierarchical bus bus matrix Network-on-chips? time UCSD Talk Feb # 8

9 Evolution of On-chip Communication Architectures custom shared bus hierarchical bus bus matrix Network-on-chips? time Focus of this talk! UCSD Talk Feb # 9

10 SoC Bus based Communication Architectures BRIDGE a) single bus b) hierarchical bus c) multiple bus d) split-bus e) point-to-point bus f) bus matrix UCSD Talk Feb # 10

11 Bus Terminology Master (or Initiator) component that initiates a read or write data transfer Slave (or Target) component that does not initiate transfers and only responds to incoming transfer requests Arbiter Controls access to the shared bus Uses arbitration scheme to select master to grant access to bus Decoder Determines which component a transfer is intended for Bridge Connects two busses Acts as slave on one side and master on the other UCSD Talk Feb # 11

12 Modern SoC Design Flow algorithm selection optimization allocation behavior partitioning scheduling protocol selection channel partitioning arbitration cycle scheduling protocol scheduling Product requirements from customer Specification Model Architecture Model Communication Model Implementation Model UCSD Talk Feb # 12

13 Bus-based Communication Architectures Several bus based CA commonly used in SoC designs AMBA Wishbone CoreConnect PowerPC Bus Key Features High Performance System Bus processors, memory, DMA etc. Low Bandwidth Peripheral Bus timer, interrupt controller, UART etc. UCSD Talk Feb # 13

14 Outline Motivation CA Exploration at Transaction Level Floorplan-aware Bus Architecture Synthesis Approach SoC Power/Energy Modeling Design Drivers Summary UCSD Talk Feb # 14

15 Issues Selecting and configuring busbased CA for optimal performance is a critical activity in a SoC design, requiring CA exploration PE Interface bus architecture (e.g. PPC Bus, AMBA, CoreConnect) architecture parameters (e.g. bus width, burst size)? Interface PE bus topologies (e.g. shared, hierarchical) protocol choices (e.g. arbitration strategies) Interface PE UCSD Talk Feb # 15

16 Bus Exploration at what Abstraction? Cycle Rate (Hz) Technology 10 8 Silicon Reference Design 10 6 HW Emulator 10 5 Transaction Model 10 4 Cycle Accurate Model 10 2 RTL Model 10 Gate Level Model Capturing a SoC design at RTL level and then simulating for communication space exploration is too slow (~ cycles/s) cumbersome to capture all the detail too late in the design flow for exploration! UCSD Talk Feb # 16

17 Communication Space Exploration Abstraction Levels Algorithm TLM T-BCA PA-BCA CA Register Transfer Level UCSD Talk Feb # 17

18 Communication Space Exploration Abstraction Levels Algorithm TLM T-BCA PA-BCA CA Register Transfer Level UCSD Talk Feb # 18

19 Existing Abstractions for Exploration above RTL: Cycle Accurate (CA) Models master var1 = a + b; wait(); REG = d<<var1; wait(); HREQ.set(1); e = REG4 0xff wait(); bus arb pin interface slave case CTR_WR: CTR_WR = in; wait(); CTR_WR =0xf; wait(); ST_RG = in 0x1 wait(); Algorithm TLM T-BCA Detailed system debug and analysis PA-BCA Time consuming to model -/1 to /3 RTL Too slow for exploring SoC designs -100x RTL CA Register Transfer Level UCSD Talk Feb # 19

20 Existing Abstractions for Exploration above RTL: Pin-accurate Bus Cycle Accurate (PA-BCA) Models master var1 = a + b; REG = d<<var1; HREQ.set(1); e = REG4 0xff wait(3, SC_NS); bus arb pin interface slave case CTR_WR: CTR_WR = in; CTR_WR =0xf; ST_RG = in 0x1 wait(3,sc_ns); Algorithm TLM T-BCA High level system exploration Still time consuming to model - /5 to /10 RTL Still slow for exploring SoC designs - 100x to 500x RTL PA-BCA CA Register Transfer Level UCSD Talk Feb # 20

21 Existing Abstractions for Exploration above RTL: Transaction Level Models (TLM) master var1 = a + b; d = d << var1; request(port1); e = REG4 0xff wait(); channel bus arb slave case CTR_WR: CTR_WR = in; CTR_WR =0xf; ST_RG = in 0x1 wait(); generic channel interface Algorithm TLM T-BCA High level system validation and embedded software development PA-BCA Fast to model - /10 to /50 RTL Fast simulation speed, but model not too detailed for exploring SoC designs - >>1000x RTL CA Register Transfer Level UCSD Talk Feb # 21

22 Existing Abstractions for Exploration above RTL: Transaction-based BCA (T-BCA) Models master var1 = a + b; d = d << var1; request(port1); e = REG4 0xff wait(3, SC_NS); HSEL.set(1); bus arb slave case CTR_WR: CTR_WR = in; CTR_WR =0xf; ST_RG = in 0x1 wait(3, SC_NS); pin, transaction interface Algorithm TLM T-BCA Uses Transaction Level Modeling (TLM) techniques to speed up BCA model simulation PA-BCA Time to model varies Simulation speed generally faster than PA-BCA CA Register Transfer Level UCSD Talk Feb # 22

23 Previous work in T-BCA Modeling Xinping et al. (ICCAD 2002) use function calls instead of slower signal semantics to model AMBA2 and CoreConnect resulting models not detailed enough for accurate CA exploration Caldari et al. (DATE 2003) similarly model AMBA2 using function calls for reads/writes Bus signals are also modeled : slows simulation Clocked threads used extensively : slows simulation Ogawa et al. (DATE 2003) also model data transfers in AMBA2 using read/write transactions use low level handshaking semantics In mid 2003, ARM released the AHB Cycle-Level Interface Specification for modeling AMBA AHB at CA level in SystemC function calls emulate bus signals at interface Scope for improving speed by reducing number of calls UCSD Talk Feb # 23

24 CCATB Modeling Abstraction (DAC-2004) CCATB: Cycle Count Accurate at Transaction Boundaries Observe signals at transaction boundaries BUT maintain overall cycle accuracy essential for system exploration Variant of T-BCA Models no pins at interface extension of read(), write() transaction interface from TLM s modeled at behavioral level protocol details (e.g. burst size, cache hints) need to be passed Modeling Language SystemC fast (C/C++ native execution) provides constructs (concurrency, timing) for hardware modeling extensive commercial tool support (debugging, waveform viewing) Trades off intra transaction visibility for simulation speed more than 2x faster than fastest BCA models UCSD Talk Feb # 24

25 Timing Diagram CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 HBUSREQ_M1 HGRANT_M1 HMASTER[3:0] # 1 HTRANS[1:0] NSEQ SEQ SEQ SEQ NSEQ HADDR[31:0] A1 A2 A3 A4 HREADY HWDATA D_A1 D_A2 D_A3 D_A4 HBURST[2:0] HWRITE HSIZE[2:0] HPROT[3:0] control for burst INCR4 CCATB delay model wait (REQ + ARB + SLV + BURST_LEN + PPL) = ( ) = 9 cycles arbiter call to slave UCSD Talk Feb # 25

26 Timing Diagram CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 HBUSREQ_M1 HGRANT_M1 HMASTER[3:0] HTRANS[1:0] HADDR[31:0] # 1 CCATB: Observe signals at NSEQ SEQ SEQ SEQ NSEQ transaction boundaries only! A1 A2 A3 A4 HREADY HWDATA D_A1 D_A2 D_A3 D_A4 HBURST[2:0] HWRITE HSIZE[2:0] HPROT[3:0] control for burst INCR4 CCATB delay model wait (REQ + ARB + SLV + BURST_LEN + PPL) = ( ) = 9 cycles arbiter call to slave UCSD Talk Feb # 26

27 Delays Modeled Slave delay Communication delay Arbitration delay nirq nfiq ITC Timer1 TIMER Timer2 FAST MEMORY DMA Slave interface Slave interface Slave interface Slave interface AMBA 2.0 CHANNEL (Read, Write) ARBITER master interface master interface slave interface GENERATOR (esw) ARM CCM ISS (with esw) DUMMY MASTER 1 MEM CONTROLLER MEM1 MEM2 Master delay Interface delay Pasricha et al. [DAC 2004] UCSD Talk Feb # 27

28 Case Study: Multimedia SoC Subsystem ARM926EJ-S MEM1 MEM2 DMA AHB System bus USB 2.0 A/V Encoder SDRAM controller MEM3 MEM5 MEM4 AHB/APB Bridge ITC Timer APB peripheral bus UART Flash Interface GPIO UART AMBA 2.0 based multimedia subsystem for audio and video encoding Designer needs to add support for audio/video decoding additional AVlink interface for streaming data Maintain bandwidth constraints for USB (480 Mbps) and AVLink interface (768 Mbps) UCSD Talk Feb # 28

29 Extended Architecture Variation 1 ARM926EJ-S MEM1 MEM2 DMA USB 2.0 A/V Encoder AHB System bus SDRAM controller MEM3 AVLink controller MEM4 MEM5 A/V Decoder AHB/APB Bridge Arch Arbitration Scheme RR TDMA1 TDMA2 SP1 SP2 Arch Execution cycle count (in millions of cycles) UCSD Talk Feb # 29

30 Extended Architecture Variation 2 ARM926EJ-S MEM1 MEM2 DMA USB 2.0 A/V Encoder AHB System bus SDRAM controller MEM3 MEM4 MEM5 AHB/APB Bridge AHB System bus AHB/AHB Bridge MEM6 AVLink controller A/V Decoder Arch Arbitration Scheme RR TDMA1 TDMA2 SP1 SP2 Arch Arch Execution cycle count (in millions of cycles) UCSD Talk Feb # 30

31 Extended Architecture Variation 3 ARM926EJ-S MEM1 MEM2 DMA USB A/V Encoder AHB System bus SDRAM controller MEM3 MEM4 MEM5 MEM6 AHB/APB Bridge AHB System bus A/V Decoder AHB/AHB Bridge AHB System bus AVLink controller Arch Arbitration Scheme RR TDMA1 TDMA2 SP1 SP2 Arch Arch Arch Execution cycle count (in millions of cycles) UCSD Talk Feb # 31

32 Extended Architecture Variation 4 ARM926EJ-S MEM2 DMA MEM1 A/V Encoder AHB System bus SDRAM controller MEM3 MEM4 A/V Decoder MEM5 MEM6 AHB/APB Bridge AHB System bus USB 2.0 AHB/AHB Bridge AHB System bus AVLink controller Arch Arbitration Scheme RR TDMA1 TDMA2 SP1 SP2 Arch Arch Arch Arch Execution cycle count (in millions of cycles) UCSD Talk Feb # 32

33 Simulation Speed Comparison Goal is to compare simulation performance for Pin accurate BCA (PA-BCA) Transaction based BCA (T-BCA) CCATB We were interested in exploring effect of changing system complexity on simulation speed UCSD Talk Feb # 33

34 Example SoC Platform ARM926EJ-S Arbiter + Decoder AHB System bus 1 SDRAM controller AHB/APB Bridge ITC Timer APB peripheral bus ROM DMA RAM USB UART EMC Arbiter + Decoder Traffic generator1 AHB System bus 2 AHB/AHB Bridge Arbiter + Decoder Traffic generator2 AHB System bus 3 RAM Switch RAM Traffic generator3 UCSD Talk Feb # 34

35 Comparison Graph CCATB PA-BCA T-BCA Kcycles/sec masters UCSD Talk Feb # 35

36 Modeling Effort Comparison Model Abstraction Average CCATB speedup (x times) Modeling Effort CCATB 1 ~3 days T-BCA 1.67 ~4 days PA-BCA 2.2 ~1.5 wks UCSD Talk Feb # 36

37 CCATB Summary CCATB models Faster to simulate than PA-BCA models by 120% (average) T-BCA models by 67% (average) Less modeling effort compared to BCA models Since intra-transaction visibility is not a concern Accurate exploration of CA space Performance figures comparable in accuracy to detailed pin accurate BCA models Conveniently fit into SoC Design Flow Easy to extend TLM level models to get CCATB models Easy to refine down to pin accurate BCA level UCSD Talk Feb # 37

38 Outline Motivation CA Exploration at Transaction Level Floorplan-aware Bus Architecture Synthesis Approach SoC Power/Energy Modeling Design Drivers Summary UCSD Talk Feb # 38

39 Need for Physically-aware BA Synthesis Improving process technology has led to increasing number of cores being integrated on a single SoC Tens to hundreds of cores today Sharp increase in overall on-chip communication next generation of multimedia, broadband and networking apps Communication is fast becoming a major design bottleneck! Standard bus architectures such as AMBA, PPC Bus and CoreConnect are popular choices for handling on-chip communication Relatively simple to design Low area overhead UCSD Talk Feb # 39

40 Bus Architecture Synthesis S4 S4 MEM1 CPU1 S1 S1 M2 MEM2 S2 S2 Bus Architecture Synthesis main1 main2 M2 M2 MEM2b S1 S1 M3 M3 bridge bridge bridge S2 S2 S3 S3 periph MEM3 main3 S3 S3 M3 MEM3 MEM1 CPU1 S4 S4 MEM2a bridge Communication Parameter Space Bus Topology Space S3 MEM1 S3 S3 S3 S3 S3 S3 S3 periph periph X MEM2b M3 M2 M3 M2 MEM1 MEM2b M3 M2 M2 S1 M2 S1 periph MEM2b M3 M3 M3 S1 S1 M3 M2 S1 S1 bridge bridge main1 main1 S2 S2 S2 MEM3 main1 main1 S2 S2 S2 MEM3 bridge S2 S2 MEM3 main2 main2 main2 iterate through different design configurations! MEM1 CPU1 S4 MEM1 S4 CPU1 S4 S1 S4 S1 M2 M2 CPU1 S4 bridge S4 MEM2a MEM2a MEM2a MEM2a Arbitration strategy (RR, TDMA, static) Manual traversal of this vast exploration space not practical Data bus widths But designers today still create high level simulation models and manually Bus clock speeds DMA burst sizes UCSD Talk Feb # 40

41 Bus Cycle Time Violation 1 To meet performance constraints, bus speed set to 333 Mhz (3 ns bus cycle time) - excessive capacitive load on bus can increase signal propagation delay For load capacitance C L = pf, wire length = mm, implying delay of 3.5 ns Such a violation has adverse effect on system cost, complexity and constraint satisfiability Since BA synthesis decides cumulative C L on bus, there is a need to make BA synthesis physically aware To eliminate bus cycle violations, designers pipeline busses with latches, register slices - severely effects performance - considerable manual rework of RTL - extensive re-verification effort UCSD Talk Feb # 41

42 Our Approach: FABSYN (DAC-2005) S4 S4 MEM1 CPU1 S1 S1 M2 MEM2 S2 S2 Automated Bus Architecture Synthesis main1 main2 M2 M2 MEM2b S1 S1 M3 M3 bridge bridge bridge S2 S2 S3 S3 periph MEM3 main3 S3 S3 M3 MEM3 MEM1 CPU1 S4 S4 MEM2a bridge early BA exploration and timing violation detection / elimination verify feasibility of synthesized BA early in the design flow saves costly design iterations later increasingly important in the deep submicron era as clock speeds increase lengthy propagation delays cause timing violations Floorplan and Wire Delay Estimation Engine UCSD Talk Feb # 42

43 Related Work Automating Bus Architecture Synthesis Early work (Narayan et al. [DATE 94], Daveau et al. [TVLSI 97], Gasteier et al. [TODAES 99]) was aimed at minimizing bus width simple synchronization protocol selection topology generation for simple busses without arbitration Pinto et al. [DAC 02] and Ryu et al. [DATE 03] focused on automating bus topology synthesis Lahiri et al. [ICCAD 00] and Shin et al. [DATE 04] synthesized bus architecture parameters Using High Level Floorplanner in CA Synthesis Dick et al. [DATE 99], Drinic et al. [ICCAD 00], Hu et al. [ASPDAC 02] for estimating wire lengths to determine energy consumption and global delays for real time constraint satisfaction Bergamaschi et al. [CODES+ISSS 03] and Thepayasuwan et al. [DATE 04] for generating an early core placement estimate UCSD Talk Feb # 43

44 FABSYN: Our Approach (DAC-2005) FABSYN: Floorplan Aware Bus Architecture SYNthesis FABSYN automates bus topology synthesis, AND bus architecture parameter generation arbitration priorities bus widths bus speeds DMA burst sizes Unlike previous approaches, we use a floorplanner to identify and eliminate bus cycle time violations UCSD Talk Feb # 44

45 Problem Formulation Given: SoC with performance constraints a target bus-based communication architecture (e.g. AMBA) Assumptions: hardware-software partitioning has been done already s are standard non-modifiable black box components memories can be split and modified Goals: automatically synthesize BA topology AND parameter values detect/eliminate BA configurations with bus cycle time violations satisfy all throughput constraints in the design minimize implementation cost UCSD Talk Feb # 45

46 SoC Performance Constraints SoC designs have performance constraints that can be represented in terms of Data Throughput Constraints Communication Throughput Graph, CTG = G(V,A) incorporates SoC components and throughput constraints Throughput Constraint Path (TCP) is a CTG sub-graph MEM1 M2 360 Mbps S4 S4 CPU1 S1 S1 MEM2 S2 S2 S3 S3 M3 MEM3 UCSD Talk Feb # 46

47 Bus Architecture Synthesis Flow Output CTG library comm arch. constraint Set (Ψ) preprocess simple bus mapping Select unsatisfied TCP from Ω explore_params output synthesized communication arch yes no Ω still empty? Run floorplanner and delay estimator Inputs TCP met? yes no mutate_topology no Ω empty? optimize_design yes UCSD Talk Feb # 47

48 preprocess MEM1 M2 MEM1 M2 S4 S4 CPU1 S3 S3 M3 S1 S1 MEM2 MEM3 S2 S2 split S4 S4 MEM2a CPU1 S3 S3 M3 S1 S1 MEM2b MEM3 S2 S2 MEM1 M2 cluster S4 S4 MEM2a CPU1 S1 S1 MEM2b S2 S2 S3 S3 M3 MEM3 UCSD Talk Feb # 48

49 Bus Architecture Synthesis Flow CTG library comm arch. constraint Set (Ψ) preprocess simple bus mapping Select unsatisfied TCP from Ω explore_params output synthesized communication arch yes no Ω still empty? Run floorplanner and delay estimator TCP met? no mutate_topology no optimize_design yes Ω empty? yes UCSD Talk Feb # 49

50 Simple Bus Mapping MEM1 M2 S4 S4 MEM2a CPU1 S1 S1 MEM2b S2 S2 S3 S3 M3 MEM3 Bus mapping bridge CPU1 subsys subsys MEM1 M2 M3 S1 S1 MEM2b S3 S3 S2 S2 MEM3 main peripheral UCSD Talk Feb # 50

51 Bus Architecture Synthesis Flow CTG library comm arch. constraint Set (Ψ) Communication Parameter Constraint Set (Ψ) preprocess simple bus mapping Select unsatisfied TCP from Ω explore_params output synthesized communication arch To ensure that our approach generates realistic BA Constraints are in the form of a discrete set of valid no values for BA parameters to be synthesized Ω still empty? Allows designer to bias the synthesis process based on knowledge of the design and technology being targeted yes Run floorplanner and delay estimator TCP met? no mutate_topology no optimize_design yes Ω empty? yes UCSD Talk Feb # 51

52 explore_params Set (bus speed, bus width) <= Ψ(max_speed, max_width) Select unselected combination of valid arbitration priority ordering and valid DMA burst size All valid comb covered? N Simulate design Y exit Communication Y behavior is characterized by unpredictability TCP violation? - Dynamic bus requests from cores - Non-deterministic delay N arbitration conflicts - Buffer Remove overflow satisfied delays TCP from Ω Simulation necessary for accuracy in performance estimation Simulate We use design a SystemC for remaining based DMA fast transaction-based, burst sizes bus cycle to prune DMA burst size set accurate modeling abstraction (Pasricha et al. [DAC 04]) UCSD Talk Feb # 52

53 Bus Architecture Synthesis Flow CTG library comm arch. constraint Set (Ψ) preprocess simple bus mapping Select unsatisfied TCP from Ω explore_params output synthesized communication arch yes no Ω still empty? Run floorplanner and delay estimator TCP met? no mutate_topology no optimize_design yes Ω empty? yes UCSD Talk Feb # 53

54 mutate_topology bridge CPU1 subsys subsys MEM1 M2 M3 S1 S1 MEM2b S3 S3 S2 S2 MEM3 main bridge peripheral Create new bus and/or migrate s CPU1 subsys subsys MEM1 M2 M3 S1 S1 MEM2b S3 S3 S2 S2 MEM3 main2 main1 peripheral UCSD Talk Feb # 54

55 mutate_topology bridge CPU1 subsys subsys S1 S1 MEM1 M2 M3 MEM2b S3 S3 S2 S2 MEM3 main2 main1 bridge peripheral Create new bus and/or migrate s CPU1 subsys subsys MEM1 M2 S1 S1 M3 MEM2b S3 S3 S2 S2 MEM3 main3 main2 main1 peripheral UCSD Talk Feb # 55

56 Bus Architecture Synthesis Flow CTG library comm arch. constraint Set (Ψ) preprocess simple bus mapping Select unsatisfied TCP from Ω explore_params output synthesized communication arch yes no Ω still empty? Run floorplanner and delay estimator TCP met? no mutate_topology no optimize_design yes Ω empty? yes UCSD Talk Feb # 56

57 Bus Architecture Synthesis Flow CTG library comm arch. constraint Set (Ψ) preprocess simple bus mapping Select unsatisfied TCP from Ω explore_params output synthesized communication arch yes no Ω still empty? Run floorplanner and delay estimator TCP met? no mutate_topology no optimize_design yes Ω empty? yes UCSD Talk Feb # 57

58 Bus Architecture Synthesis Flow CTG library comm arch. constraint Set (Ψ) preprocess simple bus mapping Select unsatisfied TCP from Ω explore_params output synthesized communication arch yes no Ω still empty? Run floorplanner and delay estimator TCP met? no mutate_topology no optimize_design yes Ω empty? yes UCSD Talk Feb # 58

59 Floorplanning and Wire Delay Estimation Our floorplanner is adapted from the simulated annealing based floorplanner proposed by Adya and Markov et al. [TVLSI 03] The input to the floorplanner is a list of components and their interconnections in the system area of components dimensions of components (widths/heights or aspect ratios) maximum die size (optional) fixed locations for hard macros (optional) We use the following cost function with the floorplanner: Cost = w 1.Area + w 2.BusWL + w 3.TotalWL The wire delay estimation is adapted from the models proposed by Cong and Pan [ICCAD 01] UCSD Talk Feb # 59

60 Bus Architecture Synthesis Flow CTG library comm arch. constraint Set (Ψ) preprocess simple bus mapping Select unsatisfied TCP from Ω explore_params output synthesized communication arch yes no Ω still empty? Run floorplanner and delay estimator TCP met? no mutate_topology no optimize_design yes Ω empty? yes UCSD Talk Feb # 60

61 Synthesized Bus Architecture bridge main3 main1 CPU1 subsys subsys M2 M2 MEM1 main2 S1 S1 M2 S1 S1 M3 MEM2b Parameter main1 peripheral bridge S3 S3 S2 S2 Values MEM3 main1 main2 main3 periph bus width bus speed arb priority CPU1 > M3 > M2 (static) S3 S3 periph main2 MEM2b M3 M3 bridge bridge S2 S2 MEM3 main3 MEM1 CPU1 S4 S4 bridge MEM2a UCSD Talk Feb # 61

62 Case Study 1 ITC ITC ROM ROM Set ARM926 ARM926 bus speed ASIC1 ASIC1 33, 66, 100, 133, RAM3 RAM3 166, 200 USB USB RTC RTC Communication Parameter TIMER TIMER Constraint Set (Ψ) UART UART SDRAM Values SDRAM IF IF bus width 8, 16, 32 DMA burst size 1, 2, 4, 8, 16 arbitration strategy SWITCH SWITCH static priority RAM2 RAM2 EXT EXT IF IF DMA DMA RAM1 RAM1 UCSD Talk Feb # 62

63 Case Study 1 ARM926 AHB1 Parameter RAM3 EXT_IF ROM ASIC1 bus width 32 RAM1 32DMA 32 BRIDGE1 32 USB 2.0 VIC BRIDGE2 SDRAM_IF TIMER AHB2 bus speed dma size 16 BRIDGE3 arb priority AHB3 Communication Parameter Values Values arbiter arbiter arbiter UART AHB1 AHB2 AHB3 APB1 APB1 RTC ARM>USB> DMA> EXT_IF>ASIC1>SWITCH SWITCH RAM2 UCSD Talk Feb # 63

64 Case Study 1 UCSD Talk Feb # 64

65 Case Study 2 ITC ITC ROM ROM Set ARM926 ASIC1 ASIC1 bus speed 33, 66, 100, 133, RAM3 166, RAM3 200 USB USB RTC RTC Communication Parameter TIMER TIMER Constraint Set (Ψ) UART UART SDRAM Values SDRAM IF IF bus width 8, 16, 32, 64 DMA burst size 1, 2, 4, 8, 16 SWITCH SWITCH arbitration strategy RAM4 RAM4 static priority ASIC2 ASIC2 RAM2 RAM2 EXT EXT IF IF DMA DMA RAM1 RAM1 UCSD Talk Feb # 65

66 Case Study 2 ARM926 AXI1 EXT_IF VIC BRIDGE2 UART APB1 RAM1 RAM3 ROM ASIC1 arbiter Excessive capacitive load causes bus cycle time arbiter violation DMA for AXI1 AXI2 BRIDGE1 TIMER RTC BRIDGE3 arbiter USB 2.0 SDRAM_IF AXI3 SWITCH RAM2 RAM4 ASIC2 UCSD Talk Feb # 66

67 Case Study 2 ARM926 AXI1 Parameter BRIDGE3 AXI3 RAM3 AXI2 EXT_IF Values arbiter ROM RAM1 ASIC1 USB 2.0 VIC DMA BRIDGE2 Migrate RAM1 to AXI2 arbiter SDRAM_IF BRIDGE1 TIMER arbiter UART APB1 RTC AXI1 AXI2 AXI3 APB1 bus width bus speed dma size 16 arb scheme Communication Parameter Values SWITCH>ASIC2>ARM>USB>EXT_IF>DMA>ASIC1 SWITCH RAM2 RAM4 ASIC2 UCSD Talk Feb # 67

68 Case Study 2 UCSD Talk Feb # 68

69 Synthesis Result Comparison CaseStudy1 Designs initial ABS manual FABSYN Number of Busses TCP constr. satisfied 0/2 2/2, not feasible 2/2 2/2 Exec. cycles (millions) Time to synthesize ~mins ~hours ~days ~hours CaseStudy2 Designs initial ABS manual FABSYN Number of Busses TCP constr. satisfied 0/3 3/3, not feasible 3/3 3/3 Exec. cycles (millions) Time to synthesize ~mins ~hours ~days ~hours UCSD Talk Feb # 69

70 FABSYN Summary FABSYN: Floorplan-Aware BA Synthesis bus topology and bus architecture parameter synthesis detect and eliminate bus cycle time violations satisfy performance constraints minimize implementation cost Results from BA synthesis for SoC case studies show usefulness of approach when compared to approaches without integrated floorplanners manual or semi-automated synthesis approaches Although experiments have been performed on AMBA BA, approach is portable to other standard BA such as PowerPC Bus and CoreConnect UCSD Talk Feb # 70

71 Outline Motivation CA Exploration at Transaction Level Floorplan-aware Bus Architecture Synthesis Approach SoC Power/Energy Modeling Design Drivers Summary UCSD Talk Feb # 71

72 Power/Energy Modeling Key Objective: SOC Power Optimization Framework Develop early power exploration environment for SOC designers Provide meaningful power-aware exploration with estimates that combine Previously characterized blocks New/customized blocks On-chip communication architectures Allow qualitative and quantitative comparison for power/energy of alternative SOC architectures UCSD Talk Feb # 72

73 SoCPower: Key Challenges SOC Component-level challenges Power characterization methodology Accuracy Variability Efficiency SOC-level system-level modeling challenges Interconnections/communication architectures Early Analysis and Modeling (physically aware!) Statistical vs. simulation tradeoffs Accuracy Variability Efficiency SOC-level system-level exploration challenges Impact of power budgeting Static Dynamic (power management) Tradeoffs between power, performance, cost.. Accuracy Variability Efficiency UCSD Talk Feb # 73

74 SoCPower Framework: Our Approach SOC-level power modeling components Interconnections/communication architecture Memory architecture Sizing, partitioning, banking, etc. Hardware/software partitioning and allocation ASIC, AS, coprocessor, DSP, etc. Interconnection/bus architecture exploration Single, multiple, hierarchical, crossbar, etc. Floorplanning and Thermal Effects Considering leakage power and temperature variations Algorithmic level tradeoffs Alternative algorithmic implementations with varying power, performance, cost UCSD Talk Feb # 74

75 SoCPower Framework Power Modeling/Prediction Approach SoC Template (e.g. AMBA) SoC Specs Explores bus, memory and component varieties Provides Early Area, size, length and performance estimates Estimation Library Area Timing Power Precharacterized components Software Test Bench SoC Modeling/ Simulation Power management Strategy E.g. Powerwise, IEM, etc Power, area, performance area vs. performance vs. power UCSD Talk Feb # 75

76 Outline Motivation CA Exploration at Transaction Level Floorplan-aware Bus Architecture Synthesis Approach SoC Power/Energy Modeling Design Drivers Summary UCSD Talk Feb # 76

77 Design Drivers Case Studies JPEG2000 encoder H.264 video decoder JPEG 2000 Encoder H.264 Decoder Preprocessing DWT Transform Quantization EBCOT encoder Context Modeling Tier-1 coder Arithmetic Coder Tier-2 coder UCSD Talk Feb # 77

78 Outline Motivation CA Exploration at Transaction Level Floorplan-aware Bus Architecture Synthesis Approach Power/Energy Modeling Design Drivers Summary UCSD Talk Feb # 78

79 Summary Presented work on SoC Performance and Power Modeling Key Concepts Communication Architecture Exploration for -based Design Transaction-Level Modeling Abstraction Integration of Physical Design Concerns Power/Energy Characterization at SoC Level Related Efforts in My Lab Specifications/Requirements Capture using SoC ADL ADL: Architecture Description Language Validation/Verification of SoC Specifications Formal, Semi-formal and Simulation Based Techniques ADL-driven SoC Performance and Power Exploration UCSD Talk Feb # 79

80 Acknowledgements CCATB and FABSYN research done jointly with PhD student Sudeep Pasricha Conexant collaborator Dr. Mohamed Ben-Romdhane SOC Power Optimization Framework Research project jointly with Prof. Fadi Kurdahi, EECS, UCI Sponsors Conexant, Inc. and UC MICRO program NSF SRC UCSD Talk Feb # 80

81 Thank You! UCSD Talk Feb # 81

82 Related Publications [1] S. Pasricha, N. Dutt, M. Ben-Romdhane, Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration, DAC 2004 [2] S. Pasricha, N. Dutt, M. Ben-Romdhane, Fast Exploration of Busbased On-Chip Communication Architectures", CODES+ISSS 2004 [3] S. Pasricha, N. Dutt, M. Ben-Romdhane, "Automated Throughputdriven Synthesis of Bus-based Communication Architectures", ASPDAC 2005 [4] S. Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, "Floorplanaware Automated Synthesis of Bus-based Communication Architectures", DAC 2005 [5] S. Pasricha, N. Dutt, M. Ben-Romdhane, Constraint-Driven Bus Matrix Synthesis for MPSOCs", ASPDAC 2006 UCSD Talk Feb # 82

83 Back-up slides from ASAP UCSD Talk Feb # 83

84 CCATB Transaction Token Fields Request field m_data m_burst_length m_burst_type m_byte_enable m_read m_lock m_cache m_prot m_transid m_busy_idle m_id Description pointer to an array of data length of transaction burst type of burst (incr, fixed, wrapping etc.) byte enable strobe for unaligned transfers indicates whether transaction is read/write lock bus during transaction cache/buffer hints protection modes transaction ID (needed for OO access) schedule of busy/idle cycles from master ID for identifying the master UCSD Talk Feb # 84

85 Back-up slides from DAC UCSD Talk Feb # 85

86 UCSD Talk Feb # 86 Wire Delay Estimation Then the delay for a wire of length l, is given by where L d a 2 C R rc 2 1 = α l c l R rc R c l W l 2 l W l R C T f a d f d o d. ) ( ) ( = α α α α 1 rc a 4 1 = α = = = k j j j i i L C l l C 1 1. = = k j L j O C C C 1

87 Wire Delay Estimation Inputs to the wire delay estimation engine are wire lengths from the floorplanner and the capacitive loads (CL) of component output pins l 1 l 2 l k (a) R d C 1 C 2 C k-1 C k l (b) Rd C 0 C L The wire delay estimation is adapted from the models proposed by Cong and Pan [ICCAD 01] UCSD Talk Feb # 87

88 Wire Delay Estimation Other parameters include W(x) is Lambert s W function defined as the value of w which satisfies we w =x R d is the resistance of the driver l is the wire length process technology dependent parameters (shown in Table) r is the sheet resistance in Ω/sq, c a is unit area capacitance in ff/µm2 c f is unit fringing capacitance in ff/µm (sum of fringing and coupling cap.) Tech (µm) r c a c f UCSD Talk Feb # 88

89 Detecting Bus Cycle Time Violations 1 and 2 are connected to the same bus as ASIC1, Mem4, ARM, VIC and DMA To meet throughput constraints, bus speed is set to 333 Mhz implies a bus cycle time of 3 ns For a 0.13 µm process, R d = 0.4 kω, C L = pf and C O = pf the floorplanner finds wire length = 9.9 mm between pins connecting the two s to the bus Implies a wire delay of 3.5 ns. This is a violation of the clock cycle time constraint of 3 ns Our BA synthesis flow attempts to automatically eliminate such violations once they are detected UCSD Talk Feb # 89

90 Related Work Other approaches have made use of high level floorplanner before, but for different reasons Dick et al. [DATE 99] invoked it to obtain global wiring delays to ensure that real time deadlines were met during custom bus topology synthesis Drinic et al. [ICCAD 00] used it to determine design feasibility by comparing estimates of wire length with an upper bound on wire length Hu et al. [ASPDAC 02] used it to estimate wire length, for calculating energy consumption in point to point networks Bergamaschi et al. [CODES+ISSS 03] and Thepayasuwan et al. [DATE 04] used it to generate an early core placement estimate UCSD Talk Feb # 90

91 SoC Performance Constraints SoC designs have performance constraints that can be represented in terms of Data Throughput Constraints Communication Throughput Graph (CTG) incorporates SoC components and throughput constraints, where each edge connects 2 communicating components each vertex represents a component and information about its area dimensions capacitive loads on output pins which bus type it connects to Throughput Constraint Path (TCP) is a sub-graph of a CTG that contains a master for which data throughput must be maintained, and includes other masters, slaves and memories in the critical path UCSD Talk Feb # 91

92 optimize_design Select previously unselected bus from BA Reduce bus width. Simulate TCP violation? N N Y Undo bus width reduction all busses examined? Y exit Reduce bus speed. Simulate N TCP violation? reduces system cost Y lower bus speed implies larger bus cycle time, (less probability of bus Undo cycle bus time width violation) reduction Reducing bus widths and speeds UCSD Talk Feb # 92

93 Why worry about power? -- Chip Power Density Sun s Surface Power Density (W/cm2) Nuclear Reactor Hot Plate Rocket Nozzle P6 Pentium chips might become hot Year Source: Borkar, De Intel UCSD Talk Feb # 93

94 Why worry about power? -- Standby Power Year Power supply V dd (V) Threshold V T (V) Drain leakage will increase as V T decreases to maintain noise margins and meet frequency demands, leading to excessive battery draining standby power consumption. 50% 40% 1.7KW 8KW and phones leaky! Standby Power 30% 20% 10% 12W 88W 400W 0% Source: Borkar, De Intel UCSD Talk Feb # 94

95 Multimedia Controller SoC Example Communication between s significantly affects system performance and power! UCSD Talk Feb # 95

96 Communication Architectures NOC based Bus based UCSD Talk Feb # 96

97 CCATB Transaction Example Arbiter + Decoder channel_status_slave * read (SDRAM_ADDR_TYPE addr_in, slave_data_and_control * packet) { switch (addr_in - m_start_address) { case SDRAM_CONTR_MODE: *(packet->data) = m_mode; slave_status->status = BUS_OK; slave_status->wait_cyc = 4; return slave_status; break; case SDRAM_CONTR_RESET: System BUS SDRAM Controller Reset Controller process lcdc() { if (enable.read() == 1) { read(port, SDRAM_addr1, token); wait(wait_period); size_info = token->data; } } ISS + esw LCD Controller MEM1 DMA UCSD Talk Feb # 97

98 Modeling Abstractions for CA Exploration Increasing simulation speed Increasing simulation accuracy master v1 = a + b; wait(1); //cycle 1 REG = d << v1; wait(1); //cycle 2 REQ.set(1); ADDR.set(REG); WDATA.set(v1); wait(1); //cycle 3 master v1 = a + b; REG = d << v1; REQ.set(1); ADDR.set(REG); WDATA.set(v1); wait(3); //3 cycles master v1 = a + b; REG = d << v1; addr = REG; REQ.set(1); write(addr,v1); wait(3); //3 cycles bus arb signal interface bus arb slave Cycle Accurate (CA) slave signal interface case CTR_WR: CTR_WR = in; wait(1); //cycle 1 CTR_WR2 =0xf; wait(1); //cycle 2 HRESP.set(1); HREADY.set(0); case CTR_WR: CTR_WR = in; CTR_WR2 =0xf; wait(2); //2 cycles HRESP.set(1); HREADY.set(0); Pin Accurate Bus Cycle Accurate (PA-BCA) slave bus arb signal, transaction interface case CTR_WR: CTR_WR = in; CTR_WR2 =0xf; wait(2); //2 cycles bus_resp(ok); HREADY.set(0); Transaction based Bus Cycle Accurate (T-BCA) master slave Simulation speed: ~10-100x RTL Modeling effort: /1 - /3 RTL Simulation speed: ~ x RTL Modeling effort: /5 - /10 RTL Simulation speed: ~1000x RTL Modeling effort: ~/10 RTL v1 = a + b; bus case CTR_WR: REG = d << v1; CTR_WR = in; addr = REG; arb CTR_WR2 =0xf; write(addr,v1); chan_resp(ok); wait(); transaction interface Transaction level Model (TLM) Simulation speed: >>1000x RTL Modeling effort: ~/20 RTL UCSD Talk Feb # 98