FPGA Implementation of Space-Based Lossless and Lossy Multispectral and Hyperspectral Image Compression

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Implementation of Space-Based Lossless and Lossy Multispectral and Hyperspectral Image Compression Didier Keymeulen, Huy Luong, Thang Pham, Hamid Ghossemi, Simon Shin, Aaron Kiely, Matthew Klimesh,

1 Implementation of Space-Based Lossless and Lossy Multispectral and Hyperspectral Image Compression Didier Keymeulen, Huy Luong, Thang Pham, Hamid Ghossemi, Simon Shin, Aaron Kiely, Matthew Klimesh, Michael Cheng, 1 David Dolman, 1 Chris Holyoake, 1 Ken Crocker, Charles Sarture, Michael Eastwood, Robert Green, Ian Mccubbin Jet Propulsion Laboratory, California Institute of Technology 1 Alpha Data Inc. The research described in this presentation was carried out at the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration

Fast Lossless (FL) MSI/HSI Compressor FL Compressor Overview Predictor predicted sample values Entropy Coder compressed data MSI/HSI image Approach: Predictive

right) Adaptively adjusts prediction weights for each spectral band via adaptive linear prediction Entropy Coder Losslessly encodes the difference between predicted

2 Fast Lossless (FL) MSI/HSI Compressor FL Compressor Overview Predictor predicted sample values Entropy Coder compressed data MSI/HSI image Approach: Predictive compression, encoding samples one-at-a-time Predictor Computes predicted sample value from previously encoded nearby samples (prediction neighborhood illustrated at right) Adaptively adjusts prediction weights for each spectral band via adaptive linear prediction Entropy Coder Losslessly encodes the difference between predicted and actual sample values Adaptively adjusts to changing prediction accuracy previous three bands current spectral band current sample 3D neighborhood used for prediction. 2!

FL : PRISM & AVIRISng Real-time aircraft onboard compression

Compresses one sample every clock cycle, a speed of 40 MSample/sec.

Virtex-6 LX240T two 256MBytes DRAMs (32bit data word, 3.

PRISM and AVIRISng HSI image data transferred in real-time

link board, compressed on the Virtex-6 and transferred through PCIe to

3 FL : PRISM & AVIRISng Real-time aircraft onboard compression Implemented pushbroom FL compressor on a COTS Virtex 6. Compresses one sample every clock cycle, a speed of 40 MSample/sec. Implementation tested via Alpha-Data ADPE-XRC-6T which includes Xilinx Virtex-6 LX240T two 256MBytes DRAMs (32bit data word, 3.2GBytes/sec per bank) PCIe x4 Gen2 (500MBytes/sec per lane). PRISM and AVIRISng HSI image data transferred in real-time (60MBytes/sec) to the Virtex-6 via Alpha-Data FMC-CLINK-MINI camera link board, compressed on the Virtex-6 and transferred through PCIe to a 1GBytes SSD drive configured as RAID0 (500MBytes/sec) ADPE-XRC-6T/LX240T-3 FMC-CLINK-MINI PRISM HSI PRISM HSI Support Equipment 3!

4 FL Architecture Alpha-Data ADPE-XRC-6T Camera Link interface Camera Link Interface Virtex6-LX240T-3 Alpha-data FMC-CLINK CameraLink 640by285,165Hz,60MB/s BIL; 16 bits/sample IMU/GPS Resync Pass through acquisition BIL to BIP Formatting Control & Status Hyperspectral source Custom App (JPL) FL Compression Hyperspectral sink Host Software Drivers Camera Link & OCP interface Compression Xeon CPU RAM SSD 1 TB 0.5GB/s (raw Compressed) PCIe Gen2 X4 0.5GB/s PCIe Interface & Target Wrap DMA Bank#2 transfer DMA Bank#1 transfer transpose OCP Interface Mux SDRAM #1 DDR bank #1 SDRAM 512MBytes 32bits; 3.2 GB/sec OCP Interface Mux SDRAM #2 DDR bank#2 SDRAM 512MBytes 32bits; 3.2GB/sec 4!

5 FL Resource Utilization Virtex6 Device Utilization Virtex6-LX240T-3 (Compressor and Interface) Available Used Utilization All Utilization Compressor Slice Register (Flip-Flop) 301,440 37,284 12% 4% 8% Slice Look-up-table (LUTs) 150,720 37,374 24% 8% 8% Fully used LUT-Flip Flop pairs 50,693 19,105 38% 13% 26% Block RAM/FIFO % 12% 12% DSP 48eS % 1% 1% Device Utilization SDRAM (AVIRISng) Available Used Utilization SDRAM Bank#1 (2 segments) 256 MBytes 40 MBytes 20 % SDRAM Bank#2 (3 segments) 256 MBytes 60 MBytes 24 % Block Synchronization frames with IMU/GPS Transpose BIP to BIL Predictor Entropy Encoder Packer Timing: Critical Path Critical Path Timing <25ns <10ns ns ns ns Utilization Virtex5 Compressor (estimated) The implementation compresses one sample every clock cycle, which results in a speed of 40 MSample/sec 5!

Fast Lossless Extended (FLEX): lossless & nearlossless hyperspectral image compression sample prediction value error y(n) e(n) l(n) y ˆ (n) predicted sample value Q

Residuals through an Entropy Coder: The better the predictor, the lower the entropy of the prediction residuals.

6 Fast Lossless Extended (FLEX): lossless & nearlossless hyperspectral image compression sample prediction value error y(n) e(n) l(n) y ˆ (n) predicted sample value Q quantization Q -1 ˆ e (n) Entropy Coder compressed data Predictor Z -1 ˆ y (n) FLEX Compressor Block Diagram FLEX compresses data by passing Quantized Prediction Residuals through an Entropy Coder: The better the predictor, the lower the entropy of the prediction residuals. The quantizer allows further lowering of this entropy at a cost of inexact reconstruction from the compressed data (lossy compression). The entropy coder losslessly encodes quantized prediction residuals, producing compressed bits 6!

Host SSD (1 TB 0.3GB/s) (raw/ compressed) RAID0 RAM Drivers Software: Compute statistics Convert to integer format Convert to BIP Xeon CPU PCIe Gen2 X4 1.

15 GB/sec FLEX framework provides a platform to integrate FLEX Intellectual Property (IP) core with Peripheral Component Interconnect Express (PCIe) and synchronous

CameraLink simulator is used for testing FLEX IP core independent of the software FLEX Platform Block Diagram Alpha-Data ADM-XRC-7V1/VX690T-3 on ADC-PCIe-XMC carrier

image_memif (0) adb3_ocp_mux_n b (Bank1) DDR3 bank #1 SDRAM 1GBytes 32bits; 6.

7 Host SSD (1 TB 0.3GB/s) (raw/ compressed) RAID0 RAM Drivers Software: Compute statistics Convert to integer format Convert to BIP Xeon CPU PCIe Gen2 X4 1.5 GB/sec Camera Link Simulator 0.15 GB/sec FLEX framework provides a platform to integrate FLEX Intellectual Property (IP) core with Peripheral Component Interconnect Express (PCIe) and synchronous dynamic random access memory (SDRAM) FLEX Software and are integrated into Alpha Data framework providing PCIe and SDRAM interface compatible with other HW platforms CameraLink simulator is used for testing FLEX IP core independent of the software FLEX Platform Block Diagram Alpha-Data ADM-XRC-7V1/VX690T-3 on ADC-PCIe-XMC carrier board Virtex7/VX690T-3 mptl mptl_sb clink_in clink_out mptl_bridge_if clink_adb3 (for test only) (1) registers_clink camera_link_ocp_interf ace (for test only) image_memif (0) adb3_ocp_mux_n b (Bank1) DDR3 bank #1 SDRAM 1GBytes 32bits; 6.4GB/sec adb3_ocp_l_splite q adb3_ocp_l_splite q direct_slave_r32 adb3_ocp_mux_n b (Bank2) dma_channels clink_custom_app (for test only) blk_mem_if DDR3 bank #2 SDRAM 1GBytes 32bits; 6.4GB/sec blk_clocks ocp_registers (1) (0) cam_data_custom cam_data (2) (3) adb3_ocp_mux_n b (Bank3) ocp_interupt_contro ller compression_memif (0) (1) (2) (3) (0) (1) (2) (3) adb3_ocp_mux_n b (Bank4) (0) (1) ram_if (2) (3) mem_add_out; mem_ctrl_out; mem_data_inout DDR3 bank #3 SDRAM 1GBytes 32bits; 6.4GB/sec Compression/Memory PCIe DMA PCIe Register and IRQ Camera FLEX core Memory PCIe Blocks CameraLink Addr_split_ eqint_collec adb3_ocp_me gamux t Stub FLEX IP Core#15 (FLEX compressor Stub ) FLEX IP Core#1 (FLEX compressor ) DDR3 bank #4 SDRAM 1GBytes 32bits; 6.4GB/sec 7!

8 -Software Overview FLEX Application Software decomposes HSI image into a set of segments (between 32 and 64 lines each) which are passed on to the FLEX hardware API layer through a C interface. FLEX hardware API handles configuration and interaction with card The scheduler queues the segments from the application as a set of jobs to be executed on the available FLEX IP cores in the. The scheduler manages a set of workers (proportional to the number of cores in the design). Each worker is assigned a core to use in the. The scheduler assigns the idle worker a segment in the queue to compress on the. The worker handles the data transfer to the, triggering a FLEX core to execute, and acquiring compressed data back from the. FLEX design compresses in parallel up to 15 segments at a time. Each FLEX IP core: Works independently on the data assigned by the FLEX worker. This data is stored in the SDRAM banks directly attached to the. Uploads and downloads intermediary data to/from its own SDRAM partition. Downloads compressed data in SDRAM and alerts its FLEX worker that the job is done. Software FLEX Application Software FLEX API C/C++ OS/Host Drivers Hardware + Memory + PCIe Bridge Input Raw Image (Solid State Drive) JPL FLEX Console or FLEX V1 Application Output Compressed Data (Solid State Drive) Scheduler (Manages queue of segments) FLEX worker 0 FLEX worker 1... FLEX worker 29 Interface Abstraction (API, Drivers, PCIe bridge, DMA engines) SDRAM SDRAM design (with 15 FLEX cores) SDRAM SDRAM 8!

FLEX Timing Compress 147 MSamples (Integer Image) in < 10 sec

(40 MBytes/segment), 15 segments Computes Statistics of full image on

compress and download 15 segments from SDRAM to host computer 118ms

Action Actions Data Transfer Host Reads BIP Image from Hard Drive SW

TO 2384ms = 16x 149 ms Compress 8ms 8m s DMA TO HOST Compress 8m s DMA

9 FLEX Timing Compress 147 MSamples (Integer Image) in < 10 sec Assumptions: 32 frames/segment, 480x640 samples/frame, 32bits/sample (40 MBytes/segment), 15 segments Computes Statistics of full image on host computer in 54ms Upload 15 segments from host Memory to SDRAM, compress and download 15 segments from SDRAM to host computer 118ms 2271ms 217 ms 54 ms 1806 ms ms ms 103m s 1277ms 17ms Software Action Actions Data Transfer Host Reads BIP Image from Hard Drive SW Compute Statistics DMA TO 28ms DMA TO Compress 149 ms DMA TO HOST DMA TO 2384ms = 16x 149 ms Compress 8ms 8m s DMA TO HOST Compress 8m s DMA TO HOST SZvault Host Writes Compressed File to HDD Actions 8ms 8ms 8ms SW HEADE R SW HEADE R 9!

FLEX Performance 15-Cores Execution time of the FLEX Platform IP 15-cores for 147 MSamples: (1) the Data flow is limited by PCIe interface used for HOST-SDRAM data transfer during the upload of the

6GHz Xeon processors using 10 times less power Actions of each of the 15 cores on the DMA Transfer between CPU and DDR Data Transfer > PCIe Gen2 x4 data bandwidth of 1,400 Mbytes/sec DDR transfer

10 FLEX Performance 15-Cores Execution time of the FLEX Platform IP 15-cores for 147 MSamples: (1) the Data flow is limited by PCIe interface used for HOST-SDRAM data transfer during the upload of the uncompressed data; (2) implementation use only 13% of the SDRAM data bandwidth; (3) is 41% faster than SW on 8 cores 3.6GHz Xeon processors using 10 times less power Actions of each of the 15 cores on the DMA Transfer between CPU and DDR Data Transfer > PCIe Gen2 x4 data bandwidth of 1,400 Mbytes/sec DDR transfer during upload/download and compression Data Transfer << DDR data bandwidth of 18,000 Mbytes/sec Data Compression Rate & Power : Compression Engine: 81.5 MSamples/sec TOTAL (HDD+Statistics+SZvault+): 64 MSamples/sec Power: Watt Data Compression Rate & Power SW SW Compression Engine: MSamples/sec TOTAL (HDD+Statistics+SZvault+SW): 50 MSamples/sec Power: 130 Watt 10!

FLEX performance 15-Cores with Large Image Compression of 521 MSamples: (1) pipeline of

SW; (2) memory rotation distributes the DDR memory load reducing memory latency; (3)

5 GBytes/sec) has no effect on the data rate (pipeline data compression & data transfer);

and DDR Data Transfer > PCIe Gen2 x4 data bandwidth of 1,400 Mbytes/sec Actions cores DDR

11 FLEX performance 15-Cores with Large Image Compression of 521 MSamples: (1) pipeline of compression and upload/download increases data rate to 95 MSamples/sec or 64% faster than SW; (2) memory rotation distributes the DDR memory load reducing memory latency; (3) limited PCIe data bandwidth (1.5 GBytes/sec) has no effect on the data rate (pipeline data compression & data transfer); (4) the HOST processors can do real-time acquisition while simultaneously performs real-time data compression. HOST CPU Cores Actions SSD read Compress & CPUs sleep SSD write DMA transfer between CPU and DDR Data Transfer > PCIe Gen2 x4 data bandwidth of 1,400 Mbytes/sec Actions cores DDR transfer during upload/download and compression Data Transfer << DDR data bandwidth of 18,000 Mbytes/sec Data Compression Rate - : Compression Engine: 95 MSamples/sec Total (HDD+Statistics+SZvault+): 73 MSamples/sec 11!

Eliminates the effect of limited PCIe data bandwidth 2.

12 FLEX Performance 15-core Summary Advantages of the FLEX implementation : 1. Pipelining data download/upload with data compression a. Data rate increases linearly with the number of cores (no memory bottleneck) b. Data rate increases more for large image c. Eliminates the effect of limited PCIe data bandwidth 2. Can provide up to a 106 MSamples/sec compression data rate in real-time data streaming. Data rate is limited only by predictor module which uses 26 Clks/sample at 200 MHz 3. Dedicated processor can relieve main CPU to run other essential tasks. 12!

13 Hardware Implementation FLEX Virtex7-XC7VX690T Resource utilization, 1 and 15 cores The Table provides the resource utilization of the Virtex-7 for 3 design configurations: The arithmetic for 1-core implements a single data compression core writing and reading uncompressed and compressed data on SDRAM/DDR memory and interacting with the software through Register and Interrupt controllers. The full design for 1-core implements the arithmetic for 1-core and the glue logic needed to communicate with the Software through the Peripheral Component Interconnect Express (PCIe) The full design for 15 cores implements 15 arithmetic for 1-core and the glue logic needed to communicate with the Software to write/read uncompressed and compressed data of 15 cores simultaneously to/from DDR/SDRAM memory. Available Used, Arithmetic for 1-core Used, Arithmetic for 1-core (Percent) Used, Full Design for 1 core Used, Full Design for 1 core (Percent) Used, Full Design for 15 cores Used, Full Design for 15 cores (Percent) Slice Registers (Flip- Flop) Slice LUT 866, ,200 Slice LUT as Memory (1 LUT is 62 bits) 174, Mbytes Block RAM Tile (36kBit each) Mbytes DSP Worst Case Timing Slack 9,158 13, N/A 1.05% 3.03% 0.20% 2.41% 0.86% 82,056 73,514 19, Kbytes Kbytes 9.47% 16.96% 11.00% 4.04% 0.86% 260, ,807 52, Kbytes Mbytes 30.09% 68.74% 30.02% 37.85% 12.91% Power N/A ns 7.84W ns 11.40W 13!

14 Infusion of FLEX to ECOSTRESS: Data Compression Architecture and Block diagram LVDS Uncompressed Segment BIP 197 kbytes 135 Mbits/sec Max per SSD Spec Header Compressed Segment 1kBytes I/O DPU compressed Segment 79 kbytes Mass Storage Unit (256Gbytes) Working Memory for Up Loading Next Segments 1.58 MBytes Uncompressed Frame BIP (3 kbytes) Working Memory for Compressing Segment 1.58 MBytes 4x512 MB SDRAM 266 Mbits/sec required by compression for Max Data Compression Speed ECOSTRESS Memory Controller Virtex 5 (FX130T, Clk 50MHz) Register Controller Interrupt Controller Converter BIL to BIP IP Specifications: 1 frame = 256 cross-track, 6 spectra FLEX_2_0_1 Lossless 1 core IP Specifications: 1 segment = 256 cross-track, 6 spectra, 64 frames FLEX used 32bits sample bit-width 786 kbytes uncompressed 315 kbytes compressed Data compression rate: 33Mbits/sec Inputs: Uncompressed data 32bits extended Initialization data Constants (N_x, N_y, N_z, ) Compress Reset Compress Start Outputs: Compressed data 32-bits aligned Compress End Compress Size FLEX Controller IP Segment Header IP Specifications: 1 header per segment 1kBytes Content: Compressed size Segment number Frame number Time Stamp Camera Mode 14!

15 FLEX Virtex5 used on ECOSTESS: Resource Utilization for Implementation of FLEX 1 core and Entropy Coder stand-alone Resource utilization for FLEX on Virtex5FX130TFF1738, Speed: -1 for full FLEX single core design and entropy coder same resource as Virtex5Q-FX130 (Rad-Hard Space-Qualified) Resource Available Entropy Coder Used Entropy Coder % Complete FLEX used Complete FLEX % DSP48Es % 40 13% Slices % % Slice Registers % % Slice LUTs % % Slice LUT-FF pairs % % RAM/FIFO 18Kb % 16 5% RAM/FIFO 36Kb % 27 9% Entropy Encoder Stand-Alone: Maximum clock frequency MHz Data Throughput (7Clks/Samples): 24 Msamples/sec Estimated total power FLEX single-core (including entropy coder): Maximum clock frequency 82.5 MHz Data Throughput (24Clks/samples): 3.4 Msamples/sec Estimated total power 15!

16 Summary We presented an implementation of the adaptive Fast Lossless (FL) hyperspectral data compression algorithm and flight demonstration. The implementation targets the Xilinx Virtex 6 s and provides a data throughput of 40MSamples/sec using a single core, making the use of this compressor practical for satellites and planet orbiting missions with hyperspectral instruments. We presented a SW/ implementations of the FL EXtended (FLEX) compressor lossy & lossless compressor to increase compression ratio needed for large Focal Plane Array (FPA). Implementations target the Xilinx Virtex 7, space qualified Virtex 5 s as well as System-on- Chip (SoC) to embed the compression next to the FPA Readout Integrated Circuit (ROIC). It can accommodate raw, radiance and reflectance data. Future development will explore new hardware technologies such as Multiple Processor System-on-the-Chip (MPSoC); Zynq Z7045Q including Kintex-7 and dual-core ARM Cortex-A9 Processors with embedded pre-processing including real-time cloud screening. 16!

17 References 1. A. Kiely, M. Klimesh, A New Entropy Coding Technique for Data Compression, IPN Progress Report, vol , pp. 1 48, M. Klimesh, Low-complexity lossless compression of hyperspectral imagery via adaptive filtering, IPN Progress Report, vol , pp. 1 10, Nov. 15, [Online]. Available: 3. M. Klimesh, Low-complexity adaptive lossless compression of hyperspectral imagery, Proc. SPIE, vol. 6300, pp N N-9, Sep N. Aranki, D. Keymeulen, M. Klimesh, A. Bakhshi, Fast and Adaptive Lossless On-Board Hyperspectral Data Compression System for Space Applications, 2009 IEEE Aerospace Conference, 8 pages, March 7-14, 2009, Big Sky, MT, USA. 5. N. Aranki, D. Keymeulen, M. Klimesh, A. Bakhshi, Hardware Implementation of Lossless Adaptive and Scalable Hyperspectral Data Compression for Space, NASA/ESA Conference on Adaptive Hardware and Systems, pp , July, 2009, San Francisco, CA, USA. 6. M. Klimesh, A. Kiely, P. Yeh, Fast Lossless Compression of Multispectral and Hyperspectral Imagery, Proc. International Workshop on On-Board Payload Data Compression (OBPDC), 8 pages, Toulouse, France, Oct , Lossless Multispectral & Hyperspectral Image Compression. Recommendation for Space Data System Standards, CCSDS B-1. Blue Book. Issue 1. Washington, D.C.: CCSDS, May 2012 [Online] ( ) 8. A. Bakhshi, J. Kang, N. Aranki, D. Keymeulen, M. Klimesh, A. Kiely Ecosystem Whitepaper: Implementation of Fast Lossless Hyperspectral Data Compression on Virtex-5 s, Xilinx on-line January Newsletter D. Keymeulen, N. Aranki, A. Bakhshi, H. Luong, C. Sartures, D. Dolman, Airborne Demonstration of implementation of Fast Lossless Hyperspectral Data Compression System, NASA/ESA Conference on Adaptive Hardware and Systems, July, 2014, Leicester, UK 10. Didier Keymeulen, Huy Luong, Nazeeh Aranki, Charles Sarture, Michael Eastwood, Ian Mccubbin, Alan Mazer, Matt Klimesh, Robert Green, David Dolman, Alireza Bakhshi, Real-time Airborne Demonstration of Fast Lossless Hyperspectral Data Compression System for AVIRIS-NG and PRISM, Proceedings of 2014 HyspIRI Science and Applications Workshop, October 2014, California Institute of Technology, Pasadena, CA [Online] ( ) 11. Lossless Multispectral & Hyperspectral Image Compression. Report Concerning Space Data System Standards, CCSDS G-1. Green Book. Issue 1. Washington, D.C.: CCSDS, December 2015 [Online] ( ) 17!

FPGA Provides Speedy Data Compression for Hyperspectral Imagery

FPGA Provides Speedy Data Compression for Hyperspectral Imagery Engineers implement the Fast Lossless compression algorithm on a Virtex-5 FPGA; this implementation provides the ability to keep up with