HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips

Transcription

1 on introducing a new design paradigm HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips D. Diamantopoulos, K. Siozios, E. Sotiriou-Xanthopoulos, G. Economakos and D. Soudris School of Electrical and Computer Engineering National Technical University of Athens, Greece {diamantd, ksiop, stasot, geconom, dsoudris}@microlab.ntua.gr

2 Presentation Outline Introduction Motivation Proposed methodology for supporting HVSoC Experimental results Conclusions & Questions

3 System Design Is today s SoC technology enough for future IC industry? Conventional System-on-Chip Good time-to-market But is it OK for: Development before the availability of physical prototype? Simulation of advanced SoC designs? Heterogeneous systems co-simulation? Modular verification? Higher functionality per mm 2?... under time-to-market pressure

4 Motivation (1/2) high-level exploration and optimization Computer Vision algorithms (C/ C++/ VHDL) Profiling Behavioral optimization Partitioning Step1 Step2 Step3 Step4 Modules to be implemented on coarse-grain hardware HDL implementation Modules to be implemented on fine-grain hardware Modules to be implemented on CPU Software implementation Step5 Tools for mapping on FPGA platform Tools for mapping on CPU Xilinx EDK System integration Back end tools Step6 Configuration & Run-time Step7

5 Motivation (2/2) Hardware

6 Motivation (2/2) Hardware

7 3D integration: What, Why, When Impact of process technology to delay As submicron technology shrinks, RC interconnection delay dominates. Interconnection Delay 2:1 9:1 Gate delay Source: ITRS - Interconnect

8 More than Moore age is coming Battery MEMS DNA Chip Image Sensor RF Chip Processor Memory Highly intergraded systems might be fabricated at various technologies! 3-D results to reduced interconnection delay and higher functionality per space!

9 3-D Integration: It is already here

10 Short, medium and long term path to 3D-IC Cadence states that Packaging has become sexy! Cadence has already released Encounter Digital Implementation System (EDI).

11 Our Contribution Physical design flow implementation including Rapid Virtual System Prototyping (Topdown SoC design). 3D HVSoC Implementation of demonstrators for 3D SoCs. 3D-Pathfinding (Partitioning, Floorplan, Global Routing) for SoC Evaluation.

12 3D HVSoC: A new design concept Virtual prototyping: accelerates pre-rtl embedded software development, HW/SW integration, and system validation. helps starting multi-core SoC prototyping earlier. improves software debug visibility. Compatible with the simulated target hardware, allowing the development of software that can run unmodified on the equivalent hardware platform. SW Challenges Growing software content requires more and better testing throughout the development cycles Virtual Prototyping Virtual Prototyping provides a powerful solution for SW development. system integration, test and verification HW Challenges High complexity of hardware systems requires extended design & verification time which leads to high time-to-market. Connects to the real world using the physical interface hardware of the host PC (i.e. Ethernet), allowing the device drivers and application testing with real-world stimuli. HWdependent SW Development SWdependent HW

13 Proposed Methodology System Modeling Proposed Rapid Virtual Prototyping System Integration ASIC All-Software solution (e.g. ROS, UML, OpenCV...) FPGA RTL Technology Libraries Timing Constraints μp SystemC-TLM SystemC peripherals μp Target System Design Constraints e.g. Profiling (e.g. Valgrind, Vtune) Hardware-dependent software (e.g. Software running on ARM) Conventional Prototyping 3D System Integration Evaluation Analysis Area-Power-Delay Evaluation Co-Debugging RUN-TIME! Phase B2: 3-D ASIC Physical Implementation HW/SW Partitioning Proposed Hybrid Prototyping 1 st step 2 nd step 3 rd step Pre-processing 3-D Stack 3-D System Step Generation Prototyping Control-flow software (e.g. Software running on x86 host) HotTalk API (Device driver, SW stack) 3-D stacking Design Constraints 3D Design Strategy P&R Options FPGA-in-the-loop Early Prototyping Custom HW IPs (e.g. Application running on FPGA) System Modeling (e.g. SystemC) High-level Synthesis (e.g. Cadence C-to-Silicon, Xilinx Vivado) Virtual Library RTL-Library TLM-SystemC Interconnection Bus TLM-SystemC models Technology Library Virtual 3D OpenRISC PLUG & CHIP 3-D System Pareto Solutions

14 The proposed methodology in detail: PHASE A: Virtual Prototyping PHASE B: Design of 3-D Architectures

15 Phase A: Virtual Prototyping Phase A: HVSoC Prototyping TLM-SystemC Interconnection Bus TLM-SystemC models Virtual Library High-level System Modeling New functionality is developed in SystemC I/O with SoC using TLM sockets Configurable SystemC/TLM Case study: Processor Leon3 (TRAP Gen POLIMI : Generation of SystemC and TLM based Instruction Set Simulators (ISS)) RTL-Simulation New IP is developed in SystemC HDL-level System Modeling Embedded Processors IP Reuse Silicon proven functionality RTL-Library RTL Interconnection Bus RTL-SoC Configurable RTL Leon3 (VHDL) Communication with SoC s bus using TLM sockets Easy integration of desired functionlity on top of AMBA protocol

16 Phase A: Virtual Prototyping Phase A: HVSoC Prototyping TLM-SystemC Interconnection Bus TLM-SystemC models Virtual Library High-level System Modeling High-level Synthesis (Cadence C-to-Silicon) Co-Simulation (Cadence Incisive) HVSoC-RTL HDL-level System Modeling Gate Synthesis (Cadence Encounter RTL Compiler) RTL-Library RTL Interconnection Bus RTL-SoC Co-simulation of transaction (SystemC) and RTL level (VHDL) on Cadence Incisive Simulator. Transaction Level Analysis capabilities put on top of SystemC. SystemC Abstract domain <-> VHDL Signal Domain Generates pipelined data path and control logic Considers real timing constraints during RTL generation Explores implementation tradeoffs

17 Phase A: Virtual Prototyping Phase A: HVSoC Prototyping TLM-SystemC Interconnection Bus TLM-SystemC models Virtual Library High-level System Modeling High-level Synthesis (Cadence C-to-Silicon) Co-Simulation (Cadence Incisive) HVSoC-RTL HDL-level System Modeling Gate Synthesis (Cadence Encounter RTL Compiler) RTL-Library RTL Interconnection Bus RTL-SoC Top-down NEW IP implementation NEW IP (SystemC) High-level Synthesis (Cadence C-to-Silicon) NEW IP (VHDL) AHB TVM AHB RTL LEON3 Processor based SoC 7-Stage Integer Unit AHB Interface AHB Controller Register File (256B) AMBA AHB (High-Speed Bus) 8/32-bits memory bus Memory Controller Control Core Instruction-Cache (4KB) Data-Cache (4KB) AHB/APB Bridge UART (1KB) RS232 Debug Serial Unit (1KB) AMBA APB (Peripheral Bus) Timers IrqCtrl I/O port PROM VHDL SystemC I/O SDRAM RS232 WDOG 16-bit I/O port

18 The proposed methodology in detail: PHASE A: Virtual Prototyping PHASE B: Design of 3-D Architectures

19 Total Wirelength 2D Design Parameters Phase B: Design of 3-D Architectures 1. 2D System Prototyping 2. 3D Stack Generation 3. 3D System Prototyping HDL SoC Design (LEON3) Technology Libraries Timing constraints Placement, Routing Policies Functional Simulation Gate-Level Synthesis Floorplan - Placement Global/Detail Routing System Partitioning Partitioning to Layer Layer Ordering Floorplan Placement (TSVs, macro blocks) Global Routing 3D Design Parameters TSV s Library Interconnection Options 3D Design Strategy 4. Evaluation Analysis Area-Power-Delay Evaluation No Performance Degradation Power Consumtion 5. Overall Pareto Configurations

20 2D Design Parameters Phase B: 2-D System Prototyping Technology Libraries Timing constraints Placement, Routing Policies 1. 2D System Prototyping HDL SoC Design (LEON3) Functional Simulation Gate-Level Synthesis Floorplan - Placement Global/Detail Routing This task includes the EDA tools for conventional 2-D physical prototyping Simulation with Cadence Incisive Simulator Synthesis with Synopsys Design Compiler Physical synthesis with Cadence SOC Encounter Post-layout Sim. with Cadence Incisive Simulator Power Analysis with Synopsys Primetime PX From this step we extract the functional integrity for the SoC design along with metrics: size of components activity per component power profile

21 Phase B: 3-D Stack Generation The application's components have to be assigned at architecture layers, under specific design constraints Application Graph Application Functions Communication between Logic Functions 3DPart [1] Cost_function (edgecut,area,balance) Number of layers Interlayer connections Power/delay constraints 2. 3-D Stack Generation edgecut=74 System Partitioning Partitioning to Layer Layer Ordering 3-D Stack Graph (2 layers) By appropriately controlling the weighting factors, the resulting partitioning can be optimized either to minimize the number of inter-die connections, the area balance and power variation edgecut=206 edgecut= Application Functions Communication between Logic Functions Inter-die Connections 3-D Stack Graph (4 layers) Derived Constrained Solutions [1] K. Siozios and D. Soudris, A Tabu-based Partitioning Algorithm for Application Mapping onto 3-D FPGAs, IEEE Embedded Systems Letters, Vol. 3, No. 3, September edgecut=39

22 Phase B: 3-D System Prototyping [1] Application Graph Platform Graph Optimal 3-D Stack Graph Application Functions Communication between Logic Functions Architecture Elements Communication path between HW elements Appropriate Input from previous steps Application Functions Communication between Logic Functions Inter-die Connections D System Prototyping Floorplan Placement (TSVs, macro blocks) Global Routing 3D Design Parameters TSV s Library Interconnection Options 3D Design Strategy 3DSystem Prototyping Layer 1 Assign TSVs to interconnection buses Floorplan this layer Conventional LEON3 Physical layout 3-D LEON3 (2 tiers) Then, the IPs assigned to each layer are P&R and a number of parameters related to interconnection network are retrieved. Layer 2 Place Macro blocks + TSVs (this layer) Route (this layer) Propagate Constraints (other layers) [1] K. Siozios, et al., "A method and tool for early design/technology search-space exploration for 3D ICs", VLSI-SoC, 2008.

23 Phase B: 3-D System Prototyping (proposed) Application Graph Platform Graph Optimal 3-D Stack Graph Application Functions Communication between Logic Functions Architecture Elements Communication path between HW elements Appropriate Input from previous steps Application Functions Communication between Logic Functions Inter-die Connections Uniform Layer (Virtual Layer + TSV nets) D System Prototyping Floorplan Placement (TSVs, macro blocks) Global Routing 3D Design Parameters TSV s Library Interconnection Options 3D Design Strategy 3DSystem Prototyping Assign TSVs to interconnection buses Floorplan Virtual layer Conventional LEON3 Physical layout 3-D LEON3 (Virtual tier) Place Macro blocks + TSV Nets Then, all the IPs are P&R simultaneously and a number of parameters related to interconnection network are retrieved. Route Virtual layer Propagate Constraints (other layers) [1] D. Diamantopoulos, et. al., A Framework for Performing Rapid Evaluation of 3-D SoCs, IET Electronics Letters, pp , June 2012.

24 Phase B: 3-D System Prototyping (Virtual Layers TSV Nets) Uniform Layer (Virtual Layer + TSV nets) Layer-1 Nets New 4-direction Vias Layer-2 Nets New Via Rules Fill New Stack Layer-N Nets 3-D LEON3 (Virtual tier) New Via Rules for Via DB-LIB DB-LEF TSV Nets New Metal Layers Virtual TSV Layer-2 Layer-N Virtual TSV Layer-1 Layer-2 New Segment Spacing Tables New Via array genegarion The virtual layers are generated by replicating the technology metal layers. TSV s are represented as special (extra) metal layers with fixed RLC values. For each virtual layer and TSV, almost 34 extra text fields are added to physical library files.

25 Phase B: Evaluation Analysis Uniform Layer (Virtual Layer + TSV nets) Power consumption for logic blocks in 2-D and 3-D system implementation are exactly the same. Power consumption at TSVs differs, since it is tightly firmed to the final P&R of the 3-D system Physical Hypergraph Netlist2Graph DBAccess + TCL + C 3-D LEON3 (Virtual tier) 4. Evaluation Analysis Area-Power-Delay Evaluation Design Basic Blocks TSVs Block Physical Net Buses 3-D IC Metrics P A D ower (mw) rea (mm^2) elay (ns) PowerCalc PrimetimePX + Ncsim + C + TCL + Bash Basic-Block s Power Profile by 2-D System Prototyping Delay, Capacitance by 3-D System Prototyping Evaluation with both commercial and new academic tools

26 Test Case: The SPARTAN/SEXTANT Systems

27 Case Study: SPARTAN System SPARTAN system organized as a combination of algorithms implemented in a FPGA plus a central processing component acting as an interface to rover sensors. Stereo-vision images are the main source of data to feed the SPARTAN system Central processor built on top of ROS (Robot Operating System) SPARTAN Architecture SPARTAN Sensors Vision Stereo System Imaging 3D Map reconstruct. Visual Odometry Map Merging IMU Acc + Gyros Visual SLAM Path Planning Mechanical Odometer Proximity Sensors Localisation GNC Guidance - Navigation Control

28 SPARTAN System: Visual Odometry The Visual Odometry component computes the pose of the rover based on the estimated displacement between two consecutive instants of time. 1 Landmark Detection The landmark detection module comprises the features extraction methodology from an image Landmark 3D Reconstruction The 2D features extracted from the images transformed into 3D coordinates Landmark Matching The matched features are used for the estimation of the instantaneous rotation angle of the robot The two centers of the matched features in the two successive images are computed.

29 Evaluation Results: Case study LEON3 We designed a low-power 3-D instantiation of LEON3 RISC8 processor with 2 layers Technology : UMC 0.13μm (both layers) Control Core LEON3 Processor Timing constraint: 4.25ns (230MHz) Total std. cells: Custom Memory Models (no-distributed logic) RS232 7-Stage Integer Unit AHB Interface Register File (256B) Instruction-Cache (4KB) Data-Cache (4KB) Debug Serial Unit (1KB) AMBA AHB (High-Speed Bus) AHB Controller Memory Controller AHB/APB Bridge UART (1KB) AMBA APB (Peripheral Bus) Timers IrqCtrl I/O port 8/32-bits memory bus PROM I/O SDRAM RS232 WDOG 16-bit I/O port Layer 1 Layer 2 External blocks

30 Brainstorming on SoC Encounter 3d-hacking

31 Brainstorming on SoC Encounter 3d-hacking

32 Evaluation Results: Power gains Average power savings of 21% on average, as compared to the corresponding 2D implementation without performance degradation. Wirelength reduction of 26% (from to um) Partitioning was tuned for TSV-minimization. Characteristic 3D 2D Layer 1 (Logic) Layer 2 (Memory) Wire-length (um) 855, , ,440 Half-perimeter (um) 823, ,010 97,527 Number of TSVs Area reserved by TSVs (mm 2 ) Aspect ratio Area per layer 2.89 mm mm mm 2

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