MS Diploma and Semester Projects offered at the Microelectronic Systems Laboratory during the Spring 2015

Transcription

1 v1.2 as of MS Diploma and Semester Projects offered at the Microelectronic Systems Laboratory during the Spring 2015 Students are asked to contact the project responsible to register. The majority of the projects are proposed as MS Diploma and Semester, and the amount of work will be adapted. Also, some projects can be carried out in groups of two students. Projects are proposed in six categories in the following pages. Analog and mixed-signal circuits Digital circuits and modeling Bio-electronic interfaces and biomedical applications Fabrication technologies Industrial projects / external projects (for MSc diploma) Application development (software development) 1/11

2 Analog and mixed-signal circuits A1 Physically Unclonable Function (PUF) implementation and analysis as a fingerprint of hardware Physically unclonable functions (PUFs) are an emerging technology for hardware key generation aiming at improving data security. Unlike conventional software-based methods, the PUF technology utilizes variability of devices/circuits in order to provide extremely unique cryptographic keys. Using practically available random characteristics, a number of different architectures of PUFs have been introduced, such as arbiter-, Butterfly-, SRAM-PUF etc. Companies and universities have been exploring more advanced PUF technologies than the current ones, as a fingerprint of hardware. In this project, the student will learn mechanisms of the existing PUF technologies using SPICE simulation and FPGA implementation. Then, the student will modify them and/or propose a new way of improving PUF implementations, possibly using error correction algorithms. The goal of this project is to demonstrate good PUF performances in simulation or FPGA development in terms of robustness and implementation area. Upon reaching a successful FPGA implementation, a further step will be realized as an ASIC development, especially regarding the necessary analog components of the proposed PUF. This project can be carried out based on the research contract established with Toshiba Corp., which supports excellent research in academia by an unrestricted contribution to the LSM regarding the ongoing research of analog/digital CMOS/nano-electronics design and application for on-chip data analysis. Compact and robust PUF will be a key of secure IT technology for future internet-of-things (IoT) and wearable healthcare applications etc. A2 - A3 - A4 - A5-40% SPICE simulation 40% FPGA implementation 20% Data analysis (possibly including error correction) Knowledge of analog design is an extra, but not necessary. Project for 1/2 MSc diploma/semester student. Project responsible, Contact: Takao Marukame (takao.marukame@epfl.ch), Toshiba Corp. Responsible teacher: Alexandre Schmid (alexandre.schmid@epfl.ch) 2/11

3 Digital circuits and modeling D1 FPGA Implementation of MIPI PHY Interface The MIPI Alliance is a non-profit corporation that operates as an open membership organization. All companies in the mobile device industry are encouraged to join, including semiconductor companies, software vendors, IP providers, peripheral manufacturers, test labs and end product OEMs. Today, more than 275 member companies (including Intel, Nokia, Samsung, ST Microelectronics, Texas Instruments, Aptina, Apple, ARM etc.) actively participate in the Alliance, developing interface specifications which drive consistency in processor and peripheral interfaces, promoting reuse and compatibility in mobile devices. However, due to the nature of the interface, current I/O s for high-end FPGAs are not compatible for interfacing the MIPI outputs and FPGA devices. The main focus of this project is designing a basic MIPI interface for high speed (up to 1 GHz) High end 5MPixel Samsung cameras, by utilizing in house designed and tested PCB boards. The boards are converting MIPI signals to FPGA compatible signals and student will be responsible of implementing the interface for cameras with an onboard image processing tools. Since the interface will have full control over high-end cell phone cameras, the project can be further extended to a realtime computational photography camera, where user have full control over each camera parameter, where nowadays it is not possible on cell phone cameras. The student working on the project will gain knowledge about image processing, real-time hardware implementation, hardware-software codesign and high-end Virtex 7 FPGA. Single camera module Camera board with 3 cameras connected Back view of the camera board The project is organized as follows: Semester Project/Master Project Digital Hardware Implementation 80% Testing and Verification 20% Contact: Kerem Seyid, kerem.seyid@epfl.ch Responsible Teacher : Y. Leblebici D2 FPGA Implementation of Real-Time Superresolution Systems The most common method is to increase the pixel density, or in other words, reducing the pixel size (spatial resolution) by fabrication techniques. It is common knowledge that the scaling effects in CMOS technology allow the semiconductor industry to make smaller devices. This rule holds for CMOS imaging applications as well, however it is known that CMOS image sensor technology is lagging behind the technology nodes in ITRS roadmap. The reason behind this lagging is very simple: current CMOS process is not imaging friendly. Reducing the pixel sizes mean less amount of light available per pixel. Furthermore, smaller size generates shot noise that reduces the image quality. There is a limit to reduce the pixel pitch without suffering the effects of shot noise. In order to satisfy the current needs of technology, Superresolution methods are introduced. In this project, student will be responsible of developing a superresolution algorithm suitable for 3/11

4 real time implementation. The algorithm will be tested will real life sequences, with images coming from single or multiple cameras. Furthermore, the student will design and implement the algorithm in RTL level in high-end Xilinx Virtex-7 devices, and test the system with FPGA, where the realtime feed is provided by high-end cameras. Two examples of superresolution algorithms can be seen above. The images on the left is bicubic interpolation of the original images and the images on the right is the results of superresolution methods, obtained from real-life sequences. The student working on the project will gain knowledge about image processing, real-time hardware implementation, hardware-software codesign and high-end Virtex 7 FPGA. The project is organized as follows: Master Project Literature survey 10% Matlab Implementation 30% Digital Hardware Implementation 60% Contact: Kerem Seyid, kerem.seyid@epfl.ch Responsible Teacher : Y. Leblebici D3 ASIC Design for Real-Time Panoramic Multi-Camera System Panoptic is a multi-camera system able to acquire and render the whole light field around the observer, using panoramic representation. The designed Panoptic prototypes are based on CMOS cell phone cameras which result in low final panorama image resolution. One of the drawbacks of Panoptic is the limited processing flexibility due to use of Virtex-5 FPGAs. The goal of this project is to design an ASIC for the purpose of creating real-time panoramic videos. Currently working FPGA system will be provided as a reference and the ASIC will be designed to support higher resolution cameras and High Definition (Full HD) output. The first steps of the project will include adapting the current Panoptic algorithms to the desired technology. The second step will include development of the interface IPs, such as Camera interface, HDMI display, UART, Memory controller. 30% Algorithm study 60% VHDL implementation, synthesis and simulation 10% Chip fabrication and measurements Project for 1 or 2 MSc diploma/semester student. 4/11

5 D4 Panorama Construction using NVidia GPU Panoptic is a multi-camera system able to acquire and render the whole light field around the observer, using panoramic representation. The designed Panoptic prototypes are based on low-cost CMOS cell phone cameras which resulted in low final panorama image resolution. One of the drawbacks of Panoptic is the limited processing flexibility due to use of Virtex-5 FPGAs. On the other hand, GPUs offer higher flexibility, faster prototyping of the envisioned algorithms, and more algorithm options. The idea of the project is to create a GPU-based processing system and compare it to the current FPGA design, in terms of both quality and performance. The project will be defined according to the student's prior knowledge of CUDA, which is not obligatory. The first steps will include porting the current Panoptic algorithms to the GPU and comparing its performance. The second step will include development of the new algorithms for image quality improvement and their GPU implementation. 30% Algorithm study 70% CUDA programming Prior knowledge of CUDA is not obligatory. Project for 1 MSc diploma/semester student. D5 PCIe Controller for FPGA PC connection The project is realized as a part of the PANOPTIC camera project ( en.html). The previous systems were able to interface with the PC/user via simple UART or USB interface. Currently, a new, very high-resolution camera system is being designed. One of the advantages of the system will be the ability to display a Full HD 1080 resolution at 30 frames per second. This signal needs a very fast transfer to the PC in order to be processed later by the available GPU. In this project, the student will work on the state-of-the-art Virtex-7 FPGA and design a PCIe controller, which will allow the FPGA board to be plugged in directly into the motherboard of the PC. The student will create a new (adapt an IP core) controller and embedded it into an already existing operational system. If needed, the initialization routines for microprocessor on board will be written. Finally, the controller will be tested by sending/receiving the data stream. A small PC test application will be created for that purpose. 30% VHDL design 50% FPGA implementation 20% C/C++ code development Project for 1 MSc diploma/semester student. D6 Reconstruction of High Dynamic Range images Brightness and contrast in the modern photographs does not represent truthfully the look of the natural scenes. High Dynamic Range (HDR) imaging is a developed technique to overcome this issue. The main idea is to capture the same scene under several different exposure settings, in order to acquire both the brightest and the darkest regions of the scene. In this project, the student will develop a new algorithm for combining such images. The algorithm is based on a new CMOS image sensor designed at LSM, and the outcome of the project will serve 5/11

6 as a starting point for the potential new architecture of the image sensors. The first steps of the project include study of the current HDR algorithms. The later steps include development and implementation of the new algorithm, comparative analysis with the state-of-theart methods, and the proposal for the best CMOS imager architecture. 40% Algorithm study 60% Matlab / C / C++ development (only one of them is necessary) Project for 1 MSc diploma/semester student. D7 JPEG / PNG image compression on FPGA and SATA controller for SSD storage The project is realized as a part of the PANOPTIC camera project ( en.html). The images acquired by the cameras are currently stored in RAW format, resulting in the large file size. Hence, an appropriate image compression should be applied to reduce the size without affecting the image quality. In this project, the student will work on the state-of-the-art Virtex-7 FPGA and design a real-time PNG (or JPEG) compression accelerator. The student will create a new core (adapt an IP core) and embedded it into an already existing operational system. Second part of the project consists of designing a small SATA controller for image storage on external SSD drive. 30% Algorithm study 50% VHDL design 20% FPGA implementation Project for 1 MSc diploma/semester student. D8 Sound acquisition and direction detection on Virtex-5 FPGA The project is realized as a part of the PANOPTIC camera project ( en.html). The previous systems were able to acquire only image frames without any audio, resulting in an incomplete multimedia experience. In this project, the student will work on the custom-made Virtex-5 FPGA system and design a module for acquisition and processing of the audio signals. The final goal is two-folded: 1) Provide full multimedia content to the user with both video and audio; 2) detect the direction of the incoming sound, and center the panoramic reconstruction to the detected direction. 30% Algorithm study 50% VHDL design 20% FPGA Implementation Prior knowledge of audio processing is not necessary. Project for 1 MSc diploma/semester student. 6/11

7 D9 Deep learning digital hardware implementation Deep Learning is an emerging algorithm of artificial neural network based machine learning, which has been introduced with the objective of being closer to Artificial Intelligence. In recent years, companies including Google, Microsoft and Apple have developed software-based deep learning systems in order to improve their service qualities like speech recognition and image classification. Inspired by this practical algorithm, system scientists in companies like IBM have been developing a new type of computer architecture that includes a mimic of human brain s neural networks in order to realize massive parallelism and ultra-low power. This project will introduce some of the important deep learning algorithms. Then, the student will realize the challenging implementation of the algorithm into digital hardware using HDL code. In the first step of the project, the goal is to demonstrate working operation of deep learning in FPGA and to argue comparisons with the current software algorithm in terms of speed performance and implementation area. Upon reaching a successful FPGA implementation, a further step will be realized as an ASIC development. This project can be carried out based on the research contract established with Toshiba Corp., which supports excellent research in academia by an unrestricted contribution to the LSM regarding the ongoing research of analog/digital CMOS/nano-electronics design and application for on-chip data analysis. Our future goal is to create a brain-inspired processing system using state-ofthe art non-volatile memory technology. The project results have a great potential to become a key technology for biomedical, robotic, automotive applications etc. 30% Algorithm study and data analysis 50% HDL design 20% FPGA implementation Project for 1/2 MSc diploma/semester student. Project responsible, Contact: Takao Marukame (takao.marukame@epfl.ch), Toshiba Corp. Responsible teacher: Alexandre Schmid (alexandre.schmid@epfl.ch) 7/11

8 Bio-electronic interfaces and biomedical applications B1 None to report B2 - B3-8/11

9 Fabrication technologies N1 None to report N2 - N3-9/11

10 Industrial projects / External projects (MSc diploma) IE1 None to report 10/11

11 Application development (software development) SW1 Application Development for Omnidirectional Vision Reconstruction System Panoptic is a custom spherical light field camera used as a polydioptric system where imagers are distributed over a spherical geometry, each having its own vision of the surrounding and a distinct focal plane. The spherical light field camera records light information from any direction around its center. Three dimensional (3D) visualization of a full 360º scene forms the foundation for enabling the emergence of novel applications in security systems, automotive platforms and mobile robots, realistic computer games and 3D cinematography. The utilization of such systems with 360º 3D visual characteristics has recently significantly increased, with the commercialization of consumer electronics products. In this project, student will be responsible for implementing and ios application for ipads and iphones, for viewing the omnidirectional data in an immersive way. Currently, an Android application for the same purpose, and the Oculus Rift application is implemented for real-time omnidirectional camera as can be seen in video link. It is expected that the student has prior knowledge for ios app development. The student working on the project will gain knowledge about image processing, network streaming and ios app development, as well has hardware implementation of multiple camera systems Semester Project Software Development 100% Contact: Kerem Seyid, kerem.seyid@epfl.ch Responsible Teacher : Y. Leblebici 11/11