Digitization of non-volatility Jean-Pascal BOST, CEO

Transcription

1 D a t a - e f f i c i e n t w o r l d Digitization of non-volatility Jean-Pascal BOST, CEO

2 Lab spin-off Incorporated people IP Fabless Non volatile Semiconductor IP emram erram

3 Where does it hurt? End users want to have the cake and eat it too: IP providers shall respond envram demand driven by: eflash, OTP, esram, logic(partial) replacement Ultra low power demand Cost management (vs eflash and at system level with rearchitecture) 10/2/2017 3

4 Full solutions with evaderis Connected Object Powered by evaderis Long lifetime wearable medical analysis SENSE COM STORE PROCESS Long lifetime smart vision (automotive, smarts cities...) Enable On Thing Machine learning Artificial intelligence 10X extended lifetime 10X energy saving More processing TCO, QoS Sensor/data fusion, micro storage (industry ) 10/2/2017 4

5 evaderis 2012 bet: 1 st mover Technology/Standalone Providers (Everspin, TDK, Crossbar, ) Material/Process R&D Standalone Indus Standalone Prod Foundries (GF, Samsung, TSMC, SMIC ) Embedded Indus Embedded Prod IP Providers (embedded) (ARM, Kilopass, evaderis ) Enable innovative NVRAM IP ecosystem Design Automation Physical Design System Design and Software for IoT Ecosystem will require IP company around Build a team, an expertise Develop dedicated non-volatile design tools and flows (Design Automation) Develop and prototype first non-volatile designs (Physical and System Design) Settle system and software level approach for ultra low power IoT, mobile As a 1 st mover, to be the leading company offering energy efficient IP solutions 10/2/2017 5

6 Value proposition (1/2) Subsystem Processor IP (non volatile) Software IP (drivers, apps) Memory IP (non volatile compilers) evaderis-powered Customer chip Power (active & standby) Flexibility (hardware & software) Costs (density & process) 10/2/2017 6

7 Value proposition (2/2) Customer chip Standard IP evaderis Non volatile IP CPU MEM1 CPU MEM1 MEM2 USB WIFI MEM2 USB WIFI Energy consomption: x Energy consomption: x/10 to x/ /2/2017 7

8 Assets 6 patents on disruptive architectures and designs Design database (analog, digital/software in esttram/40nm technology) Design tools enabling industrial outputs (Callisto Framework): o o o o o o o Add-ons to commercial-production tools Manage new physical phenomena's/impacts from device up to application Enable fast and accurate simulations, analysis with automation and modeling Java-based big data approach for fast products analysis and optimization Easy migration from one technology to an other (esttram, ereram) Easy migration from one foundry to an other (GF, TSMC, Samsung, SMIC, ) Generate IPs and compilers aligned with standardization (plug and play) 10/2/2017 8

9 NV Macro to NV Platform CPU MEM3 MEM1 MEM2 PMU CLK BIAS UART GPIO ADC TIMERS RF Current approach eflash macro replacement Limited or no digital views Limit system optimization Increase risk of errors at system level Not compatible with (all) customer s EDA tools New features Load/restore context at system bus level (thru bus, word by word) 10/2/2017 9

10 NV Macro to NV Platform CPU MEM1 MEM2 UART GPIO New features Slow (compared to SRAM) NVRAM working memory No need to load states, just restore MEM3 PMU CLK BIAS ADC TIMERS RF New requirements Manage efficiently memory hierarchy eflash, NVRAM, SRAM New digital controllers or software In data or control logic path with frequents R/W access Need more data, more accurate timing, power...for optimized system design Enter the SRAM (logic) world with multiple instances: move toward memory generators Multiple blocks: start to share dedicated BIAS block at system level for area/power optimization Faster reboot from previous states start to put the pressure on the CLK wake up time 10/2/

11 NV Macro to NV Platform CPU MEM3 MEM1 MEM2 PMU CLK BIAS UART GPIO ADC TIMERS RF New features High-speed NV SRAM working memory Load states shadowed (in RAM, local), just restore Requirements New digital controllers or software for NV SRAM management In data or control logic path with CPU f R/W access Need even more data, more accurate timing, power...for optimized system and processing design Enter the SRAM (logic) world with multiple instances: move even more toward memory generators 10/2/

12 NV Macro to NV Platform CPU MEM3 MEM1 MEM2 PMU CLK BIAS UART GPIO ADC TIMERS RF New features Instant-on peripherals Massive parallel save/load configurations New requirements Generate dedicated NV-logic libraries/cells to store non-volatile local configurations High digital flexibility (different sizes, functions...) need a logic synthesis friendly approach Library generation aligned with 3 rd part standard cells formats (again, timing, power...) and constraints (layout...) Power management/reset (PMU) update for wake-up and save sequences with non-volatile logic cells and memory (rush currents, islands, priorities...) BIAS shared with memories and multiple logic cells Fast wake-up CLK 10/2/

13 NV Macro to NV Platform CPU MEM3 MEM1 MEM2 PMU CLK BIAS UART GPIO ADC TIMERS RF New features Full Instant-on system and Normally-off Massive parallel save/load intermediate processing states: advanced check pointing mechanism New requirements Generate dedicated NV-logic libraries/cells to store non-volatile local processing states Dedicated software to manage the NV technology at system level (check pointing, memory alloc...) High digital flexibility (different sizes, functions...) need a logic synthesis friendly approach Library generation aligned with 3 rd part standard cells formats (again, timing, power...) and constraints (layout...); even more critical than for configuration -> part of data/control path. Power management/reset (PMU) update for wake-up and save sequences with non-volatile logic cells and memory (rush currents, islands, priorities...) 10/2/

14 Challenges Generate digital views for production Enable non-volatile low power flow for system design 10/2/

15 Silicon to System Design evaderis covers all emram related topics from raw silicon data up to digital design MRAM digitization MRAM (MTJ) SPICE/Compact model development Advanced emram-based IP design (not only memory) Physical IP view generation (enable compatibility for digital EDA tools) Dedicated and optimized system design and software development 10/2/

16 Activities Memory compiler friendly, support across multiple simulators... Memory level, register level, RNG... MCU (RTL) level, memory controller, energy management unit, biasing, DFT unit... Intelligent memory allocation, instant-on function, checkpointing... Silicon 2 Digital SPICE Development Physical Design System Design Software Development Design Automation Framework to enable Non-Volatile Digital Flows at SoC level Powered by evaderis Feedback IP update Demo Chip (MCU-like) Multifunctional/application IoT board to demonstrate, benchmark and analyze the gains at application level (partnership) Demo Board Development Application Development 10/2/

17 Framework for emram design Apps Prod (production, QA) Resistive Memory Core (RMC) Framework NVRAM Library Generator NVRAM Data Design Analytics NVRAM Compiler Generator Non-Volatile logic Kit (NVK) Generator Software Development Kit Apps Dev (design optimization) NVRAM Cockpit NVRAM Yield Analyser NV System Impact Analysis NVRAM Simulation Optimizer Device2System Optimization Loop Powered by evaderis Dedicated Design Automation Framework For emram (erram compatible) 10/2/

18 FDSOI and emram A powerful combo at system level: Standard system Standby power (BB) FDSOI Active Power (scaling) Low power system Standby Power (Instant-on/Normally-off) emram Dynamic Power (BB density, locality) Power-misery system 10/2/

19 Thank you! Q&A: