HIGH-LEVEL SYNTHESIS FOR REAL-TIME DIGITAL SIGNAL PROCESSING
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1 HIGH-LEVEL SYNTHESIS FOR REAL-TIME DIGITAL SIGNAL PROCESSING
2 THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE VLSI, COMPUTER ARCHITECfURE AND DIGITAL SIGNAL PROCESSING Latest Titles Consulting Editor Jonathan Allen Introduction to the Design of Tmnsconductor-Capacitor Filters, J. E. Kardontchik ISBN: The Synthesis Approach to Digital System Design, P. Michel, U. Lauther, P. Duzy ISBN: Fault Covering Problems in Reconfigurable VLSI Systems, R.Libeskind-Hadas, N. Hassan, J. Cong, P. McKinley, C. L Liu ISBN: High Level Synthesis of ASICs Under Timing and Synchronization Con51mints D.C. Ku, G. De Micheli ISBN: The SECD Microprocessor, A Verification Case Study, B.T. Graham ISBN: Field-Programmable Gate Armys, S.D. Brown, R. J. Francis, J. Rose, z.g. Vranesic ISBN: Anatomy of A Silicon Compiler, R.W. Brodersen ISBN: Electronic CAD Fmmeworks, T J. Barnes, D. Harrison, A.R. Newton, R.L Spickelmier ISBN: vndl for Simulation, Synthesis and Formal Proofs of Hardware, J. Mermet ISBN: Wal'elet Theory and its Applications, R. K. Young ISBN: X Digital BiCMOS Integmted Circuit Design, S.H.K. Embabi, A. Bellaouar, M.I Elmasry ISBN: Design Alltomation for Timing-Driven Layout Synthesis, S. S. Sapatnekar, S. Kang ISBN: Acollstical and Environmental Robustness in Alltomatic Speech Recognition, A. Acero ISBN: Logic Synthesis and Optimization, T. Sasao ISBN: Sigma Delta Modulators: Nonlinear Decoding Algorithms and Stability Analysis, S. Hein, A. Zakhor ISBN: High-Level Synthesis for Real-Time Digital Signal Processing: The Cathedral-II Silicon Compiler J. Vanhoof, K. Van Rompaey, I. Bolsens, G. Goossens, H. De Man ISBN:
3 HIGH-LEVEL SYNTHESIS FOR REAL-TIME DIGIT AL SIGNAL PROCESSING by Jan Vanhoof Karl Van Rompaey Ivo Bolsens Gert Goossens Hugo De Man IMECvzw Springer-Science+Business Media, B.V.
4 Library of Congress Cataloging-in-Publication Data High-level synthesis for real-time digital signal processing: the Cathedral-II silicon compiler I Jan Vanhoof... [et al.1. p. cm. -- (The Kluwer international series in engineering and computer science : v. 216) Includes bibliographical references and index. ISBN ISBN (ebook) DOI / Application specific integrated circuits--design and construction--data processing. 2. Silicon compilers. 3. Computer -aided design. 4. Signal processing--digital techniques. I. Vanhoof. Jan. II. Series: Kluwer international series in engineering and computer science : SECS 216. TK H dc Printed on acid-free paper All Rights Reserved 1993 Springer Science+Business Media Dordrecht Originally published by Kluwer Academic Publishers in 1993 Softcover reprint of the hardcover 1st edition 1993 as specified on appropriate pages within. No part of the material protected by this copyright notice may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording or by any information storage and retrieval system, without written permission from the copyright owner.
5 Contents 1 Introduction History and related work General-purpose computers General-purpose micro-processors Digital signal processors Application-specific DSP chips Very long instruction word architectures Domain-specific DSP chips Design methodologies for silicon compilation Design methodologies for architecture synthesis The C.A.TB.DB..A.L silicon compilers Outline ohhis book DSP architecture s7nthesis Digital signal processing Characteristics of DSP systems we exploit Characteristics of DSP systems that make it hard DSP system specifications Essential programming constructs DSP languages A iii f'ouge example Data structures Operations Control functions DSP target architectures Programmable DSPs VLIW architectures Functional building blocks Execution units Data path interconnections Timing model Controller model Building a DSP silicon compiler Problem formulation General principles Compiler phases Optimisation criteria Optimisation strategy Compiler directives Summary
6 vi a Im.plementation of data BbuctureB 3.1 Literature survey Memory management strategy Once-over lightly Types of memory in the C.A.TU.DB..A.L-II architecture Address generation hardware SIL.A.G. data streams Sbategy overview 3.3 Consbained storage Storage order Access order Window computation Selecting storage and access order 3.4 Unconsbained storage Selecting resource types and instances Default memory assignment Memory assignment directives Default address hardware assignment Address hardware assignment diredives 3.6 Organising indirectly-addressed memories Organising pages as circular buffers Circular buffer compadion Page compaction Organising diredly-addressed memories Non-repetitive and unconditional applications Repetitive and unconditional applications Repetitive and conditional applications 3.8 Physical address generation... " Direct-address generation Hardware indired-address generation Software indired-address generation 3.9 Summary Implementation of high-level operations 4.1 Code expansion sbategy Once-over lightly Sbategyoverview Explicitising data dependencies 4.3 Code expansion Signal name generation Type selection Code expansion macros Expression simplifications 4.4 Data routing
7 vii Register-transfer descriptions Demand-driven mapping. 4.5 Summary IInplelDentation o control functions 5.1 Literature survey. 5.2 Control fundion implementation strategy Once-over lightly Strategy overview Selection Alternatives for conditional control strudure generation Conditional code motion Conditional code lowering Correding code hoisting Optimising code hoisting TradeofFs Repetition Loop transformations Correding code hoisting Optimising code hoisting 5.5 Hierarchy Multi-rate systems Multi-rate semantics of SIL.A.GB control fundions Transforming multi-rate code into single-rate code Conversion to the lowest rate Conversion to the highest rate 5.7 Summary Scheduling 6.1 Scheduling strategy Terminology Time-area tradeoffs Strategy overview Scheduling algorithms Data dependency graph Precedence graph _ List scheduling JIT scheduling Incremental scheduling. 6.3 Graph transformations Loop folding Condition code hoisting Recomputation Unrepetitive code lowering
8 viii 6.4 The balancer Bounding the time-allocation search space Fixing the resource allocation Memory and loop folding optimisation. 6.5 Estimators Cycle count Data path area Memory area Controller area Summary Sbuctu1'e gene:ration 7.1 Literature survey Architectural assumptions Assignment cost functions Structure generation strategy Instance assignment Register file instance assignment Execution unit instance assignment N etlist generation Crossbar switch generation Test buses Structure optimisation Bit-level interconnection Execution unit parameters.. Summary Delllonsbato:r designs 8.1 An 8-ary baseband PAM modem for ISDN System specification Algorithmic description Architecture synthesis Chip evaluation An 800 bit/s voice coder System specification Algorithmic description Architecture synthesis Chip evaluation Summary Bibliography Index
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