# Computer Architecture. Lecture 2 : Instructions

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1 Computer Architecture Lecture 2 : Instructions 1

2 Components of a Computer

3 Hierarchical Layers of Program Code 3

4 Instruction Set The repertoire of instructions of a computer 2.1 Intr roduction Different computers have different instruction sets But with many aspects in common 4

5 The MIPS Instruction Set Used as the example throughout the book Stanford MIPS commercialized by MIPS Technologies ( Founded in 1984 by? Large share of embedded core market Applications in consumer electronics, network/storage equipment, cameras, printers, Typical of many modern ISAs 5

6 Instruction Set Stored-program concept The idea that instructions and data of many types can be stored in memory as numbers, leading to stored-program computer Let us look into MIPS instruction ti set one by one to understand this 6

7 Arithmetic Operations Add and subtract, three operands Two sources and one destination add a, b, c 2.2 Ope erations of the Com mputer Ha ardware # a gets b + c 7

8 Arithmetic Operations Operand is a quantity on which an operation is performed add a, b, c How many operands in this instruction? 2.2 Ope erations of the Com mputer Ha ardware All arithmetic operations have this form 8

9 Arithmetic Operations All arithmetic operations have same form What if we want to add b,c,d,,,, and e and put the result into a? 2.2 Ope erations of the Com mputer Hardware 9

10 Design Principle 1 All arithmetic operations have same form Design Principle 1: Simplicity favors regularity Regularity makes hardware implementation simpler 2.2 Ope erations of the Com mputer Ha ardware 10

11 Arithmetic Example C code: f = (g + h) - (i + j); Compiled MIPS code:? Hints: Use sub instruction,e.g., a=b-c, is sub a,b,c Use two temporary variables t0 and t1 11

12 Arithmetic Example C code: f = (g + h) - (i + j); Compiled MIPS code: add t0, g, h # temp t0 = g + h add t1, i, j # temp t1 = i + j sub f, t0, t1 # f = t0 - t1 12

13 Register Operands The operands of arithmetic instructions must be from special location in hardware called registers Registers are primitives of hardware design and are visible to programmers 2.3 Ope erands of the Computer Har dware 13

14 Assembler names Register Operands \$t0, \$t1,, \$t9 for temporary values \$s0, \$s1,, \$s7 for saved variables 2.3 Ope erands of the Comp puter Hardware 14

15 Register Operand Example Compiler s job to associate variables of a highlevel program with registers C code: f = (g + h) - (i + j); f,, j in \$s0,, \$s4 Compiled MIPS code? 15

16 Register Operand Example Compiled MIPS code: add \$t0, \$s1, \$s2 add \$t1, \$s3, \$s4 sub \$s0, \$t0, \$t1 16

17 Register Operands MIPS has a bit register file Numbered 0 to bit data called a word Word is the natural unit of access, typically 32 bits, corresponds to the size of a register in MIPS 2.3 Ope erands of the Comp puter Har dware There may be only 3 operands and they must be chosen from one of the 32 registers. Why only 32? 17

18 Smaller is faster Design Principle 2 Larger registers will increase clock cycle time --- electronic signals takes longer when they travel farther Design principles are not hard truths but general guidelines 31 registers instead of 32 need not make MIPS faster 2.3 Ope erands of the Comp puter Har dware 18

19 Memory Operands Programming languages, C, Java, Allow complex data structures like arrays and structures They often contain many more data elements than the number of registers in a computer Where are they stored? Memory But, arithmetic operations are applied on register operands Hence, data transfer instructions are required to transfer data from memory to registers Load values from memory into registers Store result from register to memory 19

20 Memory is like an array Data transfer instructions must supply the address (index/offset) of the memory (array) 20

21 Memory Operands Memory is bt byte addressed d Each address identifies an 8-bit byte Words are aligned in memory Each word is 32 bits or 4 bytes To locate words, addresses are in multiples of 4 21

22 A is an array of words What is the offset to locate A[8]? A[0] 0 A[1] 4 A[2] 8 A[8] 32 22

23 Memory Operands Why is memory not word-addressable? dd 23

24 Memory Operands Why is memory not word-addressable? dd Bytes are useful in many programs. In a word addressable system, it is necessary first to compute the address of the word containing the byte, fetch that word, and then extract the byte from the two-byte word. Although the processes for byte extraction are well understood, they are less efficient than directly accessing the byte. For this reason, many modern machines are byte addressable. 24

25 Memory Operands Load instruction lw refers to load word lw registername, offset (registerwithbaseaddress) lw \$t0, 8 (\$s3) offset base register 25

26 Memory Operand Example 1 C code: g = h + A[8]; g in \$s1 h in \$s2 base address of A in \$s3 A is an array of 100 words Compiled MIPS code? 26

27 Memory Operand Example 1 C code: g = h + A[8]; g in \$s1, h in \$s2, base address of A in \$s3 Compiled MIPS code: lw \$t0, 32(\$s3) # load word add \$s1, \$s2, \$t0 offset base register 27

28 Memory Operand Example 2 C code: A[12] = h + A[8]; h in \$s2, base address of A in \$s3 Compiled MIPS code: 28

29 Memory Operand Example 2 C code: A[12] = h + A[8]; h in \$s2, base address of A in \$s3 Compiled MIPS code: Index 8 requires offset of 32 lw \$t0, 32(\$s3) # load word add \$t0, \$s2, \$t0 sw \$t0, 48(\$s3) # store word 29

30 Registers vs. Memory Registers are faster to access than memory Operating on memory data requires loads and stores More instructions to be executed Compiler must use registers for variables as much as possible Only spill to memory for less frequently used variables Register optimization is important! 30

31 Immediate Operands Constant data specified in an instruction addi \$s3, \$s3, 4 No subtract immediate instruction Just use a negative constant addi \$s2, \$s1, -1 31

32 Design Principle3 Make the common case fast Small constants are common : immediate operand avoids a load instruction Allows us to avoid using memory meaning faster operations and lesser energy 32

33 The Constant Zero MIPS register 0 (\$zero) is the constant 0 Cannot be overwritten Useful for common operations E.g., move between registers add \$t2, \$s1, \$zero 33

34 Problems In the snippet of MIPS assembler code below, how many times is the memory accessed? How many times data is fetched from memory? lw \$v1, 0(\$a0) addi \$v0, \$v0, 1 sw \$v1, 0(\$a1) addi \$a0, \$a0, 1 Write the MIPS assembly language instructions for the following C statement. tt t Assume f is stored in \$s0, g in \$s1 and h in \$s2. Use a minimal i number of MIPS statements and a minimal number of registers. f = g + (h 5) 34

35 Stored-program concept The idea that instructions and data of many types can be stored in memory as numbers, leading to stored-program computer 35

36 Representing Instructions Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, Regularity! Register numbers \$t0 \$t7 are reg s 8 15 \$s0 \$s7 are reg s Rep presenting Instructi ions in the Comput ter 36

37 Example add \$t0, \$s1, \$s2 special \$s1 \$s2 \$t0 0 add op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 37

38 Representing Instructions The layout or the form of representation of instruction is composed of fields of binary numbers The numeric version of instructions is called machine language and a sequence of such instructions is called machine code 38

39 Instruction types R format (for register) Add, sub I-format (for immediate) Immediate Data transfer 39

40 MIPS R-format Instructions op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Instruction fields op: operation code (opcode) rs: first source register number rt: second source register number rd: destination register number shamt: shift amount (00000 for now) funct: function code (extends opcode) 40

41 MIPS I-format Instructions op rs rt constant or address 6 bits 5 bits 5 bits 16 bits Immediate arithmetic and load/store instructions rt: destination register number rs: register number with address Constant/ Address: offset added to base address in rs 41

42 Design Principle 4 Ideally, Keep all instructions of the same format and length But this makes it difficult to address large memories Compromise and allow different formats Principle 4: Good design demands good compromises Different formats complicate decoding, but allow 32-bit instructions uniformly Keep formats as similar as possible See example in page 98 42

43 Stored Program Computers Instructions represented in binary, just like data Instructions and data stored in memory Programs can operate on programs e.g., compilers, linkers, Binary compatibility allows compiled programs to work on different computers Standardized ISAs 43

44 Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left << << sll Shift right >> >>> srl Bitwise AND & & and, andi Bitwise OR or, ori Bitwise NOT ~ ~ nor 2.6 Log gical Opera ations Useful for extracting and inserting groups of bits in a word 44

45 Shift Operations Shift left logical Shift bits to the left and fill the empty bits with zeros sll \$t2,\$s0,3\$s

46 Shift Operations Shift left logical Shift bits to the left and fill the empty bits with zeros sll \$t2,\$s0,3\$s

47 Shift Operations Shift left logical Shift bits to the left and fill the empty bits with zeros sll \$t2,\$s0,3\$s sll by i bits multiplies by 2 i 47

48 Shift Operations op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 48

49 Shift Operations op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits sll \$t2,\$s0, \$s0 \$t2 shamt: how many positions to shift Similarly, Shift right logical 49

50 AND Operations Mask bits in a word Select some bits, clear others to 0 and \$t0, \$t1, \$t2 \$t2 \$t1 \$t

51 OR Operations Include bits in a word Set some bits to 1, leave others unchanged or \$t0, \$t1, \$t2 \$t2 \$t1 \$t

52 NOT Operations Useful to invert bits in a word Change 0 to 1, and 1 to 0 MIPS has NOR 3-operand instruction a NOR b == NOT ( a OR b ) nor \$t0, \$t1, \$zero Register 0: always read as zero \$t1 \$t

53 Hexadecimal Numbers Reading binary numbers are tedious So, hexadecimal representation is popular Base 16 is power of two and hence it is easy to replace each group of 4 binary digits 53

54 Base 16 Hexadecimal Compact representation of bit strings 4 bits per hex digit c d a 1010 e b 1011 f 1111 Example: eca8 6420? Example: eca8 6420? Example:

55 Conditional Operations Branch to a labeled instruction if a condition is true Otherwise, continue sequentially beq rs, rt, L1 if (rs == rt) branch to instruction labeled L1; bne rs, rt, L1 if (rs!= rt) branch to instruction labeled L1; j L1 unconditional jump to instruction labeled L1 2.7 Inst tructions for Makin ng Decisio ns 55

56 Compiling If Statements C code: if (i==j) f = g+h; else f = g-h; f, g, in \$s0, \$s1, 56

57 C code: Compiling If Statements if (i==j) f = g+h; else f = g-h; f,,g, in \$s0,,\$ \$s1, Compiled MIPS code: bne \$s3, \$s4, Else add \$s0, \$s1, \$s2 j Exit Else: sub \$s0, \$s1, \$s2 Exit: 57 Assembler calculates addresses

58 RISC vs CISC 58

59 CISC Approach Complex Instruction Set Computer C code: g = h + A[8]; CISC add a,32<b> Achieved by building complex hardware that loads value from memory into a register and then adds it to register a and stores the results in register a 59

60 CISC vs RISC C code: g = h + A[8]; CISC add a,32<b> Compiled MIPS code: lw \$t0, 32(\$s3) # load word add \$s1, \$s2, \$t0 60

61 CISC Advantages Compiler has to do little Programming was done in assembly language To make it easy, more and more complex instructions were added Length of the code is short and hence, little memory is required e to store the code Memory was a very costly real-estate E.g., Intel x86 machines powering several million desktops 61

62 RISC Advantages Each instruction needs only one clock cycle Hardware is less complex 62

63 RISC Roadblocks RISC processors, despite their advantages, took several years to gain market Intel had a head start of 2 years before its RISC competitors Customers were unwilling to take risk with new technology and change software products They have a large market and hence, they can afford resources to overcome complexity 63

64 Fallacies Powerful instruction higher performance Fewer instructions required But complex instructions are hard to implement May slow down all instructions, including simple ones Compilers are good at making fast code from simple instructions Use assembly code for high performance But modern compilers are better at dealing with modern processors More lines of code more errors and less productivity 2.18 Fa llacies an d Pitfalls 64

65 Fallacies Backward compatibility instruction set doesn t change But they do accrete more instructions x86 instruction ti set 65

66 Pitfalls Sequential words are not at sequential addresses Increment by 4, not by 1! 66

67 CISC vs RISC Very good slides on the topic s/pdf/riscvscisc.pdf 67

68 Patterson s blog: risc-versus-cisc-wars-in-the-prepc-and-pc-eraspart-1/ Interview with Hennessy ts/risc/about/interview.html /i /b /i i 68

69 Concluding Remarks Design principles 1.Simplicity favors regularity 2.Smaller is faster 3.Make the common case fast 4.Good design demands good compromises Layers of software/hardware Compiler, assembler, hardware MIPS: typical of RISC ISAs c.f. x Co oncluding Remarks 69

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