RTL Quality for TLM Models

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1 RTL Quality fr TLM Mdels Preeti Sharma, Senir R&D Engineer I, Synpsys (India) Pvt. Ltd., Nida, India Abstract Mre s law, which predicts that every tw years, the number f transistrs that can be placed nt a chip gets dubled, hlds true fr the enrmus cmplex systems being designed tday. With ptential increases in chip sizes, and crrespnding increase in functinality and prduct features, design quality and verificatin prcesses must be faster and efficient, t pace up with prductivity. Bug escapes and lw-quality prducts, nt nly incur cnsiderable csts t cmpanies, if identified at later stages, but als seriusly damage a cmpany s reputatin in market. The need f the hur is hence debug ease, reduced number f lines f cde, and rbust design and verificatin prcesses. Fr design develpment, Transactin Level Mdeling is emerging as a standard slutin fr virtual prttyping that prvides faster simulatin speeds. Since RTL is a direct representatin f the SC architecture, virtual prttypes shuld be as clse in functinality and behavir t their respective RTL, s as t yield substantial gains in hardware/sftware develpment life f a cmplete SC r ASIC based system. This call fr the need f a similar and standard verificatin flw fr TLM mdels, as currently exists fr RTL designs. RTL designs are knwn t use frmal tls and standard verificatin set-ups t verify cmplex designs and ensure functinal crrectness. One such hybrid methdlgy is the Universal Verificatin Methdlgy (UVM). It is highly desirable, that TLM mdels als g thrugh similar high quality verificatin prcesses, t ensure that the standard ways that find bugs in RTL, can enable TLM mdel develpers, t find bugs in their design as well, alngside measuring behaviral deviatin with respect t the RTL IP. This paper explains hw a similar verificatin apprach can be develped fr a TLM IP, using same standard UVM methdlgies, that RTL verificatin engineers use wrldwide. Keywrds TLM;verificatin;RTL;UVM;standard;simulatin I. INTRODUCTION The cmplexity f devices under test (DUTs) is cntinuusly increasing in the semicnductr industry, primarily because f grwing functinal cntent cmplexity and the sheer amunt f functinal blcks cntained in a typical SC. Hence, the hardware engineers cntinue t aim fr develping DUTs, with mre cmplicated functinalities, faster speeds and with lw csts. At the same time, these SCs are expected t perfrm better with high quality cmpared t their predecessrs. This phenmenn has thrwn a significant challenge t test engineers t develp mre cmplex test systems. With such ever increasing cmpetitin, there are tw prime cncerns these SCs face in the digital design wrld tday. First and fremst is time t market fr a prduct frm the cncept t the end level prduct. Virtual prttyping, as a methd is gaining acceptance, t prvide a slutin fr the same. Transactin-level mdeling (TLM), a high-level apprach t mdeling hardware designs, is a methdical and systematic virtual prttyping slutin. In TLM, details f cmmunicatin amng mdules are separated frm the details f the implementatin f functinal units r f the cmmunicatin architecture. Such shift in abstract level suggests that an rder-f-magnitude imprvement in designer prductivity is indicated. SystemC is the best standard fr describing transactin-level designs with a link t implementatin and ffers the best pprtunities fr reusability. It mdels hardware cncurrency and describes bth timed and untimed behavir fr prcesses, pins, threads, and cntrl lgic.

The prblem nw arises when the mst basic intent f using TLM mdels, i.e. faster simulatin speeds and hence easy hardware-sftware c-develpment, get cmprmised.

The amunt f time needed t debug, analyze and fix the rt-cause issue in a pr-quality TLM mdule in a cmplex virtual platfrm, ver-shadws the benefits that it can prvide, i.e. less time-t-market in develping end-level system level.

TLM mdels can nw be added in this flw as equivalence t RTL, fr early design and verificatin f system level designs.

2 The prblem nw arises when the mst basic intent f using TLM mdels, i.e. faster simulatin speeds and hence easy hardware-sftware c-develpment, get cmprmised. This happens when a cmplex virtual platfrm cnsists f faulty TLM blcks. The amunt f time needed t debug, analyze and fix the rt-cause issue in a pr-quality TLM mdule in a cmplex virtual platfrm, ver-shadws the benefits that it can prvide, i.e. less time-t-market in develping end-level system level. II. TLM VERIFICATION CHALLENGES A standard SC develpment flw is primarily RTL->Gates->Silicn. TLM mdels can nw be added in this flw as equivalence t RTL, fr early design and verificatin f system level designs. Observing this flw carefully, it can be nticed that functinal verificatin has becme a bttleneck fr tday s virtual platfrms, due t a crrespnding increase in the cmplexity and size f a platfrm. This has led t mre effrts and timecnsumptin in the creatin f a rbust and cmprehensive TLM-driven verificatin flw. Since, a TLM mdel can be represented as an entry pint t the SC verificatin flw, an efficiently verified TLM mdel des nt nly mean much higher prductivity, but als the ability t explre and verify a greater number f different implementatins and ease in debugging, leading t high quality and better perfrmance f virtual platfrms. TLM mdels primarily cncentrate n three majr areas during a verificatin flw: prtcl cmpliance (fr which the TLM mdel is develped), functinality (with r withut the RTL design availability) and timings (with respect t RTL simulatin results). A generic TLM mdel, which is nt based n a specific RTL cnfiguratin, is primarily cncerned with prtcl cmpliance and functinality and less n timings. Similarly, a characterized TLM mdel, which is based n a specific RTL design cnfiguratin, needs t verify its functinality and timings and match them mre clsely with the respective RTL design, ther than prtcl cmpliance. The mst imprtant pint t nte here is that currently in market, there is n established standard TLM-driven verificatin flw, thereby causing each develper r verificatin engineer t develp his wn ad-hc techniques and flws t verify his TLM mdels, leading t huge methdlgy deviatins.

3 Besides, the need t verify, a) functinal crner cases, that results frm varius interacting mdels in a platfrm, and b) a number f hardware and sftware cnfiguratins with which the TLM-IP must be tested, calls fr thinking in a new directin, where a TLM mdel verificatin flw can be synchrnized and standardized with an RTL IP verificatin flw. This means, a set f standard requirements need t be addressed and met, fr verifying TLM IPs, similar t that f their crrespnding RTL IPs, t detect design errrs as sn as pssible. Fr a successful transitin frm TLM t RTL mdel usage, a dedicated TLM mdel verificatin envirnment is highly imprtant, such that: 1. It specifies clear verificatin gals, 2. Fllws standard prcesses f reaching these gals 3. The verificatin testbench fully cmplies with design/prtcl requirements 4. Cvers cmplete prtcl interface, all pssible untested functinalities and crner cases 5. Reaches fr unanticipated tests thrugh randm traffic, and 6. Is rbust, reusable, mdular, scalable and cnfigurable III. A SOLUTION: VERIFICATION IPS The UVM is an industry standard verificatin library and methdlgy develped by Accellera, develped mainly fr RTL design verificatin. It is primarily written in System Verilg, which is a unified language fr design and verificatin. It is effective fr designing advance testbenches fr bth RTL and Transactin level mdels, since it has features like cnstraint randmizatin fr stimulus generatin, functinal cverage, assertins, bject riented cnstructs (such as class, inheritance etc). Verificatin IPs based n UVM, prvide all sufficient cmpnents and features needed t verify SC designs. Highly qualified and extensively used Synpsys VIPs, hence supprt the fllwing: Supprt System Verilg based testbenches, including built-in methdlgy supprt fr UVM, VMM and OVM Mdular test-bench architecture that prvides: Prgrammable number f masters, slaves etc. Features t simplify test-bench develpment Prtcl and test cverage Rapid creatin f cmplex tests thrugh sequence library Cnstrained randm verificatin Errr injectin With such a vast scpe f verificatin thrugh UVM VIPs, a cmbined usage f bth TLM and UVM methdlgies, acrss bth SystemC and SystemVerilg is nw apparent, t leverage the advanced features f bth in an integrated envirnment. Lking at all the abve features, it is easy t cmprehend that the Universal Verificatin Methdlgy based Verificatin IPs prvide the cmplete slutin package fr the verificatin challenges fr TLM mdels. IV. THE PROPOSAL A cmplete UVM verificatin methdlgy cmprises f a UVM testbench that cntains the fllwing: UVM cmpnents (such as master/slave/intercnnect agents, drivers, mnitrs, sequencers etc.) A UVM envirnment that creates and cnnects the abve and A UVM test that becmes the start-pint f firing sequences, ding checks fr prtcl crrectness, recrding cverage, and hence ensuring verall quality f the IP.

Necessary wrappers are created, that encapsulate a cmbinatin f different VIP agents, using Synpsys virtual platfrm creatr tls.

4 We prpse a simplified and nvel apprach t verificatin f TLM mdels thrugh reusing and refining the abve UVM cmpnents. The creatin f TLM mdel verificatin flw is accmplished by reusing RTL verificatin infrastructure in the frm f VIP masters and slaves, and RTL tests in UVM and SystemVerilg. Necessary wrappers are created, that encapsulate a cmbinatin f different VIP agents, using Synpsys virtual platfrm creatr tls. These mdified System Verilg-UVM VIPs are integrated with SystemC-TLM IPs and then this hybrid platfrm is c-simulated. An bjective data with pre-defined/mdified VIP sequences are generated. Hence the simulatin gets cmprehensively verified using VIPs. This c-simulatin f UVM VIPs is pssible fr TLM IPs that supprts bth cycle-accurate interfaces, and TLM generic paylad interfaces. V. CASE STUDY As a case study, a generic cache cherent intercnnect (CCI) based n AMBA-ACE prtcl interface was taken as the required TLM DUT. The bjective was t verify this SystemC-TLM based CCI mdel, using UVM based verificatin IPs. Since, Synpsys UVM based Verificatin IPs, prvide structured test benches that are reusable and easily maintainable, the TLM CCI mdel culd be cmpletely verified fr a number f prepackaged traffic. Using these testbenches, a cmbinatin f VIP agents was created, that can serve as a master r slave, r a cmbinatin f all, fr verificatin f the TLM CCI mdel. Using advanced Synpsys tls, such as Platfrm Architect (PA-MCO), a cmbined platfrm is created and cnnected, using UVM VIPs and TLM IPs. Then, a set f UVM sequences in System Verilg, is tapped frm a VIP master, and is fired n t the required CCI mdel that acts as a DUT. The utput f the TLM intercnnect mdel is again tapped and is injected int the crrespnding VIP slave that acts as a screbard fr pass/fail verificatin f fired data sequences. Different cmbinatins f abve flw can be made where: Only VIP masters can be used, fr TLM slave mdel verificatin Only VIP slaves can be used, fr TLM master mdel verificatin A cmbinatin f VIP masters and slaves can be used, fr verificatin f a number f TLM mdels.

Necessary test-bench mdificatins t enable this cnnectin f a UVM-System Verilg wrld with a ttally different TLM-SystemC wrld, are generally nnintrusive using PA-MCO, and hence are independent f any

5 Necessary test-bench mdificatins t enable this cnnectin f a UVM-System Verilg wrld with a ttally different TLM-SystemC wrld, are generally nnintrusive using PA-MCO, and hence are independent f any third-party tls/libraries. Verificatin f expected traffic being fired frm a VIP nt the TLM intercnnect mdel and vice versa can be easily verified thrugh Synpsys debugging and analysis tls such as vpexplrer. This experiment resulted in Running variety f directed/randm tests Randmized cnstrained testing Rapid creatin f new cmplex tests Identifying untested/unanticipated bugs in CCI mdel AMBA-ACE prtcl cmpliance Unaligned, narrw traffic Issues regarding Make Unique, make Invalid etc. Hence, a number f untested and unanticipated bugs were identified and fixed in the cache cherent intercnnect that culd nt be caught using nn-standardized TLM SystemC based initiatrs/targets. Mrever, cmplete AMBA-ACE prtcl cmpliance was cvered using the same. Belw is a sample platfrm, created fr verificatin f a TLM IP, with cycle-accurate interface: A variant f the abve is als pssible. The UVM library nw als supprts TLM. The UVM methdlgy descriptin is being extended t shw hw TLM and RTL mdels can be cmbined in a cmprehensive regressin slutin. This can be achieved thrugh UVM Cnnect. The UVM Cnnect package builds n existing standards: SystemVerilg, SystemC and UVM, allwing TLM mdels in each language t cmmunicate with each ther. The package als includes an API that allws SystemC t interact with, and cntrl the executin f, UVM testbenches. The UVM Cnnect library, allws bject passing acrss System Verilg and SystemC wrlds using certain UVM Cnnect library functins. Belw is the prttype f a platfrm, created fr verificatin f a TLM IP, with TLM generic paylad interface, using UVM Cnnect feature:

VI. CONCLUSION Since the prcess f verificatin parallels the design creatin prcess fr an RTL IP, this unified verificatin flw has demnstrated a near seamless transitin between RTL design and

6 VI. CONCLUSION Since the prcess f verificatin parallels the design creatin prcess fr an RTL IP, this unified verificatin flw has demnstrated a near seamless transitin between RTL design and verificatin f virtual prttypes, that are develped using standard TLM methdlgies. It significantly takes advantage f verificatin industry standards f UVM, fr develping and reusing bigger, cmplex and randmized tests, thereby catching mre functinal bugs in TLM mdels. The TLM mdeled platfrm, hence verified using standard UVM interface, can help in meaningful develpment f newer RTL features f high quality and better RTL upgrades t higher versins, and will carry a lt f value prpsitin fr RTL designers wh can use these TLM mdels fr identifying earlier bugs. T summarize, this flw ensures Equivalence between TLM and respective RTL design Prductivity, as an existing prven methdlgy is re-used, that creates mdular and cmplex tests faster Efficiency as a standard and cmprehensive verificatin methdlgy is used REFERENCES/ACKNOWLEDGEMENTS [1] Sandeep Kumar, Synpsys [2] [3]

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