An Overview of Test at IBM Microelectronics

Size: px

Start display at page:

Download "An Overview of Test at IBM Microelectronics"

Rafe Kelly
5 years ago
Views:

1 IBM Systems and Technlgy Grup An Overview f Test at IBM Micrelectrnics Harry Linzer Dec 1, 2005 Overview f Test IBM Systems and Technlgy Grup Agenda IBM as a Chip Maker Challenges f Test Test Methdlgy Overview LSSD OPMISR OPMISR + Illinis Test Macr Islatin Hw custmers implement test methdlgy 2

2 IBM Systems and Technlgy Grup IBM as a Chip Maker IBM has been prducing chips fr internal cnsumptin since the mid-1960 s in supprt f the IBM System/360 Mainframe Currently apprximately 20% internal use / 80% fr thers OEM ASICs vendr since mid 1990 s Currently releasing designs / year Fcus Areas: Netwrking Cnsumer Prducts Digital Cameras Vide Games OEM business prvides ecnmies f scale t supprt fabs and develpment fr internal cnsumptin 3 IBM Systems and Technlgy Grup IBM as a Chip Maker Fabs East Fishkill, New Yrk State f the art 300 mm wafer facility 130 nm, 90 nm, 65 nm, 45 nm (planned) Burlingtn, Vermnt Previus Generatin 200 mm wafer facility 250 nm, 180 nm, 130 nm Supprt Engineers Prcess Develpment Main lab in East Fishkill, New Yrk Design Supprt, 5 lcatins in Nrth America, additinal WW lcatins Apprx 500 Engineers Wrld Wide Tls Mixture f Internally Develped, Partner and Third Party Tls 4

3 IBM Systems and Technlgy Grup IBM as a Chip Maker Typical Chip 12 mm x 12 mm (range is frm 5 t 18 mm) 5 15 millin gates 700 I/O Pins (can be as many as 2500) 4 Mbit f SRAM Capability fr up t 32 Mbit f DRAM Multiple Types f Hard IP Blcks PLL s, High Speed SERDES (-> 12 Gbit/Sec), Micrprcessrs, CAM s 5 IBM Systems and Technlgy Grup Challenges f Test Custmers are Very Demanding Few custmers will accept mre than 1000 bad parts / millin shipped Sme expect less than 100 / millin 99.5 % DC Stuck / 95% Transitin Fault Cverage nt always gd enugh Chips are getting large and very cmplex 15 Millin Gates is NOT UNUSUAL 50 millin is in sight Mixture f differing type f Mixed Signal and Hard IP Fr 180 nm and less, DC Stuck at Fault testing nt ttally satisfactry. Must be supplemented by Transitin Testing t meet custmer expectatins At sub 130 nm, demand fr At Speed Testing is cmmn Test is OVERHEAD Less Test Cst = Greater Prfit Minimize Tester Time Leverage Older / Cheaper Testers 6

4 IBM Systems and Technlgy Grup Test Methdlgy Full Scan 100% ATPG Based Typically 99.5% DC Stuck at Fault Cverage achieved Mixture f Target Patterns Weighted Randm Pattern Testing AC Transitin Fault Cverage varies N Cst Optin 50-60% cverage is typical Premium - 90%+ achievable Reduced Pin Cunt Testing Allws use f Lw Cst Testers (current wrkhrse Advantest 6670) 64 High Speed Channels (->125 MHz) 64 Lw Speed Channels (-> 1 KHz) 128 VDD/GND Channnels 7 IBM Systems and Technlgy Grup Test Methdlgy Test I/O (Mst are shared with functinal pins) Scan Chains ABIST Nn-Test I/O scan latch pairs Embedded Array Register Array Nn-Test I/O PLL Lgic 8

5 IBM Systems and Technlgy Grup Test Methdlgy LSSD Level Sensitive Scan Design Develped in late 1960 s at IBM First majr use f Full Scan Test Race Free n designs with multiple clck dmains Supprts Structure based ATPG with simple straightfrward testers IBM Challenge: Make it trivial t use n mst designs Slutin IBM / Cadence DFT tl 9 IBM Systems and Technlgy Grup Test Methdlgy Cnventinal MUX Scan What happens if Clck #2 is smewhat later than Clck #1??? 10

6 IBM Systems and Technlgy Grup Test Methdlgy Flip Flp Implementatin Master Latch Slave Latch Clck Overhead 11 IBM Systems and Technlgy Grup Test Methdlgy LSSD Implementatin Independent Test Clcks Mre Cmplex Clck Overhead (Clck Splitter) Better Cntrl During Test Shared amng several flps 12

7 IBM Systems and Technlgy Grup Test Methdlgy Future Mux Scan / LSSD Hybrid Mre Cmmnality with Industry Less switching when signals are functinal Less Switching during Test Adds new functin Better AC Test Mst f LSSD Advantage (Race Free) Lses Little (Ability t Scan Flush) 13 IBM Systems and Technlgy Grup Test Methdlgy Prblem Scan test time fr latest chips takes t lng Tester Capacity Tester Operatinal Cst Tester Time slws prductin line Slutins Mve Mre data thrugh less pins OPMISR OPMISR + Illinis Test 14

8 IBM Systems and Technlgy Grup Test Methdlgy Scan t OPMISR Intrduced with 130 nm chips OPMISR = On Prduct Multiple Input Signature Register Eliminates need fr Scan Out pins Dubles number f Scan Chains / Halves Tester Time Signature read ut and cmpared against knwn gd value at end f test cycle 15 IBM Systems and Technlgy Grup Test Methdlgy Befre Scan t OPMISR 6 I/O s 3 Scan Chains 16

9 IBM Systems and Technlgy Grup Test Methdlgy After Scan t OPMISR 6 I/O s 6 Scan Chains Signature Register 17 IBM Systems and Technlgy Grup Test Methdlgy Illinis Scan + Scan t MISR Intrduced in 90 nm technlgy Observatin: High Percentage f bits in Scan Chain are Dn t Cares Scan Multiple Scan Chains frm ne input lining up Dn t Cares 18

10 IBM Systems and Technlgy Grup Test Methdlgy Illinis Scan + OPMISR Empirical Observatins 10:1 Rati f Scan In is ptimal fr mst designs Nrmally Yields 8:1 test prductivity imprvement Negative What happens if incnvenient bits just happen t line up Typically happens in a places / chip Slutin Supplement with limited amunt full scan testing ATPG time increases by 50% Wh cares Yu nly d it nce / chip!!! IBM is leading maker f UNIX Server Bxes 19 IBM Systems and Technlgy Grup Test Methdlgy Hard IP / Mixed Signal Macr Islatin Strategy Selected signals must have path t chip pins Other prts must be cntrllable r bservable via scan latches 20

11 IBM Systems and Technlgy Grup Test Methdlgy Implementatin I/O Padring cmpiled t custmer spec by tl Custmer lgic cntains Flps + Gates Hard IP wrapped t hide test issues Test Insertin dne with DFT Synthesis tl Verificatin f ATPG Design Rule cnfrmance dne my tl Full Scan Macr Islatin I/O Bundary Testing 21

The. ARM Architecture. Thomas DeMeo Thomas Becker

The. ARM Architecture. Thomas DeMeo Thomas Becker The ARM Architecture Thmas DeMe Thmas Becker Agenda What is ARM? ARM Histry ARM Design Objectives ARM Architectures What is the ARM Architecture? Advanced RISC Machines ARM is a 32-bit RISC ISA Mst ppular