A concept for expanding a UVM testbench to the analog-centric toplevel

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1 A cncept fr expanding a UVM testbench t the analg-centric tplevel Felix Assmann, Bsch Sensrtec, Dresden, Germany (Felix.Assmann@bsch-sensrtec.cm) Axel Strbel, Bsch Sensrtec, Dresden, Germany (Axel.Strbel@bsch-sensrtec.cm) Hans Zander, Cadence Design Systems, Feldkirchen, Germany (hans@cadence.cm) Abstract - This paper utlines a new apprach t imprve the prductivity in mixed-signal verificatin by addressing bth analg and digital verificatin requirements in ne testbench. The UVM verificatin envirnment which was used n the digital prtin f the design was enhanced t address the needs f the analg verificatin as well as the full chip level verificatin. The paper describes the cncept, the actual architecture, and the implementatin f the new UVMmixed-signal testbench fllwed by sme use case examples and the results and experience made with the new apprach. Keywrds UVM; MDV; mixed-signal; wreal; testbench-reuse; whitebx; blackbx I. INTRODUCTION Typical mixed signal designs cntain a digital and an analg prtin. While in general the cmplexity f ur chips especially f the digital part is grwing, the designs are still analg centric. The verificatin f these mixed-signal designs has always been challenging as there was n cmmn apprach fr digital and analg verificatin. There are already existing appraches t deal with analg centric designs with real number mdeling [1, 2]. But especially with the intrductin f advanced verificatin methdlgies, there is an even bigger gap between the digital verificatin which is based n metric-driven verificatin (MDV) and the Universal Verificatin Methdlgy (UVM) and the analg verificatin which is rather directed and use case riented, with manual inspectin using a wavefrm. The grwing cmplexity f the designs als has an impact n the simulatin perfrmance and the verificatin thrughput. Especially with the increased number f simulatins due t the randmness f the UVM testbench it is nt feasible anymre t run all regressin tests at the full chip level. Hwever, the verificatin f the full chip is mandatry t identify bugs in the analg/digital interface, which can nly be fund n tplevel, as well as full chip behavir. Tday cmmn appraches distinguish between analg and digital verificatin n tplevel [3, 4]. Such that the verificatin cannt benefit frm analg designers knwledge f the analg part. While it is nt realistic t prt the ways f wrking frm digital t analg and visa-verse, a new cncept needs t be fund. It shuld meet the requirements f fast simulatins with apprpriate accuracy and shuld still enable different flws f verificatin in rder t leave bth dmain experts in their cmfrt znes. II. CHALLENGES Even thugh we have already been using wreal mdels t be able t increase the simulatin perfrmance, the verificatin cncept was nt aligned yet. The verificatin activities f the analg and the digital team were quite discnnected and based n the usage f tw different testbenches: A. UVM based testbench alng with wreal mdels Used fr digital nly simulatins and full chip simulatins using wreal mdels Nt cmpatible with transistr level simulatins B. TCL based testbench alng with analg schematics Used fr scenaris which required full precisin (e.g. pwer-up, pwer mde transitins, functinality with strng interactins between digital and analg) N autmatic checks available 1

2 Heavily used because UVM envirnment was ften under cnstructin and was thus smetimes blcking (e.g. due t cmpilatin errrs) the verificatin prgress n the analg side Maintaining these tw testbenches required a lt f effrt. The hardest part was t always ensure that the behavir f bth testbenches was cnsistent. We bserved different behavir f the wreal mdels based n simulatin parameters, fr example delay_mde_zer tgether with delayed assignments: assign #3 a = b; (1) Equatin (1) des nt delay the signal assignment, but wreal mdels relied n this kind f structure fr e.g. enable delay mdeling f analg blcks. Smetimes it tk a huge amunt f time and lng debug cycles t identify such issues. Finally, the scripting envirnment was nt flexible enugh. In the analg dmain the functinality f a cnfig view is heavily used. It allws a substitutin f schematic level with a wreal mdel and vice versa inside f the same testbench. The ld apprach did nt easily allw t use the UVM envirnment with any specific analg cnfig view. As a cnsequence, there was just ne wrking cnfiguratin which used wreal mdels nly tgether with the UVM envirnment. It was very hard t replace selected wreal mdels with real schematics which culd have imprved the develpment f analg mdules inside tplevel cntext. Just changing simulatin scripts culd nt slve the prblem f missing encapsulatin and cnfigurability. The challenges stated abve had a big impact n the verificatin prductivity and brught a high risk fr critical bugs t escape. In rder t vercme these challenges, we develped a cncept fr expanding the UVM testbench als t the analg-centric tplevel. III. CONCEPT T address the simulatin perfrmance we used the already prven apprach f creating abstract wreal mdels fr the analg circuits. T serve the verall cncept, this time it was required t create several mdels fr the analg blcks, all with different abstractin levels. As als third party mdels were used, sme f them had t be remdeled r enhanced t prvide either higher precisin r higher perfrmance with reduced precisin. In general we needed at least tw mdels f each blck with different accuracy. Fr example a supply ramp nly needs t be accurate enugh t trigger pwer-n reset threshlds prperly fr digital verificatin The assciated questin f verifying the functinal equivalence f the mdel and the circuit will nt be discussed here. Creating a cmmn and cnfigurable testbench was the mre challenging task. As stated abve, it is nt feasible r even desired t fully prt the verificatin methdlgies and tls frm the digital/analg wrld t the ther. The main fcus was t create a cmmn testbench which allwed bth digital and analg verificatin withut any unnecessary dependencies. A. Partitining f the UVM verificatin envirnment Fr the digital part we used a bttm up apprach using UVM envirnments n blck level, reusing them up t the full digital tplevel. Having mixed-signal verificatin in mind, tw derivatives f the tplevel verificatin envirnment were required: BlackBx envirnment Used fr testcase develpment and tplevel develpment (analg and digital) Always wrking, cntains nly interface cmpnents (interface UVCs) Only functinalities which an external master wuld execute frm the chip bundary were integrated Des nt cntain any checking cmpnents Used by analg designers and verificatin engineers fr directed tests with wavefrm analysis Interactive cmmand interface t e.g. prgram registers r stimulate pins via generic pin drivers Checks are specified inside f testcases r as part f the interface UVCs 2

3 Als used fr gate level verificatin WhiteBx envirnment Used fr regressin Cntains all blck level UVCs (internal passive UVCs, SBs, internal checkers, etc.) Imprts BlackBx envirnment fr mdular reuse Used mainly by verificatin engineers All tests frm the BlackBx can be run in the WhiteBx Usable fr digital part as RTL descriptin nly B. Digital verificatin All BlackBx features (e.g. interactive mde) are usable Classical UVM/MDV apprach including interactins with analg part via wreal mdel C. Analg verificatin The verificatin f the analg blcks was dne by each analg designer in the way described in the intrductin. Once verified they were cntributed t the tplevel envirnment. In additin t that, the new testbench cncept allws the adptin f full custm lgic fr analg mdules within the tplevel design. Because cntrl signals and methds t drive them are already in place (e.g. just set a register via the interactive cmmand interface), the analg designer can fcus n the develpment f his/her mdule. With the new setup there is n need t create a stimulus mdel (which culd be different fr each analg blck). T further enhance the checking f the analg part (e.g. trimming, ffsets) and t be able t mdel impurities f the analg blcks, cnfigurable wreal mdels were added. They can be cnfigured during run-time via an active UVC which drives and reads a parameter file (cds_glbals) fr the analg wreal mdels (see Figure 1). Furthermre this gives us the pprtunity t add randmness t the analg part. D. Tp level verificatin The tplevel testbench cntains either the WhiteBx r the BlackBx verificatin envirnment. Fr analg verificatin the BlackBx envirnment is chsen fr interactive debugging and develpment. Fr regressin verificatin, mainly the WhiteBx envirnment was used tgether with tests which were develped in the BlackBx envirnment. It is als pssible t use the BlackBx envirnment as part f the regressin (e.g. gatelevel verificatin), but then the tests need t cntain the checks. T be able t als drive the analg prts, generic pin drivers were gruped under a s called stim-cre. The stim-cre represents the interface f a virtual master and is driven by an active UVC (e.g. SPI-VIP) frm the UVM verificatin envirnment. The full testbench architecture is illustrated in see Figure 1. A cmmand interface was created t als enable the analg designers t cntrl the UVM verificatin envirnment during simulatin (e.g. register writes). Only the given cmmand is executed and simulated, which gives the designers full interactive capabilities. IV. ARCHITECTURE & CONFIGURATIONS T be independent f the signal representatins (lgic signals n digital, any analg prt representatin analg, etc.) a generic pin driver cmpnent was created. Pin driver mdules replace the previusly used simple cnnect mdules which were nt functinal fr analg simulatins because f the digital utputs, missing pull-ups, and slew rate settings. The new apprach mdels the functinality f master device pad stages (the testbench mdels the reality in the sense f master slave cmmunicatin). Furthermre the mdels were extended by a clck generatr t allw a simulatin efficient methd t apply test clcks t any ASIC pin, e.g. t simulate scanmde. The architecture f a generic pin driver mdule is illustrated in Figure 2. 3

Figure 1. Full testbench architecture Driving scenaris: A_tx_lgic fr the digital value Dig_ut_en t enable digital driver A_ana fr supplys Ana_ut_en t enable analg driver Ana_slew fr supply ramps A.

Fr example all digital centric cnfiguratins nly use the digital simulatr t be faster. But there are als cnfiguratins which use the analg slver if the precisin is needed.

4 Figure 1. Full testbench architecture Driving scenaris: A_tx_lgic fr the digital value Dig_ut_en t enable digital driver A_ana fr supplys Ana_ut_en t enable analg driver Ana_slew fr supply ramps A. Cnfiguratin & Usage examples Figure 2. Architecture f a generic pin-driver The TB is used in different regressin cnfiguratins. Each cnfiguratin serves a specific purpse. Fr example all digital centric cnfiguratins nly use the digital simulatr t be faster. But there are als cnfiguratins which use the analg slver if the precisin is needed. Belw are sme cnfiguratin examples: Digital cnfig A DUT cnfiguratin All analg mdules as wreal mdels (high precisin mdels) All digital mdules as RTL Scenaris Pwer up sequence All test with interactin t external system cmpnents System level test sequences Digital cnfig B 4

5 DUT cnfiguratin All analg mdules as wreal mdels (lw precisin mdels) All digital mdules as RTL Simple third party / IP blck wreal mdels Scenaris Lng running sequences Sequences with fcus n the digital side Analg cnfig A DUT cnfiguratin All analg mdules n transistr level All digital mdules as RTL Scenaris Basic functinality tests Analg cnfig B Pwer-up sequence tests Analg/digital signal checks (enable and reset plarity, current directin) DUT cnfiguratin Sme analg mdules n transistr level Pads and pwer mdules n schematic level Rest wreal All digital mdules as RTL Scenaris Pwer mde transitins All cnfiguratins supprt bth BlackBx and WhiteBx testbenches and can be run in full regressin setup. V. EXPERIENCE & RESULTS The new cncept prvides significant imprvements in many aspects. It clearly increased the verificatin prductivity: A. Only ne tplevel testbench Only ne envirnment t maintain N mre incnsistencies Partitining f UVM envirnment int BlackBx and WhiteBx allws independent and parallel wrk mde fr analg centric and digital centric verificatin B. Efficient testcase creatin Analg designers can d full schematic verificatin in cmbinatin with existing testcases, n rewriting needed Directed testcase frm analg r digital tplevel bring-up is used as base test fr MDV. Only sme randmness had t be added 5

6 Analg testcases can nw be easily integrated in the regressin as they are based n the UVM envirnment (They nly have t be self-checking) Single testcase setup and debug abut 5x faster due t simulatin time enhancements frm mdel cnfiguratin C. Efficient analg cmpnent adjustment Analg designers can easily verify the interactin f the analg circuits tgether with the real digital input stimuli. Previusly many hacks had t be dne t get this wrking (with limitatins) D. Increased verificatin prductivity Previusly the verificatin cverage was limited by lng simulatin times and TB maintenance issues (wait until change was fixed everywhere) Different cnfig views allw different cnfiguratin fr fast, accurate r ther simulatins Simulatin time speedup because f different cnfig views Pwer up cycle: 10s in digital cnfig B vs. 5min in digital cnfig A A lt f interactins between digital and analg (e.g. cntrl lps) are nw simulatable in a reasnable timeframe Fast simulatin pssible due t wreal mdels Lts f tests pssible due t randm UVM envirnment Pssibility t verify single wreal mdels in tplevel cntext with tplevel/real stimuli VI. SUMMARY The new cncept was successfully applied n ur current prject. It prved t increase ur verificatin prductivity dramatically. Als the verificatin cverage increased in all aspects, fcusing n functinalities which culd nt be verified easily in the past. Overall the new cncept imprved the quality f the prduct. New prjects will certainly apply this cncept, where sme enhancements are planned already: A. Mdel checks inside f regressin Cmpare schematic and wreal mdel in regressin (due t missing equivalence checking) The checking part is still under discussin B. Enhance interactive mde fr mre granular usage, e.g. cntrl f single register fields VII. REFERENCES [1] Ira Miller, Ana Ferreira-Nullet, Behaviral Mdeling in Industrial IC Design Experiences and Observatins, BMAS, [2] Jnes,K., Analg and mixed signal verificatin, FMCAD, [3] Mixed-Signal System-n-a-Chip (SC) Verificatin Based n SystemVerilg Mdel, 45th Sutheastern Sympsium n System Thery Baylr University, [4] Cha Liang, Mixed-Signal Verificatin Methds fr Multi-Pwer Mixed-Signal System-n-Chip (SC) Design, ASICON,

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