User Visible Registers. CPU Structure and Function Ch 11. General CPU Organization (4) Control and Status Registers (5) Register Organisation (4)

Transcription

1 PU Stuctue and Function h Geneal Oganisation Registes Instuction ycle Pipelining anch Pediction Inteupts Use Visible Registes Vaies fom one achitectue to anothe Geneal pupose egiste (GPR) ata, addess, index, P, condition,. ata egiste Int, FP, ouble, Index Addess egiste Segment and stac pointes only pivileged instuction can wite? ondition codes esult of some pevious ALU opeation 4 Geneal PU Oganization (4) ALU does all eal wo Registes data stoed hee Intenal PU us ontol Moe in haptes 4-5 detemines who does what when diven by cloc uses contol signals (wies) to contol what evey cicuit is doing at any given cloc cycle Fig.. Fig..2 2 ontol and Status Registes (5) P next instuction (not cuent!) pat of pocess state IR, Instuction (ecoding) Registe cuent instuction MAR, Memoy Addess Registe cuent memoy addess MR, Memoy uffe Registe cuent data to/fom memoy PSW, Pogam Status Wod what is allowed? What is going on? pat of pocess state Fig..7 5 Registe Oganisation (4) Registes mae up PU wo space Use visible egistes accessible diectly via instuctions ontol and status egistes may be accessible indiectly via instuctions may be accessible only intenally Intenal latches fo tempoay stoage duing instuction execution E.g., ALU opeand eithe fom constant in instuction o fom machine egiste A R,R2,R3 Neq Loop HW exception 3 PSW - Pogam Status Wod (6) State info fom latest ALU-op Sign, zeo? ay (fo multiwod ALU ops)? Oveflow? Inteupts that ae enabled/disabled? Pending inteupts? PU execution mode (supeviso, use)? Stac pointe, page table pointe? I/O egistes? 6 hapte, PU Stuctue and Function

2 Instuction ycle (4) asic cycle with inteupt handling Indiect cycle Figs.5-6 ata Flow Figs.7-9 PU, us, Memoy ata Path PU s intenal data bus o data mesh All computation is data tansfomations occuing on the data path ontol signals detemine data flow & action fo each cloc cycle Fig..4 Fig a s O d e Pipelined Laundy () A 6 PM fo one load Latency 90 minutes pe load.5 loads pe hou houghput Aveage speed Max speed?.5 load pe hou Pipelined laundy taes 3.5 hous fo 4 loads At best case, laundy is completed evey 40 minutes 0 Pipeline Example Laundy Example (avid A. Patteson) Ann, ian, athy, ave each have one load of clothes A to wash, dy, and fold Washe taes 30 minutes ye taes 40 minutes Folde taes 20 minutes (liuuhihna) Pipelining Lessons (4) Pipelining doesn t help latency of single tas, but it helps thoughput of the entie woload A Pipeline ate limited by slowest pipeline stage Multiple tass opeating simultaneously Potential speedup = maximum possible speedup = Numbe pipe stages 6 PM (nopeutus) 8 a s O d e A Sequential Laundy (6) 6 PM fo one load (viive?) Latency.5 hous pe load Sequential laundy taes 6 hous fo 4 loads If they leaned pipelining, how long would laundy tae? houghput Midnight 0.67 loads pe hou 9 Pipelining Lessons (3) Unbalanced lengths of pipe stages educes speedup May need moe esouces Enough electical cuent to un both washe and dye simultaneously? Need to have at least 2 people pesent all the time? to fill pipeline and time to dain it educes speedup 6 PM A fill dain 2 hapte, PU Stuctue and Function 2

3 2-stage Instuction Execution Pipeline (4) Fig..0 Good: instuction pe-fetch at the same time as execution of pevious instuction ad: execution phase is longe, I.e., fetch stage is sometimes idle ad: Sometimes (jump, banch) wong instuction is fetched evey 6 th instuction? Not enough paallelism moe stages? Pipeline Execution (3) to execute one instuction (latency, seconds) may be longe than fo non-pipelined machine exta latches to stoe intemediate esults to execute 000 instuctions (seconds) is shote (bette) than that fo non-pipelined machine, I.e., houghput (instuctions pe second) fo pipelined machine is bette (bigge) than that fo non-pipelined machine Is this good o bad? Why? 3 6 Anothe Possible Instuction Execution Pipeline FE -Fetch instuction I -ecode instuction O -alculate opeand effective addesses FO -Fetch opeands fom memoy EI -Execute Instuction WO -Wite opeand (esult) to memoy Fig.. Pipeline Speedup Poblems Some stages ae shote than the othes ependencies between instuctions contol dependency E.g., conditional banch decision now only afte EI stage Fig..2 Fig Pipeline Speedup (3) No pipeline, 9 instuctions Not evey instuction uses evey stage seial execution actually even faste speedup even smalle will not affect pipeline speed unused stage PU idle (execution bubble ) 54 time units Fig.. 6 stage pipeline, 9 instuctions 4 time units Speedup = 9 * 6 old new = 54/4 = 3.86 < 6! (nopeutus) 5 Pipeline Speedup Poblems ependencies between instuctions data dependency One instuction depends on data poduced by some ealie instuction stuctual dependency Many instuctions need the same esouce at the same time memoy bus, ALU, Fig..2 Known afte EI stage MUL R,R2,R3 LOA R6,A(R) Needed in O stage WO SORE R,VaX A R2,R3,VaY MUL R3,R4,R5 FI FO 8 hapte, PU Stuctue and Function 3

4 ycle [ ] + d = + d d τ = max τ τ ovehead? i m >> max gate delay in stage (min) cycle time delay in latches between stages (= cloc pulse, o cloc cycle time) gate delay in stage i ycle time is the same fo all stages time (in cloc pulses) to execute the cycle Each stage executed in one cycle time Longest stage detemines min cycle time max MHz ate fo system cloc anch Poblem Solutions (5) elayed anch compile places some useful instuctions ( o moe!) afte banch (o jump) instuctions these instuctions ae almost completely executed when banch decision is nown less actual wo lost Fig. 2.7 can be difficult to do 9 22 Pipeline Speedup n instuctions, stages not pipelined: = nτ = [ + ( n ) ]τ pipelined: cycles until st instuction completes n instuctions, stages τ = stage delay = cycle time (pessimistic because of assuming that each stage would still have τ cycle time) cycle fo each of the est (n-) instuctions anch Pobl. Solutions (contd) (6) Multiple instuction steams execute speculatively in both diections Poblem: we do not now the banch taget addess ealy! if one diection splits, continue each way again lots of hadwae speculative esults (egistes!), contol speculative instuctions may delay eal wo bus & egiste contention? need to be able to cancel not-taen instuction steams in pipeline Pipeline Speedup () n instuctions, stages not pipelined: = nτ = [ + ( n ) ]τ pipelined: Speedup with stages: S Fig..4 = = n instuctions, stages τ = stage delay = cycle time (pessimistic because of assuming that each stage would still have τ cycle time) nτ = n [ + ( n ) ] τ [ + ( n ) ] anch Pobl. Solutions (contd) (2) Pefetch anch aget IM 360/9 (967) pefetch just banch taget instuction do not execute it, I.e., do only FI stage if banch tae, no need to wait fo memoy Loop uffe eep n most ecently fetched instuctions in high speed buffe inside PU wos fo small loops (at most n instuctions) 2 24 hapte, PU Stuctue and Function 4

5 anch Pobl. Solutions (contd) (5) anch Pediction guess (intelligently) which way banch will go static pediction: all taen o all not taen static pediction based on opcode E.g., because LE instuction is usually at the end of loop, guess taen dynamic pediction taen/not taen based on pevious time this instuction was executed need space ( bit) in PU fo each (?) banch end of loop always wong twice! extension based on two pevious time execution need moe space (2 bits) Fig PU Example: PoweP Use Visible Registes 32 geneal pupose egs, each 64 bits Exception eg (XER), 32 bits 32 FP egs, each 64 bits FP status & contol (FPSR), 32 bits banch pocessing unit egistes ondition, 32 bits 8 fields, each 4 bits identity given in instuctions Lin eg, 64 bits E.g., etun addess ount egs, 64 bits E.g., loop counte Fig..22 Fig..23a able.3 Fig..23b able.4 28 anch Addess Pediction (3) It is not enough to now whethe banch is taen o not Must now also banch addess to fetch taget instuction anch Histoy able state infomation to guess whethe banch will be taen o not pevious banch taget addess stoed in PU fo each (?) banch PU Example: PoweP Inteupts cause system condition o event instuction able anch Histoy able ached PoweP 620 enties only fo most ecent banches anch instuction addess, o tag bits fo it anch taen pediction bits (2?) aget addess (fom pevious time) o complete taget instuction? Why cached expensive hadwae, not enough space fo all possible banches at looup time chec fist whethe enty fo coect banch instuction PU Example: PoweP Machine State Registe, 64 bits able.6 bit 48: extenal (I/O) inteupts enabled? bit 49: pivileged state o not bits 52&55: which FP inteupts enabled? bit 59: data addess tanslation on/off bit 63: big/little endian mode Save/Restoe Regs SRR0 and SRR tempoay data needed fo inteupt handling hapte, PU Stuctue and Function 5

6 Powe P Inteupt Invocation Save etun P to SRR0 able.6 cuent o next instuction at the time of inteupt opy elevant aeas of MSR to SRR opy additional inteupt info to SRR opy fixed new value into MSR diffeent fo each inteupt addess tanslation off, disable inteupts opy inteupt handle enty point to P two possible handles, selection based on bit 57 of oiginal MSR 3 Powe P Inteupt Retun Retun Fom Inteupt (fi) instuction able.6 pivileged Rebuild oiginal MSR fom SRR opy etun addess fom SRR0 to P End of hapte : PU Stuctue -- 5 stage pipelined vesion of datapath (Fig. 6.2) (Patteson-Hennessy, ompute Og & esign, 2nd Ed, 998) 33 hapte, PU Stuctue and Function 6