Chapter 4 (Part III) The Processor: Datapath and Control (Pipeline Hazards)

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1 Chapte 4 (Pat III) The Pocesso: Datapath and Contol (Pipeline Hazads) 陳瑞奇 (J.C. Chen) 亞洲大學資訊工程學系 Adapted fom class notes by Pof. M.J. Iwin, PSU and Pof. D. Patteson, UCB 1 吃感冒藥副作用怎麼辦? 2

2 4.7 Can Pipelining ( 效能提高 ) Get Us Into Touble? p.291( 頁 302) Yes: Pipeline Hazads ( 副作用 ) stuctual hazads: attempt to use the same esouce by two diffeent instuctions at the same time data hazads: attempt to use data befoe it is eady An instuction s souce opeand(s) ae poduced by a pio instuction still in the pipeline contol hazads: attempt to make a decision about pogam contol flow befoe the condition has been evaluated and the new PC taget addess calculated banch instuctions Can always esolve hazads by waiting (stall) (bubble) pipeline contol must detect the hazads and take action to esolve hazads 3 A Single Memoy Would Be a Stuctual Hazad Time (clock cycles) I n s t. O d e lw Inst 1 Inst 2 Inst 3 Mem Reg Mem Reg Mem Reg Mem Reg Mem Reg Mem Reg Reading data fom memoy Mem Reg Mem Reg Inst 4 Reading instuction fom memoy Mem Reg Mem Reg Fix with sepaate inst and data memoies (IM and DM) 4

3 How About Registe File Access? Time (clock cycles) Stuctual Hazad! I n s t. O d e add $1, Inst 1 Inst 2 add $2,$1, Data dependency Witing data into egiste file Reading data fom egiste file 5 The fifth pipe stage (WB) of an instuction (Wite back) MEM Wite IF wite Stuctual Hazad! W 6

4 How About Registe File Access? Time (clock cycles) I n s t. O d e add $1, Inst 1 Inst 2 add $2,$1, W R W Fix egiste file access hazad by doing eads in the second half of the cycle and wites in the fist half clock edge that contols egiste witing clock edge that contols loading of pipeline state egistes Registe Usage Can Cause Data Hazads Data Dependencies backwad in time cause hazads (RAW, WAR, WAW, RAR) add $1, W R R sub $4,$1,$5 and $5,$1,$6 o $7,$1,$8 xo $7,$1,$9 Read afte wite (RAW; 寫後讀 ): data hazad R R W R R 8

5 Pipelined dependences p.293( 頁 304) Fig Poblem with stating next instuction befoe fist is finished l dependencies that point backwad in time ae data hazads 10 One Way to Fix a Data Hazad add $1, stall stall W Can fix data hazad by waiting stall but impacts CPI (Bubbles) sub $4,$1,$5 and $6,$1,$7 o $7,$1,$8 xo $7,$1,$9 R R IM Reg DM R 12

6 Softwae Solution Have compile guaantee no hazads Whee do we inset the nops?? sub $2, $1, $3 and $12, $2, $5 o $13, $6, $2 add $14, $2, $2 sw $15, 100($2) Inset NOP sub $2, $1, $3 NOP NOP and $12, $2, $5 o $13, $6, $2 add $14, $2, $2 sw $15, 100($2) 空包彈 # NOP = sll $0, $0, 0 = Poblem: this eally slows us down! 13 Anothe Way to Fix a Data Hazad I n s t. O d e add $1, sub $4,$1,$5 and $6,$1,$7 o $8,$1,$9 Fix data hazads by fowading (bypassing) esults as soon as they ae available to whee they ae needed xo $4,$1,$5 14

7 Fowading with Read befoe wite Data Hazads Fowading Feedback (Need Mux) p.267( 頁 277) Fig No fowading datapath p. 297( 頁 307) Fig top 17

8 With fowading datapath Instuction Fomats: all 32 bits wide OP s t d sa funct OP s t immediate p. 297( 頁 307) Fig R fomat I fomat 18 The datapath modified to esolve hazads via fowading p. 299( 頁 310) Fig EX/MEM.RegWite MEM/WB.RegWite FowadA FowadB 20

9 Fowading Illustation I n s t. add $1, sub $4,$1,$5 O d e and $6,$7,$1 EX/MEM hazad fowading MEM/WB hazad fowading 22 Yet Anothe Complication! Anothe potential data hazad can occu when thee is a conflict between the esult of the WB stage instuction and the MEM stage instuction which should be fowaded? I n s t. O d e add $1,$1,$2 add $1,$1,$3 add $1,$1,$4 23

10 超市買鮮奶 ( 有效日期 ) sign 32 ext. 32 immediate Fig p. 300( 頁 311) 30

11 Instuction Flushing fo Banch p. 304( 頁 320) Fig top Memoy-to-Memoy Copies Fo loads immediately followed by stoes (memoy-tomemoy copies) can avoid a stall by adding fowading hadwae fom the MEM/WB egiste to the data memoy input. l Would need to add a Fowad Unit and a mux to the memoy access stage I n s t. O d e lw $1,4($2) sw $1,4($3) 32

12 With fowading datapath ID/EX.RegisteRt 3 Instuction Fomats: all 32 bits wide OP OP s t d sa funct s t immediate MEM/WB.RegisteRd EX/MEM.MemWite = 1? MEM/WB.MemRead = 1? R EX/MEM.Rt=MEM/WB.RegisteRd fomat? I p. fomat 297( 頁 307) Fig Fowading with Load-use Data Hazads I n s t. O d e lw $1,4($2) sub $4,$1,$5 and $6,$1,$7 o $8,$1,$9 Fowading xo $4,$1,$5 Will still need one stall cycle even with fowading 34

13 Fowading with Load-use Data Hazads Can t always avoid stalls by fowading l If value not computed when needed l Can t fowad backwad in time! Fowading Stall nop p.267( 頁 277) Fig Data hazads and Stall p. 301( 頁 312) Fig Load wod can still cause a hazad! 38

14 PC.Wite IF/ID.Wite Data hazads and Stall p. 303( 頁 314) Fig Fowading nop 39 Datapath with Hazad Detection p.304( 頁 315) Fig Stall by letting an instuction that won t wite anything go fowad stall 0 s t ID/EX.MemRead (load instuction) Inset NOP LOAD continues to next stage 0 00 ID/EX.RegisteRt 42

15 Stalls and Pefomance Stalls educe pefomance The BIG Pictue But ae equied to get coect esults Compile can aange code to avoid hazads and stalls Requies knowledge of the pipeline stuctue Ty and avoid stalls! E.g., eode these instuctions: lw $t0, 0($t1) lw $t2, 4($t1) sw $t2, 0($t1) sw $t0, 4($t1) lw $t0, 0($t1) lw $t2, 4($t1) sw $t0, 4($t1) sw $t2, 0($t1) Contol Hazads (Banch Hazads) When the flow of instuction addesses is not sequential (i.e., PC = PC + 4); incued by change of flow instuctions Conditional banches (beq, bne) Unconditional banches (j, jal, j) Exceptions Possible appoaches Stall (impacts CPI) Move decision point as ealy in the pipeline as possible, theeby educing the numbe of stall cycles Delay decision (equies compile suppot) Pedict and hope fo the best! Contol hazads occu less fequently than data hazads, but thee is nothing as effective against contol hazads as fowading is fo data hazads 48

16 Banch Hazads p. 305 ( 頁 316) Fig When we decide to banch, othe instuctions ae in the pipeline! We ae pedicting banch not taken l need to add hadwae fo flushing instuctions if we ae wong 51 One Way to Fix a Contol Hazad I n s t. beq stall Fix banch hazad by waiting stall but affects CPI O d e stall stall lw Inst 3 IM Reg DM 52

17 IF.Flush Moving Banch Decisions Ealie in Pipe Move the banch decision hadwae back to the EX stage Reduces the numbe of stall (flush) cycles to two Adds an and gate and a 2x1 mux to the EX timing path Add hadwae to compute the banch taget addess and evaluate the banch decision to the ID stage Reduces the numbe of stall (flush) cycles to one (like with jumps) - But now need to add fowading hadwae in ID stage Computing banch taget addess can be done in paallel with RegFile ead (done fo all instuctions only used when needed) Compaing the egistes can t be done until afte RegFile ead, so compaing and updating the PC adds a mux, a compaato, and an and gate to the ID timing path Fo deepe pipelines, banch decision points can be even late in the pipeline, incuing moe stalls 53 Flushing Instuctions p. 308( 頁 320) Fig X 00 0 Optimized data path fo banch pefomance: Banch delay: 3 => 1 54

18 Instuction Flushing fo Banch p. 308( 頁 320) Fig Instuction Flushing fo Banch p. 308( 頁 320) Fig (Flushed and inst.)

19 Flushing with Mispediction (Not Taken) I n s t. O d e 4 beq $1,$2,2 8 flush sub $4,$1,$5 16 and $6,$1,$7 20 o 8,$1,$9 To flush the IF stage instuction, asset IF.Flush to zeo the instuction field of the IF/ID pipeline egiste (tansfoming it into a nop) 64 省還要更省 65

20 PC Dynamic banch pediction The BHT pedicts when a banch is taken, but does not tell whee its taken to! A banch taget buffe (BTB) in the IF stage can cache the banch taget addess, but we also need to fetch the next sequential instuction. The pediction bit in IF/ID selects which next instuction will be loaded into IF/ID at the next clock edge - Would need a two ead pot instuction memoy O the BTB can cache the banch taken instuction while the instuction memoy is fetching the next sequential instuction BTB Instuction Memoy Read 0 Addess If the pediction is coect, stalls can be avoided no matte which diection they go 68 1-bit Pediction Accuacy A 1-bit pedicto will be incoect twice when not taken Assume pedict_bit = 0 to stat (indicating banch not taken) and loop contol is at the bottom of the loop code 1. Fist time though the loop, the pedicto mispedicts the banch since the banch is taken back to the top of the loop; invet pediction bit (pedict_bit = 1) 2. As long as banch is taken (looping), pediction is coect 3. Exiting the loop, the pedicto again mispedicts the banch since this time the banch is not taken falling out of the loop; invet pediction bit (pedict_bit = 0) taken X O Fo 10 times though the loop we have a 80% pediction accuacy fo a banch 69

21 Dynamic Banch Pediction p. 310( 頁 321) Fig If the banch is not taken, we have the penalty of one cycle. Fo ou simple design, this is easonable With deepe pipelines, penalty inceases and static banch pediction dastically huts pefomance Solution: dynamically banch pediction Accuacy = 90% Not taken X O A 2-bit pediction scheme 70 Final data/contol path fo hazad handling p. 313( 頁 325) Fig

22 Summay All moden day pocessos use pipelining fo pefomance (a CPI of 1 and fast a CC) Pipeline clock ate limited by slowest pipeline stage so designing a balanced pipeline is impotant Must detect and esolve hazads Stuctual hazads esolved by designing the pipeline coectly Data hazads - Stall (impacts CPI) - Fowad (equies hadwae suppot) Contol hazads put the banch decision hadwae in as ealy a stage in the pipeline as possible - Stall (impacts CPI) - Delay decision (equies compile suppot) - Static and dynamic pediction (equies hadwae suppot) 78 Thank you! 79

23 2-Bit Pedicto (4th ed.) Only change pediction on two successive mispedictions p. 310( 頁 321) Fig