Introduction To Pipelining. Chapter Pipelining1 1

Transcription

1 Intoduction To Pipelining Chapte Pipelining1 1

2 Mooe s Law Mooe s Law says that the numbe of pocessos on a chip doubles about evey 18 months. Given the data on the following two slides, is this tue? Chapte Pipelining1 2

3 Chapte Pipelining1 3

4 Chapte Pipelining1 4

5 Intel Achitectue Chapte Pipelining1 5

6 Intel Achitectue Chapte Pipelining1 6

7 Intel Achitectue Chapte Pipelining1 7

8 Pipelining is Natual! A B C D Laundy Example Ann, Bian, Cathy, Dave each have one load of clothes to wash, dy, and fold Washe takes 30 minutes Dye takes 40 minutes Folde takes 20 minutes Chapte Pipelining1 8

9 Sequential Laundy 6 PM Midnight Time T a s k O d e A B C D Sequential laundy takes 6 hous fo 4 loads If they leaned pipelining, how long would laundy take? Chapte Pipelining1 9

10 Pipelined Laundy: Stat wok ASAP 6 PM Midnight Time T a s k O d e A B C D Pipelined laundy takes 3.5 hous fo 4 loads Chapte Pipelining1 10

11 Pipelining Lessons T a s k O d e 6 PM Time A B C D Pipelining doesn t help latency of single task, it helps thoughput of entie wokload Pipeline ate limited by slowest pipeline stage Multiple tasks opeating simultaneously using diffeent esouces Potential speedup = Numbe pipe stages Unbalanced lengths of pipe stages educes speedup Time to fill pipeline and time to dain it educes speedup Stall fo Dependences Chapte Pipelining1 11

12 The Five Stages of An Instuction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 lw Ifetch Reg/Dec Exec Mem W Ifetch: Instuction Fetch Fetch the instuction fom the Instuction Memoy Reg/Dec: Registes Fetch and Instuction Decode Exec: Calculate the memoy addess Mem: Read the data fom the Data Memoy W: Wite the data back to the egiste file Chapte Pipelining1 12

13 Pogam execution ode Time (in instuctions) lw $1, 100($0) Instuction Reg fetch Pipelining Data access Reg lw $2, 200($0) 8 ns Instuction Reg fetch Data access Reg lw $3, 300($0) Pogam execution Time ode (in instuctions) lw $1, 100($0) lw $2, 200($0) Instuction fetch 2 ns 8 ns Reg Instuction fetch Reg Data access Reg Data access Reg Instuction fetch 8 ns... lw $3, 300($0) 2 ns Instuction fetch Reg Data access Reg 2 ns 2 ns 2 ns 2 ns 2 ns Impove pefomance by inceasing thoughput Ideal speedup is numbe of stages in the pipeline. Do we achieve this? Chapte Pipelining1 13

14 Basic Idea IF: Instuction fetch 0 M u x 1 ID: Instuction decode/ egiste file ead EX: Execute/ addess calculation MEM: Memoy access WB: Wite back Add 4 Shift left 2 Add Add esult PC Addess Instuction Instuction memoy Read egiste 1 Read data 1 Read egiste 2 Registes Read data 2 Wite egiste Wite data 0 M u x 1 Zeo esult Addess Wite data Data memoy Read data 1 M u x 0 16 Sign extend 32 Single-Cycle Datapath; Coloed lines show flow of data backwads. What do we need to add to split the datapath into stages? Chapte Pipelining1 14

15 Pipelined (Single-Cycle) Datapath 0 M u x 1 64 bits 128 bits 97 bits 64bits IF/ID ID/EX EX/MEM MEM/WB Add 4 Shift left 2 Add Add esult PC Addess Instuction memoy Instuction Read egiste 1 Read data 1 Read egiste 2 Registes Read data 2 Wite egiste Wite data 0 M u x 1 Zeo esult Addess Wite data Data memoy Read data 1 M u x 0 16 Sign extend 32 Pipeline egistes (coloed), sepaate the datapath stages. Must be wide enough to stoe data, contol and conditions as they flow downsteam. Chapte Pipelining1 15

16 Why Pipeline? One Instuction Completes Each Cycle! Time (clock cycles) I n s t. O d e Inst 0 Inst 1 Inst 2 Inst 3 Inst 4 Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Chapte Pipelining1 16

17 Can pipelining get us into touble? Yes: Pipeline Hazads stuctual hazads: attempt to use the same esouce two diffeent ways at the same time e.g., combined washe/dye would be a stuctual hazad o folde busy doing something else (watching TV) contol hazads: attempt to make a decision befoe condition is evaluated e.g., washing football unifoms and need to get pope detegent level; need to see afte dye befoe next load in banch instuctions data hazads: attempt to use item befoe it is eady e.g., one sock of pai in dye and one in washe; can t fold until get sock fom washe though dye instuction depends on esult of pio instuction still in the pipeline Can always esolve hazads by waiting pipeline contol must detect the hazad take action (o delay action) to esolve hazads Chapte Pipelining1 17

18 Single Memoy Is a Stuctual Hazad Time (clock cycles) lw needs memoy hee I n s t. O d e Load Inst 1 Inst 2 Inst 3 Inst 4 Mem Reg Mem Reg Instuction fetch needs memoy hee Mem Reg Mem Reg Mem Reg Mem Reg Mem Reg Mem Reg Mem Reg Mem Reg Detection is easy in this case! (ight half highlight means ead, left half wite) Chapte Pipelining1 18

19 Stuctual Hazads Limit Pefomance Example: if 1.3 memoy accesses pe instuction and only one memoy access pe cycle then. aveage CPI 1.3 ; othewise, esouce is moe than 100% utilized. Chapte Pipelining1 19

20 Contol Hazad Solution #1: Stall I n s t. O d e Add Beq Load Time (clock cycles) Mem Reg Mem Reg Mem Reg Mem Reg Lost potential Mem Reg Mem Reg Stall: wait until decision is clea (conditional banching). Impact: 2 lost cycles (i.e., 3 clock cycles pe banch instuction) => slow. Move decision to end of decode. save 1 cycle pe banch. Chapte Pipelining1 20

21 I n s t. O d e Contol Hazad Solution #2: Pedict Add Beq Load Time (clock cycles) Mem Reg Mem Reg Mem Reg Mem Reg Mem Reg Mem Reg Pedict: guess one diection then back up if wong Impact: 0 lost cycles pe banch instuction if ight, 1 if wong (ight - 50% of time) Need to Squash and estat following instuction if wong Poduce CPI on banch of ( ) = 1.5 Total CPI might then be: = 1.1 (20% banch) Moe dynamic scheme: histoy of 1 banch (- 90%) Chapte Pipelining1 21

22 Contol Hazad Solution #3: Delayed Banch I n s t. O d e Add Beq Misc Load Next instuction always fetched. Time (clock cycles) Mem Reg Mem Reg Mem Reg Mem Reg Mem Reg Mem Reg Mem Reg Mem Reg Delayed Banch: Redefine banch behavio (takes place afte next instuction) Impact: 0 clock cycles pe banch instuction if can find instuction to put in slot (- 50% of time) As launch moe instuction pe clock cycle, less useful Chapte Pipelining1 22

23 Data Hazad on R1 add 1, 2, 3 sub 4, 1, 3 and 6, 1, 7 o 8, 1, 9 xo 10, 1, 11 Chapte Pipelining1 23

24 Data Hazad on R1: Dependencies backwads in time ae hazads I n s t. O d e Time (clock cycles) I ID/R E ME W F Im FReg X M Dm Reg B add 1,2,3 sub 4,1,3 and 6,1,7 o 8,1,9 xo 10,1,11 Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Chapte Pipelining1 24

25 Data Hazad Solution: Fowading (o Bypassing) Fowad esult fom one stage to anothe I n s t. O d e Time (clock cycles) I ID/R E ME W F Im FReg X M Dm Reg B add 1,2,3 sub 4,1,3 and 6,1,7 o 8,1,9 xo 10,1,11 Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg Im Reg Dm Reg o OK if define ead/wite of egiste-file popely Chapte Pipelining1 25

26 Fowading (o Bypassing): What About Loads? Dependencies backwads in time ae hazads Time (clock cycles) I ID/R E ME F Im FReg X M Dm lw 1, 0(2) W Reg B sub 4, 1, 3 Im Reg Dm Reg Can t solve with fowading. Must delay/stall instuction dependent on loads Chapte Pipelining1 26

27 Fowading (o Bypassing What About Loads Dependencies backwads in time ae hazads Time (clock cycles) I ID/R E ME F Im FReg X M Dm lw 1, 0(2) W Reg B sub 4, 1, 3 Stall Im Reg Dm Reg Can t solve with fowading: Must delay/stall instuction which dependent on loads Then diectly fowad data to esouce equesting it () Chapte Pipelining1 27

28 Summay: Pipelining Reduce CPI by ovelapping many instuctions. Aveage thoughput of appoximately 1 CPI with fast clock. What makes it easy: all instuctions ae the same length; just a few instuction fomats; memoy opeands appea only in loads and stoes.. What makes it had? stuctual hazads: suppose we had only one memoy; contol hazads: need to woy about banch instuctions; data hazads: an instuction depends on a pevious instuction.. Chapte Pipelining1 28

29 Summay Micopogamming is a fundamental concept implement an instuction set by building a vey simple pocesso and intepeting the instuctions essential fo vey complex instuctions and when few egiste tansfes ae possible Contol design educes to Micopogamming Chapte Pipelining1 29