CATHEDRAL-II (1) VLSI SIGNAL PROCESSING CHAPTER 5
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1 VLSI SIGNAL PROCESSING CHAPTER 5 Application-Domain-Specific Processors (ADSPs) CATHEDRAL-II (1) Paper De Man, H., J. Rabaey, J. Vanhoof, G. Goossens, P. Six and L. Claesen, CATHEDRAL-II, A Computer-Aided Synthesis System for Digital Signal Processing VLSI Systems, Computer-Aided Engineering Journal, pp 55-66, (April 1988). Academic predecessor of A RT Designer Earlier commercial names: Mistral, DSP Station Designed to allow user interaction in architectural synthesis. Selection/adaptation by: Sabih Gerez, University of Twente, February 26, Selection/adaptation by: Sabih Gerez, University of Twente, February 26, CATHEDRAL-II (2) State-of-the-art in 1988: 3 μm (3000 nm) techlogy vs. 90/65 nm w. No logic synthesis from HDL descriptions (VHDL was just emerging as a simulation tool); instead: layout generators for regular structures (module generators). Architecture model needs functional units t directly visible in DFG, such as calculation units (ACUs, basically incrementers to compute ROM/RAM es). application(s) Design process cycles/alg occupation more appl.? HW design nsec/cycle, area, power/instr processormodel 3 phases 1. exploration 2. hw design 3. design appl. sw Fast, accurate and early feedback go to phase 2 Selection/adaptation by: Sabih Gerez, University of Twente, February 26, Selection/adaptation by: Sabih Gerez, University of Twente, February 26,
2 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RF8 FU1 FU2 FU3 FU4 IR1 IR2 IR3 IR4 Instruction memory flags Control Additional characteristics of the A RT designer template interconnect network: busses + input multiplexers mux control is part of the instruction control can change every clock cycle network can be incomplete busses can be merged memories are modelled as FUs separated data in and data out 2 inputs (data in and ) and 1 output Each FU can generate one or more flags instruction format mux 1 mux 2 ADSP/VLIW architectures RF 1 RF 1 RF 2 RF 2 VLIW = very-long instruction word control FU output drivers Selection/adaptation by: Sabih Gerez, University of Twente, February 26, Selection/adaptation by: Sabih Gerez, University of Twente, February 26, ADSP/VLIW architectures: example ADSP/VLIW architectures: example bus1 RF1 RF2 RF3 RF4 ALU MAC bus2 GRTP RF1 = ALU (RF1, RF2) RF2 = ALU (RF1, RF2) RF3 = ALU (RF1, RF2) RF3 = MAC (RF3, RF4) RF4 = MAC (RF3, RF4) RF2 = MAC (RF3, RF4) Instruction bits x c c c c x x c c c x x x x x x x x x x x c x c c c c c c c x x x x x x x x x x x c x c c x x c c c c x x c c x x x x x x x x x x x x x x x c c c c c c x c c c x x x x x x x x x x x c c x x c c c c c c x x x x c c x x x x c c x x c x c c c mux 2 RF1 RF1 RF2 RF2 ALU instr. mux 3 RF3 RF3 RF4 RF4 MAC instr. Selection/adaptation by: Sabih Gerez, University of Twente, February 26, Selection/adaptation by: Sabih Gerez, University of Twente, February 26,
3 ADSP/VLIW architectures: design flow RF1 : x = RF2 : y, RF3 : z ALU = ADD Inmux = bus2 VLIW makes relatively simple code selection possible specification Datapath synthesis RTs area, power, timing Controller synthesis Selection/adaptation by: Sabih Gerez, University of Twente, February 26, assign ( a+b, ALU, fu_alu1) assign ( a+_, ALU, fu_alu1) assign ( _+_, ALU, fu_alu1) Change pragmas Design Database Design Database Mistral2 Mistral2 Estimation Low power aspects Architecture EXU ACTIVITY AREA POWER alu_ acs_asu_1 83% or_asu_1 10% romctrl_1 16% acu_1 36% ipb_ opb_1 11% ctrl total Selection/adaptation by: Sabih Gerez, University of Twente, February 26, area speed power Estimation Database GSM Viterbi decoder: default solution alu_1 alu_1 96% 96% romctrl_1 romctrl_148% 48% acu_1 acu_1 26% 26% ipb_1 ipb_1 5% 5% opb_1 opb_1 23% 23% ctrl ctrl total total controller responsible for 70% of power consumption maximum resource-sharing heavy decision-making : main loop with 16 metrics-computations per iteration EXU-numbers include Registers for local storage GSM Viterbi decoder: loop-folding alu_1 alu_1 92% 92% romctrl_1 romctrl_145% 45% acu_1 acu_1 25% 25% ipb_1 ipb_1 5% 5% opb_1 opb_1 22% 22% ctrl ctrl total total area down by 33% power down by 35% next step: reduce # of program-steps with second ALU Selection/adaptation by: Sabih Gerez, University of Twente, February 26, Selection/adaptation by: Sabih Gerez, University of Twente, February 26,
4 GSM Viterbi decoder : 2 ALU s GSM Viterbi decoder: 1 x ACS-ASU cycle count down 30% area up 42% power down by 5% next step: introduce ASU to reduce ALU-load 9739 alu_1 alu_1 69% 69% alu_2 alu_2 65% 65% romctrl_1 romctrl_167% 67% acu_1 acu_1 37% 37% ipb_1 ipb_1 8% 8% opb_1 opb_1 33% 33% ctrl ctrl total total func ACS ( M1, M2, d ) MS, MS8 = func ACS ( M1, M2, d ) MS, MS8 = begin begin MS = if ( M1+d > M2-d ) -> ( M1+d) ( M2-d) fi; MS = if ( M1+d > M2-d ) -> ( M1+d) ( M2-d) fi; MS8 = if ( M1- d > M2+d) -> ( M1- d) ( M2+d) fi; MS8 = if ( M1- d > M2+d) -> ( M1- d) ( M2+d) fi; end; end; = EXU EXU ACTIV ACTIV AREA AREA POWER POWER alu_1 alu_ acs_asu_1 acs_asu_1 83% 83% or_asu_1 or_asu_1 10% 10% romctrl_1 romctrl_1 16% 16% acu_1 acu_1 36% 36% ipb_1 ipb_ opb_1 opb_1 11% 11% ctrl ctrl total total cycle count down 5X power down 20X! Selection/adaptation by: Sabih Gerez, University of Twente, February 26, Selection/adaptation by: Sabih Gerez, University of Twente, February 26, GSM Viterbi decoder: 4 x ACS-ASU alu_1 alu_1 94% 94% acs_asu_1 acs_asu_1 95% 95% acs_asu_2 acs_asu_2 95% 95% acs_asu_3 acs_asu_3 95% 95% acs_asu_4 acs_asu_4 95% 95% split_asu_1 split_asu_1 47% 47% or_asu_1 or_asu_1 47% 47% romctrl_1 romctrl_1 28% 28% acu_1 acu_1 98% 98% ipb_1 ipb_1 23% 23% opb_1 opb_1 50% 50% ctrl ctrl total total cycle count down ather 5X area up 23% power down ather 3X! GSM viterbi example : summary Design Design Database Database Mistral power area cycles 72x 72x!! default loop 2 ALU 1 ACS 4 ACS Selection/adaptation by: Sabih Gerez, University of Twente, February 26, Selection/adaptation by: Sabih Gerez, University of Twente, February 26,
5 application(s) Discussion: phase 3 processormodel application(s) Conclusions more appl.? HW design Exploration phase Selection/adaptation by: Sabih Gerez, University of Twente, February 26, Freeze processor model Application software development: constraint driven compilation ADSPs provide efficient solutions for a well-defined application domain (2 orders of magnitude higher efficiency). The methodology is interesting for IP creation. The key problem is retargetable compilation. A (distributed) VLIW model is a good compromise between HW and SW. Although an automatic process can generate a default solution, the process usually is interactive and iterative for efficiency reasons. The key is fast and accurate feedback. Selection/adaptation by: Sabih Gerez, University of Twente, February 26,
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