TSEA22, DIGITALTEKNIK LECTURE 7

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1 LINKÖPING UNIVERSITY Department of Electrical Engineering TSEA22, DIGITALTEKNIK LECTURE 7 Mario Garrido Gálvez mario.garrido.galvez@liu.se Linköping,

2 FEEDBACK: POSITIVE Course: Good / Interesting / Relevant Lectures: Good / Interesting Good examples Easy to follow Lessons: Good Labs: Fun Easy vs Hard 2

3 FEEDBACK: TO IMPROVE Lectures: Upload to the web page what I write on the whiteboard Labs Add an intro to the lab Exams Add old exams to the webpage Suggested simulation programs Atanua Cedar Logic 3

MEMORY Circuit used for storage. It is an array of 2 n locations, each of which stores m bits of information. Each of the locations has one address that ranges from 0 to 2 n -1.

4 MEMORY Circuit used for storage. It is an array of 2 n locations, each of which stores m bits of information. Each of the locations has one address that ranges from 0 to 2 n -1. Therefore, the address of the memory is represented by n bits. ENABLE WR ADDRESS DATA IN 1 1 n WL WL WL DATA OUT We can read a memory location by selecting its address. n 2-1 In some memories we can also write in the memory locations. 4

5 TYPES OF MEMORY RAM = Random Access Memory ROM = Read Only Memory FLASH Property RAM ROM FLASH Read Yes Yes Yes Write Yes Only off-line and if it is programmable Yes, but not intended for being written often Volatile Yes No No Volatile: The data inside the memory disapears if it is disconnected from the power. 5

6 TYPES OF RAM RAM (Random Access Memory) - SRAM: Static RAM (static = does not need refresh) - DRAM: Synchronous Dynamic RAM (dynamic = needs refresh) - SDRAM: Synchronous Dynamic RAM (synchronous = synchronous with the clock) - DDR SDRAM: Double Data Rate SDRAM (upper and lower edge) 6

7 RAM MEMORY CELL DRAM SRAM Read / Write Cell Read / Write Cell Data C Data Data GND Why the DRAM needs refresh and the SRAM does not? 7

8 Selects address to be read / written RAM MEMORY LAYOUT Address 2 Address selection Read Write Refresh This is a DRAM. Other RAM memories have a similar layout with different cells. 8

9 WORKING WITH RAMs The figure shows a RAM memory. It works as follows: address is used to select the address where to read and/or write. The output provides the value selected by address in the same clock cycle that address is provided. Simultaneously, if write = 1, the value at the input ( datain ) is stored in the selected address, substituting the value in that address in the next clock cycle. The memory has 4 addresses of 8 bits each. Consider that initially all memory addresses are set to 0. Complete the timing diagram. ADDRESS WRITE DATAIN DATAOUT 9

10 TYPES OF ROM / FLASH ROM (Read Only Memory) - PROM: Programmable ROM (programmable off-line) - EPROM: Erasable Programmable ROM - EEPROM: Electrically Erasable Programmable ROM FLASH - It is an evolution of the ROM memories: Whereas the EEPROM needs to be erased completely when it is reprogrammed, in the FLASH different memory blocks can be erased independently. 10

the program memory of a new washing machine that admits

11 RAM, ROM or FLASH? Which memory would you use for: a USB stick? the data memory for a CPU? the program memory of an old washing machine? the program memory of a new washing machine that admits upgrades of the program? a SD memory card? a memory that works as a decoder from a 4-bit number to the 7 segments of a 7-segment display? 11

BUFFER The word buffer may mean different things. In this course, we use this word to refer to a circuit that delays a signal a number of clock cycles.

12 BUFFER The word buffer may mean different things. In this course, we use this word to refer to a circuit that delays a signal a number of clock cycles. We can also call it FIFO (First In, First-Out) WL L WL WL = data word length L = delay in clock cycles A buffer can be implemented by using registers (better for small buffers) or memories (better for large buffers). 12

13 USE OF MEMORIES AS BUFFERS To implement a buffer of length L, we can use a RAM memory with at least L addresses and a word length equal or larger than the word length of the input. We can use a counter to generate the addresses. Alternatives: If the memory only has one address for read and write, we can use the addresses 0 to L-1 of the memory and use them cyclically. If the memory has one reading address and one writing address, we can also make the reading address be a delayed version of the write address. In this case, we can use more than L addresses. 13

14 A shift register is used to: SHIFT REGISTER Collect data in series / in parallel and provide it in parallel / series. Create a cyclical movement of data. For instance, the following circuit is used to create a pseudo-random sequence: SHIFT REGISTER Q2 Q1 Q0 clk D Q clk D Q clk D Q 14

15 KEYBOARD DECODER From the lab of the courses TSUI03 and TSTE12. The goal is to detect numbers from a keyboard and show them on a 7-segment display. 15

16 QUOTE OF THE DAY Why do engineers confuse Halloween and Christmas? Because Oct 31 = Dec 25 16

Design and Implementation of an AHB SRAM Memory Controller

Design and Implementation of an AHB SRAM Memory Controller 1 Module Overview Learn the basics of Computer Memory; Design and implement an AHB SRAM memory controller, which replaces the previous on-chip