Design and Transient Analysis of high Performance HEMT based DRAM Cell

Transcription

1 _ Design and Transient Analysis of high Performance HEMT based DRAM Cell 1 Balwant Raj and 2 Sukhleen Bindra Narang 1 Assistant Professor, UIET, Panjab University SSG Regional Centre Hoshiarpur, Punjab, India 2 Professor, Dept. of Electronics Technology, Guru Nanak Dev University, Amritsar, Punjab, India Abstract : In this paper, work has been carried out for the design of HEMT based DRAM cell. The proposed HEMT based DRAM cell increases its speed of operation and can be used for high performance and low applications. The read/write operations have been verified and transient analysis have been performed for designed DRAM cell. We compared our results with reported data and significant improvements obtained in the simulated results, which validate our design approach. Keywords: Leakage Current, HEMT, DRAM, Simulations and AlGaN I. INTRODUCTION Dynamic Random Access Memory (DRAM) is the most cost efficient and common type of random access memory for personal computers and workstations. Providing high-density storage has long been recognized as the principal function of the DRAMs. The term dynamic is used because the leakage phenomenon inherent in DRAM necessitates the periodic refreshment for the purpose of data retention. DRAM is used for main memory of computer, due to its small size and large capacity. The area of the large memory modules is dominated by the size of the memory core. Thus, it is crucial to keep the size of the basic storage cell as small as possible. Semiconductor memory cells therefore reduce the cell area by trading off some desired properties of digital circuits, such as noise margin, logic swing, input/output isolation, fan-out or speed. While a degradation of some of those properties is allowable within the confined domain of the memory core where the noise levels can be tightly controlled, this is not acceptable when interfacing with the external or surrounding circuitry. It is common to reduce the voltage swing on the bit lines to a value substantially below the supply voltage. This reduces both the propagation delay and the power consumption. The trends in the DRAM cell structures since its evolution have been reviewed and we proposed a new DRAM in this work. The characteristics, read/write operations and limitations of all these cell designs have been described. II. BASIC MEMORY ARCHITECTURE A memory chip is composed of three blocks: a memory cell array, a peripheral circuit, and an input/output (I/O) interface circuit. A memory cell array comprising a matrix of 2X rows and 2Y columns can store binary information of 2X+Y bits. Any cell can be accessed at random with the same speed by selecting both the corresponding row and column. Figure 1 Array Structure Memory Organisations Memory Cell Array The basic array structured memory organization is shown in figure (1).In the memory organization, there are memory cell arrays, sense amplifiers and row and column decoders. In the memory, any word can be selected for reading and writing by providing the address word. The address word is partitioned into a column address (A 0 to A K-1 ) and a row address (A K to A L-1 ). The row address enables one row of the memory for R/W, while the column address picks one particular word from the selected row. Multiple words are stored in single row and are selected simultaneously. Any cell can be accessed at random with the same speed by selecting both the corresponding row and column.to route the correct word to the input/output (I/O) terminals, an extra circuitry called the column decoder is needed.the horizontal select line that enables a single row of cells is called the word line, while the wire that connects the cells in a single column to the I/O circuitry is called the bit line. When design the memory chip, the 39

2 _ memory aspect ratio should be taken into consideration. The distortion in aspect ratio results in a design that cannot be implemented. Besides the bizarre shape factor, the resulting design is also extremely slow. To solve this problem, memory arrays are organized so that the aspect ratio approaches unity. III. HEMT STRUCTURE HEMT is a three terminal device as shown in figure 2), which operation principle is based on those of the MESFET. The current between drain and source is controlled by the space charge, which is changing by applying the voltage to the gate contact. The current between drain (D) and source (S) is flowing through the two dimensional conducting channel, created by electrons called 2 dimensional electron gas (2DEG). The existence and the quality of 2DEG have a significant consequence on the electronic transport along the interface as well as to properties of final devices. Figure 2: AlGaN/GaN HEMT device Structure IV. HEMT BASED DRAM CELL DESIGN Dynamic Random Access Memory (DRAM) cell array usually covers 50-60% of the total chip area, and decreasing the cell size is the most efficient way to reduce the DRAM chip size. In early CMOS DRAM storage cell design, three-transistor and four-transistor cells were used in 1-Kb and 4-Kb generations. Later, one-transistor cell, providing smaller cell size and low cost, became the industry standard. In further attempts to scale the memory cell size, the concept of capacitor less single transistor cell was proposed [9]. DRAM is the most cost efficient and common type of random access memory for personal computers and workstations. Providing high-density storage has long been recognized as the principal function of the DRAMs. The term dynamic is used because the leakage phenomenon inherent in DRAM necessitates the periodic refreshment for the purpose of data retention. The first DRAM was proposed in 1970 with a capacity of 1Kb. Since then, DRAMs have been the major driving force behind VLSI technology development. DRAM market has achieved an unprecedented six-fold increase in memory capacity in the last three decades - from the 1-Kbit level in 1970 to the Giga and Tera byte level today [10, 15]. 4.1 DRAM Cell Operations Writing operation: As shown in figure 3, It starts with zero charge across the DRAM capacitor C1.Now first, M1 has to be switched on (through V3 supply) to write data in the DRAM or to charge the capacitor C1. Now M2 will be switched on (through V2 supply) and data will be written in memory cell through supply V3 and C1 will be fully charged or DRAM will store 'one'. All the supplies here are taken as asquire pulse generator with variable 'on' and 'off' time based on requirements of the present analysis. Reading Operation: To read data, first M1 is switched off (holding sate of DRAM), M2 is switched on and then C2 is charged to half of the supply voltage (V dd /2)through V1. Now M2 will be switched off to cut off any discharging path for C2. Now M1 will be switched on and there will be charge transferbetween C1 Figure 3 DRAM cell structure and its support circuitry and C2. If C1 is holding 0, voltage across C2 will be reduced by some factors from V dd /2 and it will be reverse if C1 is holding 1 So, bysensing the voltage change across the capacitor C2, data can be read out fromthe DRAM cell. 40

3 _ V. PERFORMANCE ANALYSIS OF HEMT Transient analysis is performed on the DRAM circuit to evaluate its performance as shown in fig. 3 and voltages at different points are plotted at different times. The plots of the different voltages are shown below in fig.4, 5 and 6. Figure 4: Analysis of DRAM Structure Red Curve : Voltage at node 1 Blue Curve : Voltage at node 2 Cyan Curve : Voltage at node 3 Orange Curve : Voltage at node 4 Green Curve : Voltage at node 5 Figure 5 Analysis of DRAM Structure Red Curve : Voltage at node 3 Green Curve : Voltage at node 4 41

4 _ From the above three graphs we can see the variation of voltages at different nodes marked in the diagram and from there we infer the proper working of DRAM cell which employs the use of HEMT as its switching device. The analysis also tells that the HEMT can work as a transistor in DRAM cell. So, from this we can propose the use of HEMT as a base for the future development of DRAM to have a faster operation. VI. CONCLUSION In this paper analysis of HEMT device have been carried out for circuit application. The DRAM cell have been designed with device. By using proposed structure of HEMT device, we have successfully implemented a HEMT Device in a 1T DRAM Cell. Our proposed model is having high drain current which helped in enhancing the switching frequency as compared to the conventional MOS based DRAM cells. The work carried out in this paper will be useful for scientific and research community high density and low power memories design. REFRENCES [1] N. Harada, S. Kuroda, T. Katakami, K. Hikosaka, T. Mimura, and M. Abe, "Pt-based gate enhancement mode HEMTs for large-scale integration," Znt. ConfiZnP and Related Materials, Cardif, pp , [2] D. Marcon, J. Viaene, P. Favia, H. Bender, X. Kang, S. Lenci, S. Stoffels, S. Decoutere, Reliability of AlGaN/GaN HEMTs: Permanent Figure 6: Analysis of DRAM Structure Red Curve : Voltage at node 1 Green Curve : Voltage at node 2 Violet Curve : Voltage at node 3 leakage current increase and output current, Microelectronics Reliability 52, pp , [3] Yu-Syuan Lin, Yi-Wei Lain, and Shawn S. H. Hsu, AlGaN/GaN HEMTsWith Low Leakage Current and High On/Off Current Ratio, IEEE ELECTRON DEVICE LETTERS, VOL. 31, PP NO. 2., [4] Balwinder Raj, A. K. Saxena and S. Dasgupta, Analytical Modeling for the Estimation of Leakage Current and Subthreshold Swing Factor of Nanoscale Double Gate FinFET Device Microelectronics International, UK, vol. 26, pp , [5] Pierret, Robert, Semiconductor Device Fundamentals, Addison-Wesley Publishing Company, Massachusetts, PP. 526,1996. [6] Takeuchi and Akasaki, GaInN Quantum Wells: Piezoelectricity, Feb1998 Properties, Processing and Applications of Gallium Nitride and Related Semiconductors, INSPEC, p. 525, [7] Asbeck, P.M., Piezoelectric Charge Densities in AlGaN/GaNHFETs, ELECTRONIC LETTERS, Journal No.14, Vol. 33, pp , 3 July [8] Iruthayaraj Beaula Rowena, Susai Lawrence Selvaraj, and Takashi Egawa Buffer Thickness Contribution to Suppress Vertical Leakage Current WithHigh Breakdown Field (2.3 MV/cm) for GaN on Si, IEEE ELECTRON 42

5 _ DEVICE LETTERS, VOL. 32,PP NO. 11, NOVEMBER2011. [9] A DRAM BOOK named DRAM Circuit Design: A Tutorial By BrentKeeth and R. Jacob Baker, John Wiley & Sons, [10] Balwinder Raj, A. K. Saxena and S. Dasgupta, Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance metric, Process variation, Underlapped FinFET and Temperature effect IEEE Circuits and System Magazine, vol. 11, issue 2, pp , [11] Haliday, Resnik, Walker, Fundamentals of Physics 5th Edition, John Wiley &Sons, New York, NY, [12] Atlas_userspdf available in folder doc,subfolder in Silvaco shortcut. [13] Ambacher, O., et al, Two Dimensional Electron Gases Induced by Spontaneousand Piezoelectric Polarization in Undoped and Doped AlGaN/GaN Heterostructures, Journal of Applied Physics, Journal no. -1,Vol. 87, PP ,January 1,2000. [14] Mohney, S., Schottky Barrier Contacts to GaN, April 1998, Properties,Processing and Applications of Gallium Nitride and Related Semiconductors, p. 496,INSPEC [15] Balwinder Raj, A. K. Saxena and S. Dasgupta, High Performance Double Gate FinFET SRAM Cell Design for Low Power Applications, International Journal of VLSI and Signal Processing Applications, vol.1, pp , 2011, ISSN