From Majorca with love

Transcription

1 From Majorca with love IEEE Photonics Society - Winter Topicals 2010 Photonics for Routing and Interconnects January 11, 2010 Organizers: H. Dorren (Technical University of Eindhoven) L. Kimerling (MIT) R. Luijten (IBM Zurich) S. Namiki (AIST)

2 Conference synthesis (RUMP session) Everything has to be in CMOS. Vertically integrated company needed to make it happen Single mode transport required for scalability Two near term datacenter disruptions PCM: pulse code modulation 3D packaging: heterogeneous electronic-photonic integration BW bottlenecks are the VALUE points in the technology supply chain. The DATA is the problem and not the compute data at rest tends to stay at rest Internet / Datacenter switching solve a global problem with local information and decisions Internet architecture moves to DC: distributed, parallel clusters DIRECT CONNECT architecture moves to chip level! Need Photon source from the wall socket just like electrons Workshop Summary 11 Jan 2010 Majorca, Spain

3 Trends Drivers Video-related services: bandwidth Ubiquitous sensor data: transport and management System parallelism: performance, power efficiency, programmability Applications HPC Data Center and Cloud Computing Network Nodes Bottlenecks Bandwidth density and energy bottlenecks at all system hierarchy levels from on-chip interconnects to global networks. Scaling limits of parallelism could be overcome by photonics, but many challenges from material to entire system architecture remain. We may still need substantial advances at the materials and fundamental physics level. 3

4 Trends Economics, Social and Policy Issues Horizontal business structures present a barrier to photonic integration. Harsh competition after the telcom bubble High volume production is the key to low cost. Telecommunication networks are low volume ʻGreenʼ could be a strong driver for photonics Particularly in data centers Paradigm Shifts Re-arranging the roles and loads of computing, storage, and networking through all-scale, all-optical interconnects Virtual infrastructure, better scalability. Optical path switching is Green for very high content transmission Should play a central role for future networks. 4

5 Electrical Power Consumption Trend is not Sustainable Ken-ichi Sato, Nagoya U 5

6 Price/Service Trend is not Sustainable Ken-ichi Sato, Nagoya U 6

7 Power Efficiency Improvement is not Sufficient Ken-ichi Sato, Nagoya U 7

8 Problem in today s network infrastructure Traffic is growing at 50% per year (perhaps more) Systems density is being limited by power dissipation 10kW per rack in telecom central offices ~50kW per rack in data centers Most of the power is being used for interconnect On chip and off chip interconnects Increasingly off chip Interconnect power scales slowly with time Scales with linear dimension reduction of Moore s law 20% per year Increasing length of electrical interconnect increases power Can t pack it closer and can t spread it out David Neilson, Alcatel-Lucent Bell Labs 8 8 All Rights Reserved Alcatel-Lucent 2010,

9 Fundamental Limits: Roadmaps to Exascale Key points The single most difficult and pervasive challenge perceived by the study group dealt with energy, namely,...energy per operation [The] energy in data transport will dwarf the traditional computational component in future Exascale systems...particularly so for the largest data center class. Data transport is *the* energy problem. Perhaps 200x more energy needed to transport a bit from a nearestneighbor chip than to operate on it. Energy needed for a floating-point operation (~ʼ13-ʼ16): pj/bit Energy needed for data transport (on-card, ~6,~ʼ13-ʼ16): 2-10 pj/bit Across a big system (50meter diameter, multi-stage network, with routers and multiple transceiver hops), the factor may be 1000x. Summarizing: Other than some software and reliability issues associated with 100-Million to 1Billion-way CPU parallelism, scaling to Exascale is hard but straightforward -- *unless* data needs to move between chips. However, data does need to move between chips. Yes, 100 Million to Billion-way! Alan Benner, IBM 9

10 Can electrical transmission solve the data transport problem? No - there are hard limits, due to: Attenuation and signal distortion at high frequencies Ritter, et. al., The viability of 25 Gb/s on-board signaling, ECTC 2008 Required System Diameter: ~8,000 10,000 cm Connectors: physical bandwidth density relative to silicon at acceptable reliability Size and weight of high-bandwidth copper cables (even with active copper) Power efficiency Typical standard electrical link budget is for ~20-25 db of loss between Tx and Rx i.e., >99% of transmitted power is lost before it reaches the receiver -- *terribly* energy inefficient. Alan Benner, IBM 10

11 Gaps and Solutions Scale $/Gb/s Reduce Interconnection power CPU to Memory Improve Interconnection density Ultimate Solution Paradigm Standard device and interconnection platform Fully designed and integrated Chip-to-System-to-Network Monolithic Integration in CMOS Single mode waveguide integration High density integration for cost and performance 11

12 Year Tech. Node (nm) On-Chip Clock (GHz) Off-Chip Clock (GHz) Signal Pins Total I/O (Tb/s) fj/bit for Off-Chip constant B/ FLOP Numbers from ITRS Roadmap Number of off-chip pins saturates Clock speed limited Energy allowed per bit becomes very small Interconnects cannot keep up with ability of chip to process Ratio of Bytes of memory access per operation (e.g., floating point operation FLOP) cannot be maintained Device Requirements for Optical Interconnects to Silicon Chips, Proc. IEEE 97, (2009)

13 1. What are the key success factors to use photonics within the server or router box? Reduce power energy per bit interconnected is what matters Get used to thinking in units of pj/bit [= mw/(gb/s)] Note we care about total energy, not received energy Improve connection density 2. What is an example of successful deployment of photonics in our systems? Optical interconnects between cabinets 3. Can you describe the 'gap'? Photonics technology not well enough integrated with electronics Seamless integration with silicon CMOS is essential For cost and performance Then optics and electronics each do what they do best 4. Can you propose a disruptive use of photonics in datacenters? Reduce energy to get information in and out of memory Energy presently ~ 2000 pj per 64 bit word in large machines

14 The Four Questions Success Factors: Driven by Integration and Design Flexibility Bandwidth Density Power per corrected bit Cost / bit * distance 1/3 The Gap: 1000x increase in bandwidth density performance Faster per channel 4x-10x Bit rate and mod format Channels per fiber 10x-32x DWDM Fiber density: 10x Multicore or smaller fiber Examples of Success: (Really commitments) IBM: PERCS/P7-IH capacity density: tight integration Intel: LightPeak 10 Gbps sales volume drives down cost Disruptive Optics: Distance independent optical interconnect At the optical layer, one optical device design and connector hierarchy Centralized off-board light source Roe Hemenway, Corning Science & Technology IEEE Photonics Winter Topicals 14

15 Electronics + photonic: options 1. Monolithic with CMOS a) Photonics in back-end: waveguide deposited on metal interconnects b) Photonics in front-end: waveguides in transistor layer (e.g. Luxtera) Many limitations on photonics and electronics 2. Heterogeneous integration: separate fabrication of electronics and photonics a) Package-level integration: separate chips in a single package (e.g. Lightwire) limited connectivity between chips packaging = costly b) 3-D integration: stack layers vertically dense connectivity wafer-scale processing Roel Baets, U Ghent

16 Energy is Disruptive Cost of Ownership CoO = (capital + electricity) / (performance) Drives shorter product cycle times More new technology Dense Integration Higher Yield and Reliability Higher Production Volumes Standardization and Larger TAM Electronic-Photonic Synergy Short electrical lines; high BW density photonics energy, form factor, cost/performance High density, monolithic electronic-photonic integration in CMOS/systems CSAIL 16 communications technology roadmap