The Xilinx UltraScale Architecture

Transcription

1 The Xilinx UltraScale Architecture Stephanie Rupprich School for Computer Science Heidelberg University, Ruperto Carola Heidelberg, Germany Abstract In the last few years, the capabilities of electronic devices have developed very quickly. End-consumers continue to ask for more bandwidth, more storage and higher resolution in the devices they buy. The FPGA manufacturer Xilinx describes this as the so-called More is Better mindset. In order to keep pace with the increasing market demands, Xilinx introduced the UltraScale architecture in It is supposed to tackle the main bottleneck of their previous-generation 7 series FPGAs, the interconnect, by implementing so-called Fast Tracks. Based on the 7 series, processing and bandwidth capabilities were improved and some other innovations were realised in the devices, e.g. ASIC-like clocking. In this paper, the history of FPGA generations is briefly reviewed and two FPGAs will be discussed in more detail: Xilinx previous-generation Virtex-7 FPGA and the current-generation Stratix 10 device by Altera. Subsequently, the Xilinx UltraScale architecture is introduced and its new features described. Afterwards, it is evaluated in comparison to the Virtex-7 device and Altera s Stratix 10 FPGA. Finally, all findings are sumarized and a conclusion is given. I. INTRODUCTION Since the UltraScale architecture is an FPGA architecture recently introduced by Xilinx, the term FPGA will be briefly discussed in this section. FPGA is the abbreviation for Field-Programmable Gate Array which is a general purpose semiconductor device programmed after manufacturing. This distinguishes it from Application-Specific Integrated Circuits (ASICs) and Application-Specific Standard Products (ASSPs), which, as their name suggests, are developed for a single application. In contrast to FPGAs, their hardware function is predefined and cannot be changed once the manufacturing process is finished. Consequently, when using FPGAs, the product features, which may be ASIC functions, are programmed first. Afterwards, the software which will be running on the previously configured hardware is developed. FPGAs are used for various security, audio, video and image processing functions in the fields of automotive, aerospace and defense, broadcast, consumer electronics, medical and wired and wireless communication. [1] [3] An FPGA consists of programmable building blocks (shown in figure 1) as well as a configuration memory which stores the description of the hardware functionality. The most primitive building block is a logic block (configurable logic block (CLB), logic cell (LC) or logic element (LE)). In figure 1, it is highlighted yellow. In an FPGA, CLBs are arranged in form of a matrix and contain Look-Up-Tables (LUTs) for logical functions and flop flops for storage. The Input/Output (I/O) blocks, which are marked blue in figure 1, are placed at the Fig. 1. FPGA Architecture [4] edges of the FPGA. They are the ideal interface bridge as they support many I/O standards. The programmble interconnect (represented as green lines in figure 1) is responsible for routing the signals between the CLBs and to and from the I/O blocks. They are placed in form of horizontal and vertical wires which span the whole device to provide low-skew clocking. Additionally, there are special-function building blocks, e.g. configurable block RAM (BRAM) for data storage, builtin multipliers and Digital Signal Processing (DSP) blocks for multiplication and mathematical signal manipulation, as well as multi-gigabit transceivers (which are basically Serializer- Deserializer (SerDes) operating at bit rates of more than 1Gbit/s) as high-performance interfaces. [1] [3], [5] [10] A. Overview II. FPGA GENERATIONS With each new generation of semiconductors, there is also a new generation of FPGAs. Approximately every two years, there is a new generation announced with a smaller processing size than the previous generation. For example, while the FPGAs introduced in 2004 had a process size of 90nm, the current-generation FPGAs are produced at 16nm or even at 14nm. In order to place the transistors on the die

2 even more densely, their size is reduced more and more, for example by changing the material of the gate or the gate oxide. Additionally, the shape of the transistor is changing from planar (2D) to 3D. The main manufacturers of FPGAs are Xilinx and Altera. Up to the last generation FPGAs, both manufacturers had three device families: low-cost (Xilinx Spartan / Artix, Altera Cyclone), mid-range (Xilinx Kintex, Altera Arria) and high-end (Xilinx Virtex, Altera Stratix). [11] [27] In the following sections, two high-end device families will be discussed in more detail: the Virtex-7, a previous-generation FPGA by Xilinx and the Stratix 10, a current-generation device by Altera. Afterwards, the current-generation UltraScale devices by Xilinx will be introduced. B. Example 1: The Xilinx Virtex-7 FPGA The Virtex-7 FPGA was introduced in 2010 and initial devices were available in It is manufactured on TSMC s 28nm High-K Metal Gate (HKMG) High Performance and Low power (HPL) process technology. The main transistor improvements include the use of a high-k gate oxide and a metal gate instead of silicon oxide as the gate oxide and a polysilicon gate. The result is a reduced leakage which has been the problem in traditional transistors since thinning the dielectric was not possible any more. The whole 7 series (Spartan, Kintex and Virtex families) has one unified architecture which allows one to start designing on one device family and easily switch to another one if there is a change in performance and cost requirements. Being part of the architecture, the AXI interconnect is conform to ARMs AMBA AXI v4 specification and connects AXI memory-mapped master devices to memorymapped slave devices. Finally, the architecture is a so-called Application-Specific Modular Block (ASMBL) architecture, which is an FPGA development model for adopting offthe-shelf, flexible solutions for different application domains. Therefore, FPGA logic is structured into long, narrow stripes which are defined during the silicon manufacturing stage and are either a standard CLB or a function-specific block (DSP, etc.). [15], [25], [26], [28] [36] According to Xilinx, the Virtex-7 has twice the system performance or half the power consumption than the Virtex-6 devices: it can operate at up to 600MHz or with less than 2W. With up to 5, 335GMAC/s, the DSP performance is almost doubled and there are up to 3,600 DSP slices placed on the chip. Moreover, the I/O bandwidth is increased by 60%: up to 2, 784Gb/s with up to 96 high-speed serial transceivers. The memory bandwidth is also twice as high (1, 886Mb/s for DDR3) and so is the density with almost 2, 000k logic cells. [15], [28] [30] C. Example 2: The Altera Stratix 10 FPGA In June 2013, Altera announced their Generation 10 FPGAs and System-on-a-Chips (SoCs). First test-chips were available in 2013 while the early-access design software for customers will be released in summer The Stratix family has always been Alteras high-end solution and this has not changed with the Stratix 10. It is manufactured on Intel s 14nm Tri- Gate process technology. Due to the 3D transistors with an increased effective channel width (and therefore an increased drive strength), higher performance can be archieved in the same die area. Moreover, the Stratix 10 is based on Altera s HyperFlex architecture. It is a new core fabric architecture which aims to overcome the limitations of conventional architectures, particularly increasing bus widths, routing congestion and interconnection delays. This is supposed to result in a higher performance and power efficiency. Additionaly, heterogeneous 3D solutions will be available which allow the mixing and matching of FPGAs, SRAM, DRAM and ASICs based on the application requirements. [20], [37] [43] The Stratix 10 is supposed to set a new level in system performance. Compared to previous-generation FPGAs, the core performance of up to 1GHz is twice as high or the power could be decreased by 70%. According to Altera, the DSP performance will be more than 10T F LOP/s at 100GF LOP s/w. With up to 144 transceivers, the highest transceiver bandwidth of up to 8, 064Gb/s is four times as high as in the previous-generation devices. Additionally, the memory bandwidth for DDR4 memory will be up to 3, 200MB/s. Finally, with more than four million logic elements, the Stratix 10 will be the largest monolithic FPGA on the market. [20], [37] [42] III. THE XILINX ULTRASCALE ARCHITECTURE A. The 7 Series as Foundation for Success Xilinx decided to build their new UltraScale architecture upon the foundation of their successful previous-generation 7 series FPGAs. There are three main cornerstones: the silicon process technology, the Stacked Silicon Interconnect (SSI) technology and the Vivado Design Suite. As mentioned in II-B, the 7 series is fabricated using the 28nm HPL process technology. Xilinx is cooperating with TSMC and they will continue this partnership in order to manufacture the UltraScale architecture devices using the 20nm 20Soc planar and 16nm FinFET process technologies. The production of higher-capability FPGAs than traditional manufacturing methods can offer with individually packaged dies is enabled by the SSI technology. It allows the combination of multiple super-logic regions (SLRs) on a passive interposer layer using dedicated interface tiles to create a single FPGA with less than 1000 inter-slr connections. While the first-generation SSI technology was based on the 7 series, the second generation will be based on the UltraScale architecture. Also introduced with the 7 series, the Vivado Design Suite attacks key bottlenecks in programmable systems integration and implementation. There are new approaches for placement and routing where multi-variable cost functions enable faster finding of the optimal solution, even at a device utilization higher than 90%, without a trade-off in performance. Soft-

3 TABLE I XILINX ULTRASCALE DEVICES AND MAXIMUM CAPABILITY Maximum Capability Kintex UltraScale Virtex UltraScale Introduction 2013 Shippment 2014 Process Technology 20nm planar 20nm planar, 16nm FinFET Logic Cells 1, 160K 4, 407K Block RAM 76Mb 115Mb DSP48 Slices 5, 520 2, 880 Peak DSP Performance 8, 180GMAC/s 4, 268GMAC/s s Peak Speed 13.6Gb/s 32.75Gb/s Peak Serial Bandwidth 2, 086Gb/s 5, 101Gb/s PCIe Blocks g Ethernet Blocks G Interlaken Blocks 1 9 Memory Interface 2, 400Mb/s I/O Pins 832 1, 456 Specialization Signal Processing Processing, Bandwidth, Throughput Fig. 2. More Interconnect Tracks Due to Fast Track Routes [50] and hardware were improved concurrently, which Xilinx calls co-optimization. [20], [37] [42] B. Market Requirements Nowadays, all kinds of electrical devices experience a rapid development in their capabilities. This is the so-called More is Better mindset. For example, at the moment, there are digital video applications in 1080p, but the step to 4k (Quad HD) is not far. Further, but still in sight, there will be video applications in 8K (Super Hi-Vision) resolution. This is only one example, but in order to keep pace with the increasing demand on all system components, especially bandwith and processing capabilities, the FPGA architecture has to be fundamentally improved. This includes communication, clocking, critical paths and especially the interconnect, which has been the number one bottleneck of Xilinx FPGAs. [44] C. Device Portfolio In order to tackle the former bottlenecks, in 2013, Xilinx introduced their new UltraScale architecture. The device portfolio consists of two devices: the Kintex UltraScale, where initial devices are already available, and the Virtex UltraScale, where initial devices are supposed to be available in the second quarter of In contrast to the 7 series, Xilinx decided not to distinguish their device portfolio by performance and cost requirements. Instead, the devices are differentiated by their specialization for different target applications. The Kintex UltraScale is optimized for signal processing and tasks of the last-generation high-end devices while the Virtex UltraScale s strengths are processing, bandwidth and throughput. This is shown by the colored cells in table I, which contains details and a comparison of the two device families capabilities. Yellow means that the FPGA is performing poorer while green stands for a higher performance. Both devices are available either in monolithic form or within the next-generation SSI technology. [30], [45] [49] D. Features Xilinx implemented a variety of features in their UltraScale architecture. In this section, the following aspects will be discussed: Scalability Data Flow and Routing Fast, Smart Processing (Bandwidth, Processing) and Other Features. The first feature of the UltraScale architecture is scalability. In the 7 series, the same lowest-level building blocks were used in different FPGA families which allowed the porting of hand-coded register-transfer-level designs to any 7 series device without modification. In the UltraScale devices, there is an additional package footprint capability across the platform allowing designs to scale to other family members with a different resource mix. Another kind of scalability is the availability of the Virtex UltraScale in either 20nm planar or 16nm FinFET technology. [23], [45] Another innovation improving data flow and routing is the implementation of Fast Tracks. The issue with routing is that with decreasing FPGA process sizes, the number of logic elements increases a lot faster than the number of interconnect tracks (see figure 2). Fast Tracks carry data between logically connected, but not necessarily adjacent logic cells. Thus, the software has more options to connect logic resources in the optimal way. Consequently, routing congesting is supposed to be eliminated. According to Xilinx, if the design fits, it routes. This is supposed to be true for device utilizations of more than 90% without trade-offs is performance or latency. [23], [45], [46], [50] In order to improve processing capabilities, the UltraScale architecture contains improved bandwidth and processing ca-

4 pabilities. For fast I/O, all devices contain GTH transceivers with a bandwidth of 500M b/s up to 16.3Gb/s. Virtex devices additionally contain GTY transceivers, which support bandwidths of up to 32.75Gb/s. Both include internal gearbox logic which operates at hundreds of MH/s and makes an external gear box redundant. For the sake of a higher memory bandwidth, there are multiple DDR3- and DDR4-capable SDRAM memory controllers with wider and faster ports compared to the previous generation, enabling data rates of up to 2, 400M b/s. The hardened SDRAM PHY blocks reduce latency by 30% and decrease power consumption by 20%. In addition, there are several BRAM and FIFO improvements. For example, there is a cascading scheme which uses output multiplexers in a novel way allow the creation of large BRAMs and FIFOs without additional routing or logic resources. In the 7 series, only two adjacent memory blocks could be connected. Furthermore, there is a support for differently sized FIFO ports, so users can create FIFOs with a different input and output port width. There are two main enhancements in signal processing. The DSP48E2 slices provide more functionality than the DSP48E1 slices implemented in the 7 series. Due to the increased number of multipliers (from 25x18-bit to 27x18-bit), larger functions can be mapped into fewer DSP slices. The inclusion of wide-mux and wide-xor functions facilitate non-dsp computations within the DSP slices. Therefore, fewer CLBs are needed which makes them available for other functions. The packet processing capabilities are improved by the integration of hardened Gigabit Ethernet MACs and Interlaken chip-to-chip interfaces, which increase the performance and level of integration of the device. Additionally, the modified DSP slices can perform CRC32 checksum calculations at wire speed, which also boosts the packet processing performance. [23], [45], [46], [50] Other features added to the UltraScale architecture are ASIC-like Clocking, Power Management, Multi-level Security, (Re-)Configuration and Co-optimization. In the 7 series FPGAs, clocking regions were defined as half of the device width in horizontal direction. In contrast, in the UltraScale architecture, the clocking regions of the devices are rectangular shapes with a fixed width and height and they are organized in tiles. The multi-region ASIC-like clocking is designed to reduce the clock skew by 50%. Additionally, the system-level clock can now be placed anywhere on the die, which makes is easier to find the optimal clock location. According to Xilinx, enhanced power management reduces power consumption by 50% compared to the 7 series. This is due to static and dynamic power gating through silicon and software. The new clocking architecture leads to the clocks only being driven where needed which increases the gating granularity and allows part of the logic to be turned off. The GTH transceivers also have an additional low-power mode to decrease power consumption. Furthermore, the enhanced DSP capabilities decrease the amount of DSP slices needed. Finally, unused BRAM blocks can be put into a sleep mode while still preserving their data, which results in only used blocks leaking power. In order to protect the IP loaded into the devices and prevent tampering, Xilinx improved various security features, e.g. the AES bit-stream decryption and authentication, and they added key-obfuscation features. Additionally, the System Monitor monitors the device s physical environment by using the on-chip temperature and supply sensors in order to detect tampering attempts. The Configuration and Encryption block enables device configuration from external media using various protocols (e.g. PCIe). Furthermore, there is a new configuration mode which allows the configuration from two quad SPI flash memories in parallel, which is equal to the x8 configuration and significantly decreases configuration time. Finally, partial and self-reconfiguration are supported as well. The last new feature is the co-optimization, which has already been discussed in III-A. [23], [45], [46], [50] [53] E. Application Areas The application areas of the UltraScale devices are still the same as of traditional FPGAs. However, Xilinx emphasizes the applicability of their devices mainly in optical transport networking, digital video processing, wireless communications and intelligence surveillance and reconnaissance as they are all areas with the More is Better mindset, which require increasing packet processing and data flow capabilities, I/O and memory bandwidth, and DSP performance. Another application may be ASIC prototyping and emulation. [23], [50], [54], [55] IV. EVALUATION The comparison of the Xilinx devices discussed before is shown in table II while table III contains details about the current-generation devices. Red cells mean lowest performance, yellow stands for moderate and green for higher performance compared to the other devices. A. Xilinx Devices As table II shows, compared to the previous-generation Virtex-7, all capabilities were improved in either the Kintex or the Virtex UltraScale device family, depending on its specialization. While the Kintex UltraScale contains fewer logic cells than the Virtex-7 and performs more poorly in serial I/O (transceivers and number of I/O pins), its DSP performance is a lot higher. In contrast, the Virtex UltraScale has lower performance in DSP capabilities, but it is superior in all other areas. This shows Xilinx new specialization strategy. Additionally, there are a lot of minor but helpful architecture tweaks, which were already discussed in section III.

5 TABLE II MAXIMUM CAPABILITY OF XILINX DEVICES Maximum Kintex Virtex Capability 7 Virtex-7 UltraScale UltraScale Introd./Shipm. 2010/ /2014 Process 20nm planar, 28nm planar 20nm planar Technology 16nm FinFET Logic Cells 1, 955K 1, 160K 4, 407K Block RAM 68Mb 76Mb 115Mb DSP Slices 3, 600 5, 520 2, 880 Peak DSP Performance 1 5, 335s 8, 180 4, 268 (GMAC/s) s Peak Speed (Gb/s) Peak Bandwidth 3 2, 784 2, 086 5, 101 (Gb/s) PCIe Blocks G Ethernet G Interlaken Memory Interface (Mb/s) 1, , I/O Pins 1, , 456 Overall Signal Specialization Performance Processing Overall Performance TABLE III MAXIMUM CAPABILITY OF CURRENT-GENERATION DEVICES Maximum Kintex Virtex Capability 8 UltraScale UltraScale Stratix 10 Introd./Shipm. 2013/ /? Process 20nm planar, 20nm planar Technology 16nm FinFET 14nm TriGate Logic Cells 1, 160K 4, 407K > 4, 000K Block RAM 76Mb 115Mb DSP Slices 5, 520 2, 880 DSP Performance 8, 180 GMAC/s 1 4, 268 GMAC/s 1 > 10, 000 GF LOP/s 2 s Speed (Gb/s) Bandwidth 2, , , 064 (Gb/s) PCIe Blocks G Ethernet G Interlaken 1 9 Memory Interface 6 2, 400 3, 200 (Mb/s) I/O Pins 832 1, 456 Specialization Signal Processing Overall Performance B. Current-generation Devices The comparison of the UltraScale devices to the Altera Stratix 10 FPGA is shown in table III. It is noticeable that the Stratix 10 performs better in all characteristics that are known about the device so far. Only the amount of logic cells is comparable to the Virtex UltraScale device. Even in DSP performance, which is the Kintex UltraScale FPGA is optimized for, the Stratix 10 superior. However, it is important to know that all facts about Altera s Stratix 10 are derived from press releases as the device is not on the market yet and thus there are no final data sheets available. Consequently, the numbers only show what Altera wants the Stratix 10 to be like and not how it will be in the end. The facts about the Xilinx devices come from data sheets, so even though they may be closer to reality, they are also part of marketing material and should be evaluated carefully. V. SUMMARY AND CONCLUSION Due to the More is Better mindset of end-consumers, high performance systems require massive data flow and routing, packet and DSP processing, internal and external memory bandwidth and I/O bandwidth. Xilinx promises to deliver these with their recently introduced UltraScale architecture, which consists of two devices: the Kintex UltraScale (available in TSMC s 20nm planar process technology) and the Virtex UltraScale (available either in TSMC s 20nm planar or 16nm FinFet process technology). There are many improvements on former bottlenecks, especially the interconnect. For example, Xilinx implemented Fast Tracks to provide more direct routes between logic cells. To improve I/O and memory bandwidth, the transceivers were enhanced and include internal gearbox logic. Additionally, there are several BRAM and FIFO improvements. The DSP blocks are wider than within the previous generation and facilitate non-dsp computations to save CLB resources. For better packet processing, Xilinx included hardened Ethernet and Interlaken blocks. Other features are ASIC-like clocking, power management, multi-level security, (re-)configuration and co-optimization with the software. All in all, in contrast to their earlier 7 series, which were differentiated according to price and performance requirements, Xilinx differentiates the UltraScale device families by optimizing them for different tasks. The Kintex UltraScale is superior in signal processing while the Virtex UltraScale FPGA is specialized on processing performance, I/O and memory bandwidth and data throughput. Compared to Altera s Stratix 10 FPGA, the UltraScale devices 1 based on symmetrical filter implementation 2 single-precision, hardened floating point DSP performance 3 Full Duplex 4 x8 Gen3 5 DDR3 6 DDR4 7 [15], [28] [30], [45] [49] 8 [20], [30], [37] [42], [45] [49]

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