Opportunities & Challenges: 28nm & 2.5/3-D IC Design and Manufacturing

Transcription

1 Opportunities & Challenges: 28nm & 2.5/3-D IC Design and Manufacturing Vincent Tong Senior Vice President & Asia Pacific Executive Leader Copyright 2011 Xilinx

2 Agenda Xilinx Business Drivers All in at 28nm & Delivering! 2.5-D & 3-D IC Case Study Summary

3 Xilinx Business Drivers Programmable Imperative Relentless Systems Integration Insatiable Intelligent Bandwidth

4 The Programmable Imperative Accelerates Estimated Chip Design Cost, by Process Node, Worldwide, /22-nm 32-nm 45-nm Design cost ($M) Mask cost ($M) Embedded software ($M) Yield ramp-up cost ($M) 65-nm 90-nm 130-nm 28nm = 2X 45nm Cost > $170 M 180-nm ($ Million) Extreme Costs Limit ASIC & ASSP Viability at 28nm Source: Gartner Page 4

5 Insatiable Bandwidth and Spending We Will Soon Live in a 100 Gbps World By Stacey Higginbotham I Feb.22, 2011, 8:21 PT I 14 Comments China s big data center build-out Sprint announces aggressive LTE 4G rollout for mid-2012 Docomo to ramp network spending following outage France Telecom Orange to increase fiber network spending in 2012 Source: EETimes, Light Reading, Gizmodo. Page 5

6 Trends Driving Insatiable Intelligent Bandwidth Extreme Bandwidth Smart Vision Lane Detection 5X Growth in 5 Years Ubiquitous Computing Embedded Security Everyware The 3 rd Wave in Computing Is It Safe? Source: Ericsson, Adam Greenfield. Page 6

7 The Chameleon Chip: Xilinx FPGAs At the forefront of industry innovation at each process node Page 7

8 Xilinx: All in at 28nm First to Tape Out & Deliver Silicon at 28nm Outstanding Partnership with TSMC Pioneering 3-D IC Technology Leading Edge Processing Sub-systems System to IC Tools & IP to Enable Silicon From Programmable Logic to Programmable System Integration Page 8

9 Delivering Today! Virtex-7 SSIT Test Chip 2010 Virtex-7 500T slice for 7V2000T taped out 4/15/11 7K325T tape out for GS on 7/30/11 7K325T taped out December 10, st in the industry 1st Virtex-7 7VX485T taped out 2/28/11 7K480T taped out 4/27/11 Zynq 1 st EPP tape out 8/10/11 Page 9

10 2.5-D & 3-D IC Case Study Copyright 2011 Xilinx

11 The First Wave of 3-D ICs Perfecting the 3-D chip R. Colin Johnson 10/11/ :31 AM EDT You ve heard the hype: The foundation of semiconductor fabrication will be transformed over the next few years as multistory structures rise up from dice that today are planar. After almost a decade of major semiconductor engineering efforts worldwide aimed at making the structures manufacturable, three-dimensional ICs are poised for commercialization starting next year several years behind schedule.

12 Why Now? Connectivity Capacity Crossovers Logic RAM Package Substrate Page 12

13 BW / Watt Connectivity: Enables High Bandwidth, Low Power Die-to-Die Communication 100x 3D Interconnect 10x SerDes & Standard I/O 1x 10x 100x 1,000x Total Die-to-Die Connections 100x bandwidth/watt advantage over conventional methods Page 13

14 Capacity Beyond Moore s Law Big Single Monolithic Die Multiple Small Die Slices Greater capacity, faster yield ramp Page 14

15 Crossover SoCs with Heterogeneous Die Logic Memory PLD Mixed functions Analog Memory Processor Mixed processes Page 15

16 The Progression of 3D Technology Traditional MCM/PCB Silicon Interposer 2.5D Full 3D Analog RF Passive Logic Memory Flipchip + wire bond 2.5D side-by-side integration with TSVs & silicon interposer Vertical stacking with memory & logic Source: TSMC Page 16

17 Technical Challenges Posed by 3D Active Active 3D Active on Active Vertical Die Stacking RAM Logic Package Substrate Microbump / TSV Thermal TSV-Induced Device Stress corner center Page 17

18 3D versus 2.5D 3D 2.5D Design Flow New Co-Design Evolutionary Testing New Methods Evolutionary Cost High 65nm Interposer Thermal Challenging Evolutionary Device Impact Stress None Reliability Challenging Evolutionary

19 Why FPGA? Technology Column based ASMBL Architecture Large Die Integration Rich Uniform Programmable Interconnect Tens of Thousands of Microbumps Testability Application Domain Telecom 400Gb Ethernet Wide Data path Packet Processing Highly Parallel DSP processing Highest IO BW (1Terabit/sec by 2014) Growing LC capacity (2 M Logic Cells)

20 Harnesses Proven Technology in a Unique Way Passive Silicon Interposer (65nm Generation) 4 conventional metal layers connect micro bumps & TSVs No transistors means low risk and no TSV induced performance degradation Microbumps Access to power / ground / IOs Access to logic regions Leverages ubiquitous image sensor Through-silicon micro-bump technology Vias (TSV) Bridge power / ground / IOs to C4 bumps Coarse pitch, low density aids manufacturability Etch process (not laser drilled) Side-by-Side Die Layout Minimal heat flux issues Minimal design tool flow impact 28nm FPGA Slice 28nm FPGA Slice 28nm FPGA Slice 28nm FPGA Slice Microbumps Silicon Interposer Through-Silicon Vias Package Substrate C4 Bumps BGA Balls Page 20

21 Column-based ASMBL Architecture ASMBLoptimized FPGA slice FPGA Slices Side-by-Side Segmented Routing High Yields Early Silicon Interposer: Silicon Interposer > 10K routing connections between slices ~ 1ns latency Page 21

22 Advantages vs. Large Monolithic FPGAs Capacity and Bandwidth and Power 20W 980K Monolithic FPGA 8W 20W 980K Monolithic FPGA 8W 8W 2 million logic cells 4-layer metal Si interposer with TSV >10,000 inter-die connections 980K Monolithic FPGA 20W 8W 980K Monolithic FPGA 20W 1 1 Virtex T = = 191.5TMACs 2M Watts LC 2 4 Largest Monolithic FPGAs 1.9M 1.2TMACs 112 LE Watts Bandwidth Capacity Power No Equivalent Page 22

23 Virtex-7 HT: Heterogeneous 2.5D Top View Cross Section TSVs 28G SerDes Fabric Interface 13G FPGA 13G 28G FPGA FPGA FPGA 28G Passive Interposers 13G FPGA 13G Yield optimized 13G FPGA 13G Noise isolation 28G SerDes Passive Interposer 2.8Tb/s ~3X Monolithic 16 x 28G Transceivers 72 x 13G Transceivers 650 GPIO 28G process optimized for performance FPGA process optimized for power Page 23

24 Eye Comparison: 2.5D vs. Monolithic 2.5D Virtex-7 28Gbps Other Monolithic 25Gbps Parameter Virtex-7 HT Other Monolithic FPGA Data Rate 28Gb/s 25 Gb/s Data Pattern PRBS31 PRBS7 Eye Opening >2X more Less than ½ Signal Quality Clean Jitter Noisy Page 24

25 Evolutionary Technology SSI Package Standard Monolithic Flip Chip Lid Standard (Cu Ni Plating) Standard (Cu-Ni Plating) TIM Standard (Silicone) Standard (Silicone) ubump Cu Post + Lead free Solder NA Chip to interposer underfill Capillary UF NA Interposer 65 nm Si Technology NA C4 Bump SnPb SnPb C4 Underfill Capillary UF Capillary UF Package substrate Standard (low-cte Core) Standard Page 25

26 The Xilinx 2.5-D Supply Chain FPGA, Interposer, & Package Design 28nm FPGA & Interposer Package Substrate IBIDEN Bump, Die separation CoC attach, & Assembly Final Test of Packaged Part Page 26

27 Summary Staying at the leading edge is not for everyone Close collaboration with the supply chain is a must 3D ICs are here! Significantly changing the semiconductor landscape Challenges remain Technical and business-related 2.5D is here to stay An important & lower risk path Page 27

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