Next-Generation Electronic Packaging: Trend & Materials Challenges. Lai Group R&D ASE

Transcription

1 Next-Generation Electronic Packaging: Trend & Materials Challenges Yi-Shao Lai Group R&D ASE Jun 26, 2010

2 Evolution & Growth of Electronics 2

3 Evolution of Electronic Products Audion Tube (1906) Transistor (1947) IC (1958) Cell Phone Guglielmo Marconi (1898) Motorola (1973) Sharp (2000) Desktop/ Notebook/ UMPC/MID Tabulating Machine (1889) ENIAC (1946) Apple I (1972) T1000 (1985) Digital Consumer Electronics John Baird (1925) RCA (1950) Kodak (1975) 3

4 Cell Phone & PC Market Growth 2,000 1,800 Cell Phone Application Units (M) 1,600 1,400 1,200 1, CAGR = 9.3% 2.9% Digital Video Player Digital Still Camera Digital Audio Player Digital TV Gaming Digital Consumer Electronics % Desktop/ Notebook/ UMPC/MID

5 Current Driving Forces: Function Integration & Ergonomics 5

6 The Great Convergence of 4 Cs Computing PC NB PDA Pen Notepad Pen Tablet Communications Two-way Radio Cellular Phone Wireless Data Paging Car A-GPS Consumer MP3 Game TV Camera 6

7 What Do People Need? Function Integration 7

8 Windows OS vs. PC Sales How Does PC Evolve? Saturated Performance Demand Lean Client with Cloud Computing 8

9 Performance? Wii Takes Lead WIN XBOX 360 PS3 Wii WIN MEMS IMU ~9 (set) WIN Gaming Station Sales 2008 (set) Wii Remote: Accelerometer Optical Sensor Gyroscope (Wii MotionPlus) 9

10 Slowing Adoption of New IC Technology Analog Feature Size (1/2 Pitch) 65 nm 45 nm 32 nm CPU GPU Consumer Logic DRAM 16 nm NAND BB/DSP PC Cell Phone 10

11 Slowing Moore s s Law 10 4 VLSI & ULSI Moore s Law Limit (16 nm?) Computing Power (MIPS/K$) 10 3 Relays 10-6 Vacuum Tube Moore s Law Discrete Transistors Technology s Performance CMOS LSI New Invention PC Technology S Curve Explosive Growth Time/Effort Maturation New IC Technologies Carbon Nanotubes Low-K / High-K (Hf Based) Strain Engineering DRAM PRAM Nanotube RAM Flash: New Architecture Binary Power NanoMEMS Soft Lithography Year

12 End of Moore s s Law: 16 nm? 12

13 Ways of Integration: SoC & SiP 13

14 3-D D Integration: Motivation 14

15 SoC (System-on-Chip) & SiP (System-in-Package) More Than Moore: Diversification More Moore: Miniaturization Source: ITRS (2005) Baseline CMOS: CPU, Memory, Logic 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm.. V Analog/RF SoC: : Set Meal Passives HV Power Sensors Actuators Combining SoC & SiP: : Higher Value Systems SiP: : Buffet Biochips 15

16 A Wide Variety of 3D SiPs to Meet Functionality & Density Requirements Density Sensor I/O Sensor I/O RF Power Low Medium High TSV (Via Last) - Single Die Cost-Competitive Competitive SoC Stacked Die (FC+WB) TSV (Via First) TSV (Via Last) - 2 Die PiP (WB) PiP (FC) PoP (WB) FO-WLP - 2 Die MCP (WB) PoP (FC) EDSi EDS Analog DRAM / NVM Cache Memory CPU Multi-level 3D IC (CPU + Cache + DRAM + Analog + RF + Sensor + I/O) Low Medium High Functionality 16

17 Bright Future of 3D SiPs 1 st Generation LF & TAB Moore s Law 2 nd Generation BGA 0.13 um 90 nm 65 nm 45 nm 32/28 nm 3 rd Generation FC & 3D SiP 4 th Generation Opto/MEMS FC FCBGA LF LK LF ELK LF w/ Si Interposer or Ceramic Substrate IC IC Wireless Interconnect TCP PBGA PoP PoP MapPoP Fan-In PoP Package Size QFP PLCC MCP Stacked Die FC+WB TSV Via Last CIS Via Last BB+ Memory FC PoP Via First CPU + Cache Optical Interconnect MEMS Devices DIP EDS EDS EDSi Stacked EDS PoP SOJ SOP Bumping EU HL LF Au Stud Cu Pillar CoC 8 TSV Stack WLP WLCSP FO-WLP TSV Interposer FO-WLP (Double Sided) FO-WLP MCP FO-WLPoP

18 Evolution of Mobile Phone Phone-call Message Internet GPRS Media Player Video GPS 18

19 Emerging Packaging Materials Issues 19

20 Copper Wire Bonding Great Cost Saving 10%~40% Cost Saving Depending on Package Type Cu or Pd-coated Cu wire Ions Released Forming Gas at EFO (95%N 2 +5%H 2 ) Al Splash Underpad Damage Slow IMC Formation & Growth Cracking after Aging or Moisture Attack HVM Ready for Leadframe & BGA with 20 μm wire Long-term Reliability Fundamental Understanding of Mechanisms 20

21 Underfill Selection for N90/N65 Low-k k Flip Chip g low-k delam hi-pb eutectic Pb-free low-k bump crack Underfill Selection Rules High Tg/High E: Good for bumps Low Tg/low E: Good for low-k Window is small for Pb-free Window can be expanded: Seal rings in chip Bump composition change 21

22 Design for Robust N40/N32 ELK Flip Chip White bumps (ELK crack beneath UBM) observed upon flip chip bond Strategy against white bumps: Stress buffer Flexible foundation Less stiff materials Smaller contact is better Intel Atom Different trends for different bump structures Larger contact is better 22

23 High-Power Flip Chip Solutions T J T C T A θ JC θ CA System Cooling TIM1 Lid 200 Power (W) 100 Grease/Gel Polymer-Solder Hybrid Solder Metal or Metal-carbon Composite Lid Alternative for Cost-Saving? Vapor-chamber Lid 23

24 3D IC Packaging is Arising Through-Silicon Silicon-Via (TSV) Underfill Interconnect (Samsung) Diameter: < 20 μm Risk: Strong Local Heating High Current Density Thermomechanical Reliability Interconnect System High Thermal Conductivity Underfill 24

25 Fundamental Studies Provides Insights Cu 3 Sn Superlattice 80 Atoms Per Unit Cell Extremely Long Single Axis Stiffness Matrix (GPa( GPa) Sym Polycrystalline Modulus: ( ~ ) GPa; Poisson s Ratio: 0.33 Excellent Agreement Nanoindentation Modulus: / 3.63 GPa 25

26 Thank You 26