Enabling An Interconnected Digital World Cadence EDA and IP Update. Jonathan Smith Director, Strategic Alliances June 1, 2017

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1 Enabling An Interconnected Digital World Cadence EDA and IP Update Jonathan Smith Director, Strategic Alliances June 1, 2017

2 IoT Market Definition and Growth Estimates Large and widely varying Known: IoT will include a large mixed-signal component, with complex packaging Cadence Design Systems, Inc. All rights reserved.

3 Cadence Implementation Leadership Technology innovation: fast, smart, and optimized Implementation Fabric Common Engines, UI, and Flows Logical Conformal Electrical Timing, Power PPA Engines Optimization Physical Quantus and DRC Genus Modus FRONT END Innovus PLACE and ROUTE Quantus Tempus Voltus ELECTRICAL SIGNOFF Pegasus DESIGN RULE CHECK Best-in-class core tools Massively parallel for speed and capacity Best PPA and intelligent flows Rapid convergence and ECO Common foundation engines Differentiated productivity Fully integrated mixed signal Cadence Design Systems, Inc. All rights reserved.

4 Cadence Custom IC and PCB Design Leadership Enabling smart product design from start to finish CHARACTERIZATION Liberate Variety CHIP Virtuoso Spectre PACKAGE Allegro Virtuoso BOARD Allegro PSpice OrCAD ANALYSIS Sigrity Market leadership for over 25 years Mixed signal Analog/RF Advanced node (16nm to 5nm) Photonics support Rigid-flex board enablement Differentiated and comprehensive support for IoT, automotive, and aero/defense designs System Design Enablement via an Extensive Ecosystem Cadence Design Systems, Inc. All rights reserved. Advanced packaging In excess of 70 different ecosystem partners

5 Cadence Verification Suite Technology innovation leadership: fast, smart, and optimized Verification Fabric Uniform multi-engine verification VIP VERIFICATION IP vmanager MET RICS Indago DEBUG Perspec SW-DRIVEN TEST JasperGold FORMAL and STATIC Xcelium SIMULATION Palladium Z1 EMULATION Protium S1 FPGA PROTOTYPE Fast: Best-in-class engines Total throughput Metric-driven signoff Application optimized Cloud-centric architecture Smart: Flow-driven engine integrations Optimized: Comprehensive solutions Cadence Design Systems, Inc. All rights reserved.

6 Successful Foundry Node Requires an Ecosystem Strong collaboration history tool enablement and design flows 2015 Digital and Signoff Tools 22FDX enabled 2016 V0.5 22FDX tapeout supported EAD in 22FDX at CDNLive 2017 Phase III of 22FDX reference flow Digital reference flow for 28FDS presented at CDNLive Voltus 28FDS certification presented at CDNLive Cadence Design Systems, Inc. All rights reserved.

7 Samsung-Cadence Collaboration on 28FDSOI Cadence Custom/Analog, Digital and Signoff Tools Achieve Certification on Samsung 28FDS Process Technology Reference flow enables system and semiconductor companies to accelerate delivery of IoT and mixed-signal designs on Samsung s process SAN JOSE, Calif., May 24, 2017 Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its custom/analog tools and fullflow digital and signoff tools have achieved certification for the process design kit (PDK) and foundation library for the Samsung Electronics 28nm fully depleted silicon-on-insulator (FDS), also known as FD-SOI, process technology. The Cadence 28nm FDS reference flow has been certified by Samsung using a quad-core design with the ARM Cortex -A53 processor covering forward body bias (FBB) with a bias controller, a power-gating scheme, UPF2.1 compliance, multi-bit FF optimization, SCAN/PMBIST/ATPG and SI/EM-aware design Cadence Design Systems, Inc. All rights reserved.

8 Custom and Analog Design Digital Implementation and Signoff (RTL to GDS) SOI Advanced-Node EDA Enablement 28FDS Design Capabilities Logic Simulation (Incisive) Synthesis (Genus) Power Analysis (Joules) Test (Modus) Place and Route (Innovus) Timing Analysis (Tempus) Extraction (Quantus) EM/IR Analysis (Voltus) Physical Verification (PVS) Litho Physical Analysis (DFM/LPA) Litho Electrical Analysis (DFM/LEA) Chemical Mechanical Polishing (DFM/CMP) Schematic Editing (Virtuoso VSE) Analog Design Environment (Virtuoso ADE) Layout System (Virtuoso VLS) Circuit Simulation (Spectre APS/XLS) Electrically Aware Design (EAD) EM/IR Analysis (Voltus-Fi) 28FDS Samsung 28FDS Cadence Digital Reference Flow presented at CDNLive Silicon Valley 2017: Fast Ramp to Reap 28FDSOI Benefits Certified Cadence Design Systems, Inc. All rights reserved. Enabled

9 Custom and Analog Design Digital Implementation and Signoff (RTL to GDS) SOI Advanced-Node EDA Enablement 22FDX Design Capabilities 22FDX Logic Simulation (Incisive) Synthesis (Genus) Power Analysis (Joules) Test (Modus) Place and Route (Innovus) Timing Analysis (Tempus) Extraction (Quantus) EM/IR Analysis (Voltus) Physical Verification (PVS) Litho Physical Analysis (DFM/LPA) Litho Electrical Analysis (DFM/LEA) Chemical Mechanical Polishing (DFM/CMP) Schematic Editing (Virtuoso VSE) Analog Design Environment (Virtuoso ADE) Layout System (Virtuoso VLS) Circuit Simulation (Spectre APS/XLS) Electrically Aware Design (EAD) EM/IR Analysis (Voltus-Fi) 12FDX: Cadence and GLOBALFOUNDRIES have started collaborating to support 12FDX node Certified Cadence Design Systems, Inc. All rights reserved. Enabled This slide contains forward-looking statements about Cadence business or products. Actual results may differ materially from the information presented here.

10 Enabling FD-SOI Process Genus Design Exploration Released in December 2016 Innovus Body-Bias Interpolation To be Released by end of May 2017 Tempus Body-Bias Interpolation To be Released by end of May 2017 Voltus Body-Bias Interpolation To be Released by November Cadence Design Systems, Inc. All rights reserved. This slide contains forward-looking statements about Cadence business or products. Actual results may differ materially from the information presented here.

11 project_setup.tcl Block Timing Model Block LEF *IEEE 1801 Power Intent Technology Files Std Cell Libraries RTL SDC DFT Files Block-Level Flow Top-Level Flow *Conformal Low Power Checker Conformal Equivalence Checker Logic Synthesis DFT Insertion Genus Synthesis Solution Quantus QRC Extraction Solution Tempus Timing Signoff Solution post_syn and post_pnr LEC/LP Check Write Abstract LEF Extract Timing Model Timing and SI Signoff Modus ATPG Digital Implementation and In-Design Signoff *Assemble Design Parasitic RC Extraction Power Integrity EMIR Signoff Best-in-Class PPA Optimization Modus Test Solution Innovus Implementation System Physical Verification System Litho Physical Analyzer Voltus IC Power Integrity Solution Cadence Design Systems, Inc. All rights reserved.

12 Cadence Tensilica Processor IP For automotive applications Digital radio and voice command ISO Ready / ISO 9001 Certified Multiple rounds of experience delivering DIAs to automotive licensees Embedded signal processing Shipping in volume; >12 HiFi licensees in automotive Multi-microphone voice command, and noise reduction Multi-channel audio decode and advanced post-processing Acoustic noise cancellation Regenerative power management Battery management Engine control Fusion DSPs introduced 2015, 2016, and 2017 Digital Radio receiver: HD Radio, DAB, DAB+, DRM, T-DMB Cabin environmental control Tensilica HiFi DSPs Tensilica Fusion DSPs ADAS vision processing Telematics connectivity / Radar Traffic sign detection / recognition Advanced Driver Assistance Systems Lane-departure warning Front-collision warning Emergency Services Peer-to-peer smart car networking for intelligent vehicle highway control GPS Shipping in 1 st V2V p from NXP; Wins in future Radar ADAS systems Multiple wins in nextgen ADAS systems Automatic high beam Tensilica Vision DSPs Built-in LTE Modem and Wi-Fi Access Point Tensilica ConnX DSPs Radar/Lidar Cadence Design Systems, Inc. All rights reserved.

13 Cadence Custom and Digital tools Ready for FD-SOI Multi-year collaboration with foundry FD-SOI leaders PDK enablement, tool readiness, design flows in place Enables designers to take optimal advantage of FD-SOI features such as bodybiasing Cadence Design Systems, Inc. All rights reserved.

14 Thank You Cadence Design Systems, Inc. All rights reserved.

15 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

16 Backup Cadence Design Systems, Inc. All rights reserved.

17 GF 22FDSOI Digital Reference Flow Overview The CDNS-GF 22FDSOI Digital Reference Flow is a RTL2GDS2 solution including Synthesis (Genus), Place and Route (Innovus), Parasitic Extraction (Quantus), Static Timing Analysis (Tempus), Power Analysis (Voltus), Formal Verification (Conformal), Test Solution (Modus), Physical Verification (PVS) and DFM (MVS) tools. The flow covers block-level flow and hierarchical multi-bias domain flow. The hierarchical reference flow (P5) uses a bias generator and a processor monitor to generate bias voltage for three bias domains. The CPU, timer block and top-level logic are physically placed in three different domains separated by boundary cells. Global physical cell placement and bias power network routing are performed during floor planning. The block-level reference flow (P2/P4) uses OR1200 RTL with Invecas Standard Cells for official digital reference flow release, with industry-standard CPU RTL is also used for PPA benchmark in P2. The reference flows include both all-in-one make file for RTL-to- GDSII and standalone make file for each step Cadence Design Systems, Inc. All rights reserved.

18 Key Features at Phased Releases P2 first released on Aug 14, 2015 Basic digital reference flow including RC, Innovus, Quantus, Tempus Block level with only FBB cells, external back bias voltage Bias routing to WellTAP cell from external power pins, one BIAS voltage pair (NW, PW), with different BIAS voltages P4 first released on Nov 6, low-power flow with 3 power domains Genus, Conformal, Incisive, and ET are also added to P2 Implementation of Mixed Vt due to various bias conditions Bias routing to WellTAP cell from external power pins, multiple BIAS voltage pairs, with predefined voltage level per domain P5 first released on April 30, 2016 Bottom-up hierarchical low power flow with body bias IP to generate body bias voltage Bias routing to WellTAP cells, multiple BIAS voltage pairs, with different BIAS voltages for different domains Cadence Design Systems, Inc. All rights reserved.

19 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.