Analyzing the Disruptive Impact of a Silicon Compiler

Transcription

1 THE ELECTRONICS RESURGENCE INITIATIVE Analyzing the Disruptive Impact of a Silicon Compiler Andreas Olofsson

2 1947 Source: Wikipedia, Computer Museum

3 2017 Source: AMD

4 Defense Advanced Research Project Agency Mission Arpanet TCP/IP GPS DARPA was #1 funding source for RISC-V s development at Berkeley (PERFECT, POEM) --UC Berkeley Technical Report Image Sources: Google, Wikipedia, UCB Grande Challenge PERFECT & POEM RISC-V

5 Why can t we have this? silicon compiler code

6 DARPA s $100M Silicon Compiler Investment IDEA: No human in the loop mixed signal circuit layout Source: Raspberry Pi POSH: A sustainable open source hardware design ecosystem

7 Academic Partners Commercial Partners University of Michigan University of California at San Diego Stanford Synopsys Sandia National Laboratories Cadence University of Texas Dallas Cairo University Carnegie Mellon University University of Virginia Boston University UIUC Princeton University University of Utah University of Southern California University of Washington Yale UT Austin Intel Qualcomm Xilinx Global Foundries Northrop Grumman Lockheed Martin MOSIS NVIDIA Analog Devices UIUC Purdue University Brown University jitx LeWiz ARM

8 Today s Hardware Layout A Better Way Training Data Training IDEA Unified Layout Generator Models Chip Package Board Chip 9 months Package 3 months Board 3 months 24 hours

9 The OpenRoad Open Source Silicon Compiler No-Human-In-The-Loop RTL to GDSII Compiler Silicon, Packaging, and Board Targets 24hr Turnaround Free and open source! UCSD Brown U of Michigan UT Dallas U of Minnesota Brown UCSD Michigan UT Dallas Michigan Brown UIUC UCSD/UTD UCSD UTD/UIUC Qualcomm ARM UTD/UIUC

10 Hardware Development Software Development User Content Two layer stack Chip Company A Chip Company B Chip Company C IP Vendors Chip Company D MemCache Thrift Cassandra Trillion Dollar Company Open Source Software Stack LINUX Apache PhP Jenkins $15B+ Open Source Infinite Layer Stack

11 High Performance Multicore RISC-V High Quality Digital Circuit Library Posh Open Source Hardware Scalable Formal Analysis Tools Analog Circuit Library FPGA Chips & Tools Open source culture

12 Tracking IDEA & POSH Progress 2018 Program Kickoff (Jun) 2018 First Integration Exercise (Jan) Source: Raspberry Pi Alpha code drop (Jun) A usable Silicon Compiler 50% PPA A great Silicon Compiler 100% PPA

13 So What?

14 ASICs Ops/ Joule 1000x DSP GPU CPU Flexibility FACT: Specialization is often the ONLY way to meet non-trivial Size, Weight, and Power system constraints

15 $1B SW $100M HW $10M FACT: High cost of ASICs Negative ROI Unreachable applications

16 $40,000,000 Status Quo TOTAL COST $4,000,000 $400,000 $40,000 A silicon compiler will enable building one-of-a-kind (N=1) million transistor chips for $500! $4,000 $ ,000 10, ,000 1,000,000 10,000, ,000,000 1,000,000,000 UNIT VOLUME (N) Assumptions: Perfect IP reuse/generation Extreme MPW Cost Sharing Free silicon compilers Standardized package & test

17 IDEA: THE MISSING PIECE! No-Human-In-The Loop Layout Chip Layout Army Massive cloud computing No-touch Foundry A General Purpose Silicon Compiler: Removes expertise barrier to democratizes access to silicon technology Replace finite human time with machine cycles Outcome: Makes it practical to specialize for N=1 Reach beyond the horizon, across the chasm,.. Source: Global Foundries, Google

18 N=1 (Extreme Energy Constraints, DARPA N-ZERO) Power Consumption 100 mw 10 mw 1 mw 100 µw 10 µw 1 µw 100 nw 10 nw Magnetic field sensor UNB Transceiver Microphone and accelerometer 1 MHz, 32-bit M4 processor IEEE ba wake-up radio receiver Wake-on-sound or motion sensors 10-year lifetime target Sleeping processors, sleeping radios, 64 kb memory and N-ZERO 20 (minutes) 3 (hours) 1 (day) 12 (days) 4 (months) 3.4 (years) 34 (years) 340 (years) Lifetime from a 30 mahr button cell PV Cells 3D Magnetic Antenna MEMS Tra nsducer Qua rtz Crystal Battery Sound Hole 3D-Printed Custom Lid Sta cked ICs Sources: ERI Summit, University of Michigan

19 N=1 (Extreme Size Constraints) Original Intel ,300 transistors Fits in a cell at 3nm Image Sources: Intel, CGTrader There is no Moore s Law for the physical world Biological and physical laws are constant Specialization needed to reach limits

20