CMSC Computer Architecture Lecture 1: Introduction. Prof. Yanjing Li Department of Computer Science University of Chicago

Transcription

1 CMSC Computer Architecture Lecture 1: Itroductio Prof. Yajig Li Departmet of Computer Sciece Uiversity of Chicago

2 Lecture Outlie Meet ad greet Computer architecture: overview ad perspectives Course ifo ad logistics Basic Cocepts 2

3 Who Are We? Istructor: Prof. Yajig Li Research ad Teachig Computer architecture ad systems Robust system desig (resiliece, security) Emergig techologies Before UChicago Itel Labs (Seior Research Scietist) Staford (PhD i EE) CMU (MS i Math, BS i ECE & CS) 3

4 Who Are We? Teachig assistat Rya Wu 2 d year CS PhD Grader Wesley Kelly CS222 aut16 alum 4

5 Your Tur 5

6 Computer Architecture The sciece ad art of desigig, selectig, ad itercoectig hardware compoets ad desigig the hardware/software iterface to create a computig system that meets fuctioal, performace, eergy cosumptio, cost, ad other specific goals. 6

7 Computer Architecture: System s Perspective Algorithm Applicatios Rutime System (VM, OS, MM) ISA (Architecture) Microarchitecture Logic Circuits Devices Programmer s view of how a computer system works CMSC This Course Digital desig How to use logic gates ad wires to meet specific desig goals? 7

8 Computer Architecture Drivig Advaces Microprocessors sigle-chip computers are the buildig blocks of the iformatio world. Their performace has grow 1,000-fold over the past 20 years, drive by trasistor speed ad eergy scalig, as well as by microarchitecture advaces that exploited the trasistor desity gais from Moore s Law. Borkar ad Chie, The future of Microprocessors, Commuicatios of the ACM,

9 Moore s Law Moore, Crammig more compoets oto itegrated circuits, Electroics Magazie,

10 Number of trasistors o a itegrated circuit doubles ~ every years Image source: Wikipedia 10

11 Deeper Isights: Deard Scalig Every geeratio, per trasistor Area: dow 50% Speed (freuecy): up 40% Power: dow 50% Every geeratio, whole chip (same area) 2X trasistors 40% faster Power stays costat Deard, et al., Desig of Io-Implated MOSFET s with Very Small Physical Dimesios, IEEE Joural of Solid State Circuits,

12 ~ 1000X Faster Computers i 3 Decades? 10, Fre (Mhz) 1980 Year 2015 Techology Scalig + Microarchitecture Advaces Image source: cpudb, staford 12

13 Microarchitecture: before early/mid-2000 s Pushig for sigle-core performace Faster memory access O-chip caches Aside: why is memory slow i the first place? Exploitig istructio level parallelism (ILP), i.e., execute as may istructios as possible simultaeously withi a sigle stream of executio Pipeliig Brach predictio Superscalar Out-of-order processig Deep pipelie Image source: Itel 13

14 Microarchitecture: after early/mid-2000 s Focus o program-level parallelism Multi-core era Proliferatio of CMP (chip multi-processor) Image source: Itel 14

15 Why Sigle-Core to Multi-Core? Sigle-core hits power wall Well beyod what s allowed by techology scalig More complexity à more trasistors à more power Higher clock rate à more switchig à more power What limits power? Coolig! No more large beefits from ILP [Olukutu Queue 05] Degrees of ILP is limited (depedecy) Dimiishig returs for exploitig ILP (complexity) 15

16 Why Sigle-Core to Multi-Core? Parallelism to improve performace Latecy (executio time) vs. throughput Parallelism to obtai power beefits A example: which sceario cosumes less power? A task takes time t to ru o core A Assume the task ca be divided ito 2 idepedet parts; Now take 2 core As, reduce the clock rate by half o both Power beefits of multi-core Power is proportioal to clock rate (liear) Also, lower clock rate à lower voltage (liear) Ad power is proportioal to the suare of voltage (skippig a few details here) 16

17 Multi-Core: Caveats For computer architects: harder or easier? For programmers: more difficult to program! But, the beefit is worth it How to mitigate these issues? 17

18 Aother Major Paradigm Shift, NOW 10,000 Power wall 10 Fre (Mhz) 1980 Year 2015 Image source: cpudb, staford 18

19 Aother Major Paradigm Shift, NOW Moore s Law is alive (still) but Deard scalig has eded Aside: whe will Moore s Law ed? Applicatio demads more E.g., big data (IoT, machie learig, ) User expects more Loger battery life, lighter, faster, smarter As a result, may walls Power / eergy efficiecy wall Memory wall Complexity wall Reliability wall Programmability wall Image source: Itel 19

20 Microarchitecture: Future That is, what are the active research topics today? Heterogeeous architecture GPUs, FPGAs, accelerators Robust ad secure systems Eergy efficiet computig Data itesive computig Brai ispired computig Architectures embracig ew techologies Carbo aotube, photoic, uatum It s a excitig time to study computer architecture! Image source: Itel 20

21 Why Study Computer Architecture? Eable better systems Faster, cheaper, smaller, more reliable, By exploitig advaces ad chages i uderlyig techology/circuits By takig advatage of applicatio characteristics Eable ew computig capabilities Eable better solutios to problems Software iovatio is built ito treds ad chages i computer architecture Uderstad why computers work the way they do 21

22 But I m CS, Math, Eco Why should I study hardware?

23 A Note o Hardware vs. Software You will be much more capable if you master both hardware ad software (ad the iterface betwee them) Ca develop better software if you uderstad the uderlyig hardware Ca desig better hardware if you uderstad what software it will execute Ca desig a better computig system if you uderstad both This course covers HW/SW iterface ad microarchitecture We will discuss tradeoffs ad how they affect software 23

24 What Will You Lear? Fudametal priciples ad tradeoffs i desigig the hardware/software iterface (ISA) ad major compoets of a moder microprocessor How to desig, implemet, ad evaluate a fuctioal moder processor Quarter-log lab assigmets C simulatio Focus is fuctioality first (the, o how to do eve better ) How to thik critically ad broadly Novel, out-of-the-box ideas that ca chage the world 24

25 Lecture Topics Fudametal priciples ad desig tradeoffs of processor, memory, ad platform architectures Buzz words ISA uarch, Cotrol, datapath ILP Pipelie, deep pipelie, superscalar, OOO Parallel processig, CMP Cache, virtual memory, mai memory, memory hierarchy I/O (Schedule subject to chage) 25

26 Takeaways Computer architecture is ot easy May walls to couer May thigs to cosider i desigig a ew system Software, techology, social treds Need to have good ituitio/isight ito ideas/tradeoffs This course: a decet amout of work But, it is fu ad very techically rewardig Ad, it eables a great future 26

27 Prereuisites C CMSC Systems Virtual memory Assembly 27

28 Textbook Computer Orgaizatio ad Desig: ARM Editio, Patterso ad Heessy (Reuired) Earlier editios of the textbook is OK Mai differece: LEGv8 vs. MIPS You eed to fid refereces to LEGv8 ISA Used i lectures, exams You eed to fid the appropriate chapters to read 28

29 Where to Get Up-to-date Course Ifo? Website Lecture otes Lab materials Exam practice problems Piazza You eed to sig up piazza.com/uchicago/fall2017/cmsc

30 Lecture ad Lab Locatios, Times Lectures TuTh 2:00-3:20am Ryerso 251 Attedace is for your beefit ad is therefore importat Labs Wed 2:30pm-3:50pm; 4:00pm-5:20pm; 5:30pm-6:50pm CSIL Attedace is ot reuired (me or Rya will ot be i labs) Separate lab assigmet review sessios will be held by Rya (look out for Piazza aoucemets ad check course webpage) 30

31 How Will You Be Evaluated? Lab assigmets: 50% Exam I: 25% Exam II: 25% 31

32 Lab Assigmets 4 labs, 50% of your grade (+1 extra credit lab) They build o top of each other! These will take time Start early ad work hard Labs will be doe i groups of 2 Fid your parter ow! Late submissio 24 hours late for a 10% pealty hours late for a 20% pealty Not accepted after 48 hours 32

33 Exams Two exams (25% of your grade each) Exam I: 11/02 (Thursday), i class Exam II: 11/28 (Tuesday), i class I will hold review sessios ad lots of office hours before each exam No make-up exams, except for exteuatig situatios See course website for examples, or come see me NOW Come see me if you have a letter from Studet Disability Services documetig accommodatios for exams or other work 33

34 Cheatig ad Academic Dishoesty Absolutely o form of cheatig will be tolerated Cheatig à Failig grade ad more (o exceptios) Official college rules Specifically, for labs, DO NOT, -- copy work (eve oe lie) from aother group's assigmet or file. -- copy work (eve oe lie) from a published source without credit (ad permissio from istructor). -- led aother group your assigmet. -- look at aother group s workig code to fix your problem -- or trasfer ay of your files to aother studet who s ot your lab parter. If you have a bug, you may ask a studet who has gotte farther i the lab to help you fid your mistake. You may ot look at his/her project if that studet is ot your lab parter. 34

35 Gettig help We ll do our best to help Office hours Lab assigmet review sessios Piazza We aim to respod as uickly as we ca Note: do ot post code publicly o Piazza 35

36 How to Ask for Help Start ad ask early Show your efforts ad tell us the details it does t work vs. I tried X, but got Y, the tried X Help us help you sv commits so far But agai, do t post code publicly o Piazza Keep tryig We will put you o the right path, ot do the work for you 36

37 What Do I Expect From You? Lear the material thoroughly Ask uestios ad participate i lectures Start early do ot procrastiate Time maagemet is very importat Provide feedback O labs, lectures, office hours 37

38 Up-comig Assigmets Lab 0: sv setup (out today) Same as 154 Your grade does t cout Your chace to check that the submissio system is workig Lab1 Out: 9/28 (this Thursday); Due: 10/10 (Tuesday, 2 weeks from today) A fuctioal C-level simulator for a subset of the ARMv8 ISA Start early! 38

39 Two Make-up Lectures I am travelig o Oct. 19 th ad Oct. 31 st Reschedulig lectures o Oct. 13 th ad Oct. 27 th (Friday) I will sed out a survey to get the best time slots Exam I review o Oct. 27 th (so you will have plety of time to study) 39

40 Fudametal Cocepts 40

41 What is A Computer? Processig cotrol (seuecig) datapath Memory (program ad data) I/O 41

42 The Vo Neuma Model Also called stored program computer (istructios i memory). Two key properties: Stored program Istructios stored i a liear memory array Memory is uified betwee istructios ad data The iterpretatio of a stored value depeds o the cotrol sigals Seuetial istructio processig Whe is a value iterpreted as a istructio? Oe istructio processed (fetched, executed, ad completed) at a time Program couter (istructio poiter) idetifies the curret istr. Program couter is advaced seuetially except for cotrol trasfer istructios 42

43 The Vo Neuma Model Q: Is this the oly way that a computer ca operate? A: No. Qualified aswer: But, it has bee the domiat way i.e., the domiat paradigm for computig for N decades 43

44 The Vo Neuma Model All major istructio set architectures today use this model x86, ARM, MIPS, SPARC Udereath (at the microarchitecture level), the executio model of almost all implemetatios (or, microarchitectures) is very differet Pipelied istructio executio: Itel uarch Multiple istructios at a time: Itel Petium uarch Out-of-order executio: Itel Petium Pro uarch Separate istructio ad data caches But, what happes udereath that is ot cosistet with the vo Neuma model is ot exposed to software Differece betwee ISA ad microarchitecture 44

45 ISA vs. Microarchitecture ISA (Istructio Set Architecture) Agreed upo iterface betwee software ad hardware SW/compiler assumes, HW promises What the software writer eeds to kow to write ad debug system/user programs To optimize SW: uarch kowledge helps Microarchitecture (uarch) Implemetatio of a ISA uder specific desig costraits ad goals Not visible to the software Computer architecture: ISA, uarch Microprocessor: ISA, uarch, circuits Algorithm Program OS ISA Microarchitecture Circuits Electros 45

46 ISA vs. Microarchitecture Implemetatio (uarch) ca vary as log as it satisfies the specificatio (ISA) x86 ISA has may implemetatios: 286, 386, 486, Petium, Petium Pro, Petium 4, Core, Microarchitecture usually chages faster tha ISA Few ISAs (x86, ARM, SPARC, MIPS, Alpha) but may uarchs Why? 46