Roadmap Benefits Past, Present and Future

Transcription

1 Roadmap Benefits Past, Present and Future Paolo Gargini Chairman ITRS2.0 Fellow IEEE, Fellow I-JSAP Intel Fellow ( ) 1

2 Second Update of Moore s Law Log 2 of the number of components per integrated function X/Year 2X/2Year Year International Electron Device Meeting, December

3 Moore s Law and Dennard s Scaling Laws Convergence => 30% LINEAR FEATURE REDUCTION S=0.7 50% 50% AREA READUCION GENERATION TO GENERATION 3

4 Phase 1 First Age of Scaling (Self-aligned Silicon Gate) 4

5 IC Industry at a Glance ( ) Driver Cost/transistor -> 50% Reduction How 2x Density/2 years (Moore) Method Geometrical Scaling (Dennard) 5

6 Gate Dielectric Scaling 4 You Are Here! Gate 1.2nm SiO 2 Tox equivalent (nm) Silicon substrate Monolayers 1997 NTRS From My Files 6

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8 1998 ITRS Update Participation extended to: EECA, EIAJ, KSIA, TSIA at WSC on April 23,1998 1st Meeting held on July 10/11,1998 in San Francisco 2nd meeting held on December 10/11,1998 at SFO 50% of tables in 1997 NTRS required some changes 1998 ITRS Update posted on web in April 1999 Tutorial for SEMI 8

9 ITRS 1.0 9

10 Phase 2 Second Age of Scaling (Equivalent Scaling) 10

11 The Ideal MOS Transistor Metal Gate Insulator Source Drain Fully Surrounding Metal Electrode Fully Enclosed, Depleted Semiconductor High-K Gate Insulator Band Engineered Semiconductor Low Resistance Source/Drain From My Files 11

12 IC Industry at a Glance (2003->2021) Driver Cost/transistor-> 50% Reduction How 2x Density/2 years (Moore) Method Equivalent Scaling ( ITRS1.0) 12

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15 Incubation Time n Strained Silicon 1992->2003 n HKMG 1996->2007 n Raised S/D 1993->2009 n MultiGates 1997->2011 Metal Gate Insulator Source Drain 1998 ~ years 15

16 NRI Funded Universities Finding the Next Switch Notre Dame Purdue Illinois-UC Penn State Michigan UT-Dallas Cornell GIT SUNY-Albany GIT Harvard Purdue RPI Columbia Caltech MIT NCSU Yale UVA TUNNEL FET GRAPHENE SPIN LOGIC UC Los Angeles C Berkeley UC Irvine UC Sana Barbara Stanford U Denver Portland State U Iowa SPIN GRAPHENE UT-Austin Rice Texas A&M UT-Dallas ASU Notre Dame U. Maryland NCSU Illinois UC Over 30 Universities in 20 States Columbia Harvard Purdue UVA Yale UC Santa Barbara Stanford Notre Dame U. Nebraska/Lincoln U. Maryland Cornell Illinois UC Caltech UC Berkeley MIT Northwestern Brown U Alabama 16

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19 Technology Node Scaling 14 Today s Challenge Technology Node (nm) ITRS 19

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21 Vertical Logic Architecture 21

22 Phase 3 Third Age of Scaling (3D Power Scaling) 22

23 IC Industry at a Glance (2021->203X) Driver Cost/transistor & power reduction How 2x Density/2 years (Moore) Method 3D Power Scaling (ITRS2.0) 23

24 The Different Ages of Scaling (Different methods for different times) ① ① ② ① ③ ① Geometrical Scaling ( ) Reduction of horizontal and vertical physical dimensions in conjunction with improved performance of planar transistors Equivalent Scaling (2003~2021) Reduction of only horizontal dimensions in conjunction with introduction of new materials and new physical effects. New vertical structures replace the planar transistor 3D Power Scaling (2021~203X) Transition to complete vertical device structures. Heterogeneous integration in conjunction with reduced power consumption become the technology drivers 24

25 Beyond 2020 O P S Y S T E M Customized Functionality Outside System Connectivity System Integration Heterogeneous Integration More than Moore A P P L E T S More Moore Beyond Moore ITRS

26 21th Anniversary of TRS 1991 Micro Tech 2000 Workshop Report NTRS 1994NTRS 1997NTRS Europe Japan Korea Taiwan USA 1998 ITRS Update 1999 ITRS 2000 ITRS Update 2001 ITRS 2002 ITRS Update 2003 ITRS 2004 ITRS 2006 ITRS Update 2005 ITRS Update 2007 ITRS 2008 ITRS Update 2009 ITRS 2010 ITRS Update 2011 ITRS 2012 ITRS Update 2013 ITRS 26

27 ITRS 2.0 ( ) 27

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29 Q: How do we get back to exponential performance scaling? IEEE Rebooting Computing Initiative 29

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31 US Initiatives Continuous Scaling NTRS FCRP NNI NRI End of Traditional Scaling in Sight Launch of USG Nanotechnology Agreement on US research coordination Equivalent Scaling Goes into Production High-k/Metal Gate. FinFET ~2021 Global Semiconductor Industry Moore s Law Continues International ITRS 1.0 International Nanotechnology Investments INC ITRS 2.0 Equivalent Scaling Research Launch of Eu/Japan Nanotechnology Yearly Conference on Nano Eu/Japan/US 3D Power Scaling 31

32 US Initiatives Rebooting Computing NSCI Computer industry Close to frequency and power limits Global Computer Industry Moore s Law Continues 3D Power Scaling IEEE RC ITRS 2.0 International Rebooting Computing Investments 32