Introduction to CMOS VLSI Design. Programmable Logic. Peter Kogge Fall 2015

Transcription

1 Introduction to MOS VLSI Design Programmable Logic Peter Kogge Fall 2015 Includes lecture slides by David Harris, Harvey Mudd ollege Programmable Logic Slide 1 Outline Gate rray and Sea of Gates PL FPG Programmable Logic MOS VLSI Design Slide 2 1

2 Sea of Gates Programmable Logic MOS VLSI Design Slide 3 Sea of Gates ctually Sea of Transistors Prior standard cell design had 2 rows of diffusion With taps to Gnd and Vdd to define sources nd metal wires to connect drains nd Poly going vertical What if we design long string of transistors on shared diffusion With room for contacts to metal Then changing only metal masks changes logic function Programmable Logic MOS VLSI Design Slide 4 2

3 Eample: ~ We implement a very long string ut may want multiple smaller strings Get it by forcing transistors in break off. MOS VLSI Design Sea of Gates as a Stick Figure Lets do + D Programmable Logic MOS VLSI Design Slide 6 3

4 Programmable Logic rrays (PL) Programmable Logic MOS VLSI Design Slide 7 Programmable Logic N Input its Programmable Logic M Output its Goal: design Logic once, but be able to change without total redesign There are M*2 2N different functions from N to M bits Two programming times In final stages of design Dynamically in the field Programmable Logic MOS VLSI Design Slide 8 4

5 ommon pproach Epress each output bit as a sum (OR) of products (ND) N Input its called Literals Generate P different Products of inputs ND plane P bits called minterms Generate m different Sums of inputs Or plane M Output its Programmable Logic MOS VLSI Design Slide 9 Eample Full adder: 3 input bits a, b, c 2 output bits s, cout s = abc + ~a~bc + ~ab~c + a~b~c cout = abc + ab + ac + bc There are 7 product terms abc, ~a~bc, ~ab~c, a~b~c, ab, ac, bc Each output is OR of 4 of these One term is reused twice Programmable Logic MOS VLSI Design Slide 10 5

6 If we invert the inputs to the NDs we can replace by NORs opyright 2011 Pearson Education, MOS Inc. Publishing VLSI Design as Pearson ddison-wesley Equivalent to a NOR Question: why choose NORs opyright 2011 Pearson Education, MOS Inc. Publishing VLSI Design as Pearson ddison-wesley 6

7 PLs with NOR Gates ND plane: P NOR gates Each with 2N possible inputs input[k] and not(input[k]) Programming: specify which subset of possible inputs to use for each product OR plane: M NOR gates Each with inverter on output Each with P possible inputs Programming: specify which subset of possible minterms to use for each sum Programmable Logic MOS VLSI Design Slide 13 ND plane: place a where minterm uses negation of column 2N olumn Wires N Inputs P Minterm Outputs M Outputs OR plane: place a where output uses minterm opyright 2011 Pearson Education, MOS Inc. Publishing VLSI Design as Pearson ddison-wesley 7

8 Place a transistor wherever there is a in prior figure opyright 2011 Pearson Education, MOS Inc. Publishing VLSI Design as Pearson ddison-wesley MOS VLSI Design 8

9 opyright 2011 Pearson Education, MOS Inc. Publishing VLSI Design as Pearson ddison-wesley Field Programmable Logic rray Programmable Logic MOS VLSI Design Slide 18 9

10 FPGs T N TIME load a string of bits into device its do several things onfigure each of many onfigurable Logic locks (L) to perform some specific logic function onfigure which outputs of which Ls are connected to inputs of which other Ls onfigure which pins on device are connected to which L Programmable Logic MOS VLSI Design Slide 19 MOS VLSI Design 10

11 it More Programmable Logic MOS VLSI Design Slide 21 Shift in Programming Data Look Up Table (LUT) 2 N bit Latch N Input its Multipleor 1 it Out To Get M outputs, Use M LUTs Programmable Logic MOS VLSI Design Slide 22 11

12 If we used a 16 bit SRM, that s 6*16+row decoders, sense amps an we do better? MOS VLSI Design lternative 4-Input LUT How Many Transistors? In onfig Reg In pass tree In total Programmable Logic MOS VLSI Design Slide 24 12

13 Switch Matri Long Wires go further before hitting switch lock Each here is one of these Each switch block is array of Switches Si configuration bits allow complete freedom in connecting,,, D, with signals that can go in either direction. Programmable Logic MOS VLSI Design Slide 25 Notation for Net Slide 3-Input LUT with inputs,, ant Output If X ed, then horizontal and vertical wires connected If not, horizontal and vertical wires are separate Switch o: Each circle can be programmed for any of the 64 possible thru connections Programmable Logic MOS VLSI Design Slide 26 13

14 14 MOS VLSI Design Sea of 3-Input LUTs Programmable Logic Slide 27 This layout is Totally Madeup MOS VLSI Design Let s Do ST + ~SVW + ~T~U~W Programmable Logic Slide 28 S T V W

15 More Typical 4-input 1 Output L oth of these mues are driven by other configuration bits Programmable Logic MOS VLSI Design Slide 29 Typical Tool hain Programmable Logic MOS VLSI Design Slide 30 15

16 Recent Product Table Programmable Logic MOS VLSI Design Slide 31 Worksheets Programmable Logic MOS VLSI Design Slide 32 16

17 17 MOS VLSI Design Programmable Logic Slide 33 MOS VLSI Design Programmable Logic Slide 34