Lecture 3. VHDL Design Units and Methods. Notes. Notes. Notes

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1 Lecture Entity, Architecture, and Components Examples of Combinational Logic Hands-on in the Laboratory BTF Digital Electronics 2 Mar. 06, 2015 Bern University of Applied Sciences Agenda Rev. ec17bd.2 The basic elements are AND, OR, NOT, EXOR, NAND, NOR Such components have a library declaration LIBRARY IEEE; To have them available include the corresponding package (STD_LOGIC_1164). for the standard package of the library IEEE is shown below: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; of an AND File name : exand-entity.vhdl Example : AND (entity) 1 LIBRARY ieee; 2 USE ieee.std_logic_1164.all; 4 ENTITY ExAnd is 5 Port( 6 AxDI : IN std_logic; 7 BxDI : IN std_logic; 8 FxDO : OUT std_logic 9 ); 10 END ExAnd; Figure: Ex : Entity Block Rev. ec17bd.

2 Some More Entity Examples Example : NOT (entity) 1 LIBRARY ieee; -- Library to include 2 USE ieee.std_logic_1164.all; -- Package of library 4 ENTITY ExNot is -- ENTITY block start 5 Port( -- PORT statement start 6 AxDI : IN std_logic; -- A input signal 7 FxDO : OUT std_logic -- A output signal 8 ); -- PORT end 9 END ExNot; -- ENTITY block end 1 type std_ulogic is ( 2 U, -- Uninitialized X, -- Forcing Unknown 4 0, -- Forcing 0 5 1, -- Forcing 1 6 Z, -- High Impedance 7 W, -- Weak Unknown 8 L, -- Weak 0 9 H, -- Weak Don t 11 ); A nine-value resolved logic type std_logic is not a part of the VHDL standard. It is defined in IEEE Std Rev. ec17bd.4 Figure: NAND based 2 to 1 Mux Some Vector Based Entities Example : AND 4 Bit (entity) 1 LIBRARY ieee; 2 USE ieee.std_logic_1164.all; 4 ENTITY ExAnd_4 is 5 Port( 6 AxDI : IN std_logic_vector( downto 0); 7 BxDI : IN std_logic_vector( downto 0); 8 FxDO : OUT std_logic_vector( downto 0) 9 ); 10 END ExAnd_4; std_logic_vector(7 downto 0); --7th bit is MSB and 0th bit is LSB here std_logic_vector(0 to 7); --0th bit is MSB and 7th bit is LSB here Rev. ec17bd.5 Some Vector Based Entities What to do when we would like to create a more generic component There is the possibility of specifying generics that are used for making components more adaptable. The generic should have a default specification that can be overwritten when instantiating the component. Example : Mux 4 to 1 generic (entity) 1 LIBRARY ieee; 2 USE ieee.std_logic_1164.all; 4 ENTITY ExMux_4_G is 5 GENERIC( 6 VECTOR_WIDTH : INTEGER := 8 7 ); 8 Port( 9 AxDI, BxDI, CxDI, DxDI : IN std_logic_vector(vector_width-1 downto 0) ; 10 Sel1xSI, Sel2xSI : IN std_logic; 11 DxDO : OUT std_logic_vector(vector_width-1 downto 0) 12 ); 1 END ExMux_4_G; Rev. ec17bd.5

Mux Exercises Exercise : Entity of 4 to 1 Mux Write the entity of a 4 to 1 multiplexer. Which libraries are required? What are the statements used? Use the syntax introduced.

6 Summary to the Interface We know the source code file block LIBRARIES: What libraries to use and which packages to include to have language definitions like standard logic types and basic logic

How can we use this information in hardware description? To make designs more understandable and maintainable, a design is typically decomposed into several blocks.

3 Mux Exercises Exercise : Entity of 4 to 1 Mux Write the entity of a 4 to 1 multiplexer. Which libraries are required? What are the statements used? Use the syntax introduced. Figure: Logic Diagram 4 to 1 Mux Rev. ec17bd.6 Summary to the Interface We know the source code file block LIBRARIES: What libraries to use and which packages to include to have language definitions like standard logic types and basic logic functions available. We know the source code file part ENTITY: Describes the function unit, its interface (direction, type etc.) to the outside-world. How can we use this information in hardware description? To make designs more understandable and maintainable, a design is typically decomposed into several blocks. These blocks are then connected together to form a complete design. Each block in VHDL is analogous to an off-the-shelf part and is called an entity. The entity describes the interface to that block and a separate part associated with the entity describes how that block operates. description is like a pin description, specifying the inputs and outputs to the block. Let s analyze an example of a latch entirely. Rev. ec17bd.7 The Latch Example Example : Latch Entity 1 library ieee; 2 use ieee.std_logic_1164.all; 4 entity Latch is 5 6 port ( 7 SetxDI, RstxDI : in std_logic; 8 QxDO, QxDLO : out std_logic 9 ); end Latch; Example : Latch Architecture 1 architecture dataflow of Latch is 2 signal QxDN, QxDNL : std_logic; begin -- architecture dataflow 4 5 QxDN <= RstxDI nor QxDNL; 6 QxDNL <= SetxDI nor QxDN; 7 8 QxDO <= QxDN; 9 QxDLO <= QxDNL; end dataflow; The Library section includes the standard logic package of a Set/Reset Latch Ports of the same mode and object can be grouped together The second part of the Latch is a description of how it works. The first line of the declaration indicates that this is the definition of a new architecture called dataflow and it belongs to the entity named Latch. This example uses the data flow approach which is discussed later. Rev. ec17bd.8

4 The internals of an element Example : VHDL Architecture 1 architecture <MODEL_NAME> of <ENTITY_NAME> is -- start of architecture statement 2 -- This part is called the declarative 4 -- section of an architecture 5 -- here goes signals and type defs 6 -- component declarations etc. 7 8 begin -- architecture behavior (start of descriptive section) This part is called descriptive section of an architecture hre goes your component model 1 -- it can be behavioral, data-flow, or structural end <MODEL_NAME>; -- end of architecture statement Rev. ec17bd.9 Signals, Assignment, Concurrency Example : Concurrent Signal Assignment 1 architecture dataflow of <ENTITY_NAME> is 2 -- declaration of signal objects among others e.g. constants -- <OBJECT_TYPE> <OBJECT_NAME> : <DATA_TYPE>; 4 signal MyTestSignalAxD : std_logic; 5 signal MyTestSignalBxD : std_logic; 6 7 begin -- architecture behavior description of functional model <TARGET> <= <EXPRESSION>; 11 MyTestSignalAxD <= MyInputAxDI and MyInputBxDI; 12 1 MyTestSignalBxD <= MyTestSignalAxD or MyInputBxDI; the expression above is the same as MyTestSignalBxD <= (MyInputAxDI and MyInputBxDI) or MyInputBxDI; Signals are software representations of wires The brackets are used to prioritize and nest sub-expressions All statements are concurrent to each other NO SEQUENTIAL execution -- think hardware whise 22 2 end dataflow; Rev. ec17bd.10 The dataflow paradigm In the data flow approach, circuits are described by indicating how the inputs and outputs of built-in primitive components (ex. an and gate) are connected together. In other words we describe how signals (data) flow through the circuit. A signal assignment statement describes how data flows from the signals on the right side of the <= operator to the signal on the left side. The right side of the <= operator is called an expression. The value of the expression is determined by evaluating the expression. Evaluating the expression is performed by substituting the values of the signals in the expression and computing the result of each operator in the expression. Exercise : S/R Latch Draw the gate diagram of the described S/R Latch Rev. ec17bd.11

5 The 4 to 1 Mux Architecture - Implicit Process Example : Mux 4 to 1 - pure logic 1 ARCHITECTURE purelogic OF ExMux_4_1 IS 2 BEGIN DxDO <= ( AxDI AND (NOT Sel1xSI AND NOT Sel2xSI) ) OR 4 ( BxDI AND (NOT Sel1xSI AND Sel2xSI)) OR 5 ( CxDI AND (Sel1xSI AND NOT Sel2xSI)) OR 6 ( DxDI AND (Sel1xSI AND Sel2xSI)); 7 END purelogic; Implicit process Dataflow method -> basic logic gates Fully concurrent implementation Rev. ec17bd.12 The 4 to 1 Mux Architecture - Implicit Process Example : Mux 4 to 1 - WHEN/ 1 ARCHITECTURE whenexample OF ExMux_4_1 IS 2 BEGIN DxDO <= AxDI WHEN (Sel1xSI & Sel2xSI) = 00 4 BxDI WHEN (Sel1xSI & Sel2xSI) = 01 5 CxDI WHEN (Sel1xSI & Sel2xSI) = 10 6 DxDI WHEN (Sel1xSI & Sel2xSI) = 11 7 X 8 END whenexample; Implicit process Priority based description Realizes nested gates Dataflow method Rev. ec17bd.12 The 4 to 1 Mux Architecture - Implicit Process Example : Mux 4 to 1 - WITH/SELECT/WHEN 1 ARCHITECTURE withexample OF ExMux_4_1 IS 2 SIGNAL SelxS : STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN 4 SelxS <= Sel1xSI & Sel2xSI; -- concatenate the select bits 5 WITH SelxS SELECT 6 DxDO <= AxDI WHEN 00, 7 BxDI WHEN 01, 8 CxDI WHEN 10, 9 DxDI WHEN 11, 10 X WHEN OTHERS; others condition is required due to std_logic is not only and 1, also X, Z among others 14 END withexample; Implicit process Not priority based implementation An efficient method of implementation Do not forget the others condition Rev. ec17bd.12

6 ModelSim Do-Files Example Do-file 1 # reset the simulation 2 restart -force -nowave 4 # add all input and output signals to the wave file 5 add wave -logic i0 6 add wave -logic i1 7 add wave -logic i2 8 add wave -logic i 9 add wave -logic Sel 10 add wave -logic out # force the input signals 1 force -freeze i force -freeze i force -freeze i force -freeze i force -freeze Sel force -freeze Sel force -freeze Sel force -freeze Sel # run the full simulation 24 run # open the wave window 27 view wave ModelSim allows you to automate sequences of commands using DO files To create a new DO file, navigate to the ModelSim main window and choose File New Source Do To run a Do-file type in ModelSim command-line <NAME>.do The option -freeze is the default drive type and can be avoided. force [-freeze -drive -deposit] [-cancel <time>] [-repeat <time>] <item_name> <value> [<time>] [, <value> <time>...] Rev. ec17bd.1 ModelSim DO-File reference manual : modelsim-command-reference-manual-v10-a The parallel carry-ripple adder Exercise : 4 Bit Full-Adder Specify the interface of a 4 Bit Full-Adder by using VHDL. Exercise : The model Write the functional model to the 4 Bit Full-Adder interface by using the VHDL methods shown above. Exercise : The test Write the functional test by using ModleSim Do-File syntax. Outlook In the upcoming session we are going to finish and test the adder in the lab. Make sure every thing is clear! Prepare questions if there are any!! We will not only do logical testing, but also a test run on real-world hardware. Rev. ec17bd.14

Lecture 3. VHDL Design Units and Methods. Entity, Architecture, and Components Examples of Combinational Logic Hands-on in the Laboratory

Lecture 3. VHDL Design Units and Methods. Entity, Architecture, and Components Examples of Combinational Logic Hands-on in the Laboratory Lecture 3 Entity, Architecture, and Components Examples of Combinational Logic Hands-on in the Laboratory BTF4220 - Digital Electronics 2 Mar. 06, 2015 Bern University of Applied Sciences Agenda Rev. ec317bd