EE 101 Homework 4 Redekopp Name: Due: See Blackboard

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1 EE 101 Homework 4 Redekopp Name: Due: See Blackboard Score: In this homework we will use Xilinx to complete the indicated designs. Using Xilinx to perform this homework. Please download the Xilinx EE 101 HW4 Project from Blackboard..Homeworks. Unzip it and open the project file: ee101_hw4.ise. In Project Navigator, first select the "Simulation" radio button rather than "Implementation". ou will see 5 testbench files (ee101_hw4_q?_tb.v) and if you expand each one (click the + sign) you will see 5 schematic files (one for each question). Open each question's schematic file in turn and complete the design based on the descriptions below. When you think you have it completed, save it and and click Tools..Check Schematic. Look for warnings and errors in the Console pane at the bottom of the window. These will list any wiring issues you have. Fix any errors and repeat the check until all errors/warnings are fixed. Save your schematic. Next double click on the associated testbench file. Open the testbench and understand what input combinations are being generated and think about what the circuit SHOULD do (i.e. what you expect the outputs to be). Then in the processes pane below, expand the ISim Simulator option and double click on "Simulate behavioral model". The ISim window will open and simulate your design. Zoom out to 100% view and then zoom in on the section of the waveforms that exercise your design and verify the outputs are what you expect. If not, you need to try to debug your design (re-watch the Xilinx video for how to add intermediate signals to see what's happening in the inner-workings of your circuit). Update your design and re-simulate until it works as you expect! Repeat this process for each Xilinx-based question. ou must submit your.sch files on the Blackboard HW 4 submission AND print out a hard copy of each schematic. No hard-copy = no points! 1

2 HW 4a Blackboard Form 1) [BB] (11 pts.) Examine the decoder on the attached page: Label the enable with E or /E depending on whether it is active high or low. ou must figure out which output corresponds to which gate based on the gate connections. Then label the outputs appropriately using or /0 /1 /2 /3 depending on whether they are active high or low. HW 4b Xilinx Submission 2) [Xilinx] (24 pts.) Design each of the following single or multiple output logic functions using the building blocks listed below for each problem along with an appropriate gate for each output bit. Hint 1: In each case you will need to cascade multiple decoders to build a 4-to-16 decoder. Then implement the outputs using that 4-to-16 decoder. F1 = WXZ(0,3,6,7,10,12,14) F0 = WXZ(1,4,7,13,15) (16 pts.) Using (2) 3-to-8 decoders with an active high enable + a minimal number of inverters or other gates, compose a 4-to-16 decoder. Then use one gate per output to produce the outputs F1 and F0. Note: F1 and F0 are functions of the same inputs, so only 1 4-to-16 decoder is required. G = ΠABCD(1,2,5,6,7,9,10,13,14,15) Using (5) 2-to-4 decoder each w/ active-hi enables (8 pts.) 3) [Xilinx] (17 pts.) Design an 8-to-3 priority encoder similar to the one we studied in class. our priority encoder should take in 8 input values I(7:0) where I(7) (highest priority) through I(0) (lowest priority). The output should be the 3-bit binary number (2:0) of the highest-priority active input. our priority encoder should also include an active-low Valid output (Vb) [Note: Xilinx and Verilog don't like a '/' in front of a name to indicate it is active low, so we use the convetion of puttin a lower-case 'b' after the name to indicate it is active low. Vb should be active to indicate that at least one input was active and was encoded (as opposed to the case where no inputs are active and the encoder outputs 000). To implement your design review the attached diagram. A simple encoder using OR gates will produce the final outputs. What you need to do is implement logic that will only allow the highest priority input to be passed to that simple OR gate encoder and force all other inputs to 0. our priority logic should only need 1 level of logic (remember inverters don't count as a level). 4) [Xilinx] (8 pts.) Although it is usually standard to build muxes with 2 n data inputs, there are times when muxes with a different number of inputs are used. our job is to design a 6-to-1, 2-bit wide mux using 4-to-1 and 2-to-1 mux building blocks (a diagram of which is shown below). our 6-to-1, 2-bit wide mux should have inputs labeled: A(1:0), B(1:0), C(1:0), D(1:0), E(1:0), and F(1:0) as well as select inputs S(2:0) and outputs labeled (1:0). A select value of 000 should pass A,, while a 2

3 select value of 101 should pass F. Behavior for select values of 110 and 111 is undefined (can be anything.) I 0 I 0 I 1 I 2 I 1 S I 3 Use several of these 2-to-1 and 4-to-1 muxes to build a 6-to-1 2-bit wide mux 5) [Xilinx] (20 pts.) our task is to design a circuit that can perform a right or left rotation on a 4-bit binary number, A(3:0) to produce an output B(3:0). A right rotation operation is defined as shifting the bits of 4-bit binary number to the right and any bit shifted out of the right-end is rotated around and put back in on the left side. A left rotation is just the opposite. To indicate how many bits to rotate the number, a rotation value, R = R(1:0) (2 s complement), is also given as input. A positive value indicates a right rotation amount and a negative value indicates a left rotation amount Positive Shift Value = Right Rotate Negative Shift Value = Left Rotate Example 1: A = 0110 with a rotation value of R=01 = +1 will cause B = 0011 (the 0 on the right end was put back into the left end.) Example 2: A = 1011 with rotation value of R=10 = -2 will cause B= 1110 To design your circuit, you need only use (4) 4-to-1 muxes as shown on the attached handout and NO other logic. To approach the problem, start by trying to write a function table for the B outputs. Recall that a function table puts the outputs (Bi) in terms of input variables and not necessarily just 1 s and 0 s. Think about which inputs really determine what value B should take and how you can express B in terms of input variables. Once you have a function table, treat each output bit as a separate function and implement it appropriately. 6) [Xilinx] (20 pts.) Implement each of the functions below using the indicated mux (either a 2-to-1 or 4-to-1) and any other necessary INVERTERS or 2-input gates [No 3- or 4- input gates] ou must use the input MSB s as your mux select bits. 3

4 a. F = WXZ(0,3,6,7,8,10,13,14,15) [4-to-1 mux] (10 pts.) b. G = ΠABCD(1,2,5,6,8,9,12,14) [2-to-1 mux] (10 pts.) Attachment for problem 1 A LSB B MSB 4

5 Attachment for problem 3) Use only 1-level of logic to only pass the highest priority Ij input to the Xj signal which is then run into the simple encoder. I0 X0 Simple Encoder (Only 1-input can be active) I1 I2 I3 I4 I5 I6 X1 X2 X3 X4 X1 X3 X5 X2 X3 X6 X4 X5 X I7 X5 X6 /V Logic for Priority Scheme 5

6 Attachment for problem 5) Please use labels rather than large amounts of wires (i.e. label the inputs to each mux using an appropriate Ai bit or Ri bit). A0 B0 A1 B1 A2 B2 A3 B3 R1 R0 6