Registers and finite state machines

Transcription

1 Registers and finite state machines DAPA E.T.S.I. Informática Universidad de Sevilla /22 Jorge Juan 2, 2, 22 You are free to copy, distribute and communicate this work publicly and make derivative work provided you cite the source and respect the conditions of the Attribution-Share alike license from Creative Commons. You can read the complete license at: Contents Introduction Flip-flops Registers Counters Finite state machines

2 Introduction Design a garage door control system with two push buttons (no switches) separated by a distance: x: open the door y: close the door open (x) close (y) door (z) Asynchronous SR latch R=S= the state is preserved S S R R S=, R= change to (set) S=, R= change to (reset) S S R R

3 SR Latch. Formal description Symbol S State table SR - State diagram SR= SR=x = = SR=x R - Q Verilog SR= S R Excitation table Q SR x x module sra( input s, input r, output reg ); r) case ({s, r}) 2'b: = 'b; 2'b: = 'b; 2'b: = 'bx; endcase endmodule Synchronous latches In real circuits with thousands or million latches, it is very useful to control the state change so that it happens in all devices at the same time. State change is synchronized to a clock signal () Gated latches State change is only allowed when is either high () or low (). Edge-triggered latches (flip-flops) State change is only allowed at the instant changes from to (positive edge) or from to (negative edge) State change is more precisely determined. Make more robust and easy to design circuits

4 Synchronous latches Gated latch Flip-flop module srl( input ck, input s, input r, output reg ); S R ck module srff( input ck, input s, input r, output reg ); S Rck s, r) if (ck == ) case ({s, r}) 2'b: = 'b; 2'b: = 'b; 2'b: = 'bx; endcase endmodule ck) case ({s, r}) 2'b: = 'b; 2'b: = 'b; 2'b: = 'bx; endcase endmodule State change when ck= State changes when ck changes from to Other flip-flops SR JK D T Similar to SR: J~S, K~R Toggle (reverse) function for J=K= A single input eual to the next state Easy to use and implement A single input to toggle the state Very useful in some special applications: counters

5 D flip-flop Synbols State table State diagram D D D= D= D= = = ck Q D= D ck Excitation table Q D Verilog module dff( input ck, input d, output reg ); ck) <= d; endmodule Asynchronous inputs Easy way to force a given state (clear): set to PR (preset): set to Immediate effect after activation: Active low () Active high () Higher priority than synchronous inputs J, K, D, T,... J K ck PR D Solution to the problem of initiating the state in complex digital systems Million of flip-flops Need to start from a known state ck PR T ck

6 Timing Synchronous inputs should not change close to the active edge of the clock signal to avoid an unpredictable state change. Set-up time (ts) Time before the active edge in which inputs should not change. Hold time (th) Time after the active edge in which inputs should not change. Timing t s t h D ck Q= D Q=X Q=X Q=

7 Contents Introduction Flip-flops Registers Counters Finite state machines Registers n-bit storage element (n flip-flops) Content is expressed from the data it represents: number (in hex or decimal), character, etc. Basic operations: Write (load): stored data modification. Read: access to the content of the register.

8 Registers. Classification Parallel input All the bits can be written (loaded) at the same time (with the same clock event). There is one load input signal for each stored bit. Serial input Only one bit can be written at each clock cycle. A single input signal for all the stored bits. Parallel output All the bits can be read at the same time. One output signal for each stored bit. Serial output Only one bit can be read at each clock cycle. A single output signal for all the stored bits. Registers. Classification parallel-in/parallel-out parallel-in/serial-out serial-in/parallel-out serial-in/serial-out

9 Parallel-in/parallel-out register x LD x 3 x 2 x x REG z 3 z 2 z z Verilog code module reg( input ck, input cl, input ld, input [3:] x, output [3:] z ); z Operation table, LD Operation Type x async. x sync. sync. reg [3:] ; ck, negedge cl) if (cl == ) <= ; else if (ld == ) <= x; assign z = ; endmodule Parallel-in/parallel-out register LD x 3 x 2 x x REG z 3 z 2 z z Asynchronous operation table Operation Typ. stage Excit. Q i = i = Q i = i i = Synchronous operation table LD Operation Typ. stage Excit. x Q i = x i D i = x i Q i = i D i = i C.C. i control data state C.C. flip-flop i i x i D i i z i z i LD

10 Parallel-in/parallel-out register x 3 x 2 x x LD REG z 3 z 2 z z x 3 x 2 x x 3 2 D 3 D 2 D D LD z 3 z 2 z z Shift register x L Verilog code EN z L REG module reg_shl( input ck, input cl, input en, input xl, output zl ); reg [3:] ; Operation table, EN Operation Type x async. SHL() sync. sync. ck, negedge cl) if (cl == ) <= ; else if (en == ) <= {[2:], xl}; assign zl = [3]; endmodule

11 Shift register x L Synchronous operation table EN REG EN Operación Et. típica Et. Ex. típ. Ex. et. SHL() Q i = i- Q = x L D i = i- D = x L Q i = i Q = D i = i D = z L C.C. i control data state C.C. flip-flop i i i- D i i z i EN Shift register x L EN REG z L x L 2 3 D D D 2 D 3 EN z L

12 Contents Introduction Flip-flops Registers Counters Finite state machines Counters Introduction Registers Counters Binary up counter modulus 2n Count limiting Down counter Up/down counter Non-binary counters Design with seuential subsystems

13 Counters Similar to the register: adds count operation Design Modular design principles Easier implementation with T or JK flip-flops (simplified count operation). Typical operations Up counting Down counting Reset (clear) Count state loading Typical output Count state Count end: counter in the last count value. Binary modulus 2 n up counter Modulus Number of counter states Binary Consecutive base-2 numbers Modulus 2n Counts from to 2n- (n bits) Cyclic count First count state follows last count state (overflow)

14 Binary modulus 2 n up counter Verilog code COUNT z 3 z 2 z z module count_mod6( input ck, input cl, output [3:] z ); reg [3:] ; Operation table Operation Type async. + mod 6 sync. ck, posedge cl) if (cl == ) <= ; else <= + ; assign z = ; endmodule Binary modulus 2 n up counter Count operation

15 Binary modulus 2 n up counter with clear and enable inputs Verilog code EN COUNT z 3 z 2 z z module count_mod6( input ck, input cl, input en, output [3:] z ); reg [3:] ; Operation table, EN Operation Type x sync. + mod 6 sync. sync. ck) if (cl == ) <= ; else if (en == ) <= + ; assign z = ; endmodule End-of-count output Verilog code EN COUNT z 3 z 2 z z C module count_mod6( input ck, input cl, input en, output [3:] z, output c ); reg [3:] ; ck) if (cl == ) <= ; else if (en == ) <= + ; assign z = ; assign c = &; endmodule

16 Binary modulus 2 n up counter with load and enable inputs LD EN x 3 x 2 x x COUNT z 3 z 2 z z Verilog code module count_mod6( input ck, input ld, input en, input [3:] x, output [3:] z ); reg [3:] ; Operation table LD, EN Operation Tipo x x sync. + mod 6 sync. sync. ck) if (ld == ) <= x; else if (en == ) <= + ; assign z = ; endmodule Count limiting. BCD counter Verilog code EN BCD COUNT (-9) z 3 z 2 z z module count_mod( input ck, input cl, input en, output [3:] z, ); reg [3:] ; Operation table, EN Operation Type x sync. + mod sync. sync. ck) if (cl == ) <= ; else if (en == ) if ( == 9) <= ; else <= + ; assign z = ; endmodule

17 Modulus 2 n down counter with clear, enable and borrow Verilog code EN COUNT z 3 z 2 z z B module count_mod6( input ck, input cl, input en, output [3:] z, output cb ); reg [3:] ; Operation table, EN Operation Type x sync. - mod 6 sync. sync. ck) if (cl == ) <= ; else if (en == ) <= + - ; assign z = ; assign c b = &; &~; endmodule Up/down counter EN UD COUNT C z 3 z 2 z z Operation table, EN, UD Operation Type xx async. x sync. + mod 6 sync. - mod 6 sync.

18 Up/down counter Verilog code module rev_counter( input ck, input cl, input en, input ud, output [3:] z, output c ); reg [3:] ; ck, posedge cl) begin if (cl == ) <= ; else if (en == ) if (ud == ) <= + ; else <= - ; end assign z = ; assign c = ud? ~( ) : &; endmodule Verilog code module rev_counter2( input ck, input cl, input en, input ud, output [3:] z, output c ); reg [3:] ; reg c; ck, posedge cl) begin if (cl) <= ; else if (en) if (!ud) <= + ; else <= - ; end if (ud) else assign z = ; c = ~( ); c = &; endmodule Ring counter z 3 z 2 z z START... PR 3 2 D 3 D 2 D D z 3 z 2 z z

19 Seuence generator seuence generator with shift register. z START PR PR z D 3 D 3 D 3 D 3 Seuence generator With counter and C.C. Verilog code START COUNT module se_gen( input ck, input start, output z ); reg [:] ; reg z; C.C. z ck) if (start == ) <= ; else <= + ; START COUNT 2 3 z case () 2'h: z = 'b; 2'h: z = 'b; 2'h2: z = 'b; 2'h3: z = 'b; endcase endmodule

20 Example: de-bouncer and edge detector x de-bouncer y edge detector z x y z Example: 7S controller AN A D[3:] D D D2 A B C D seg[:7] F B D3 E F G BCD/7S G E D A B C D E F G AN should be '' for the device to work. C D 3 D 2 D D D seg[:7] ABCDEFG

21 Example: 7S controller 4 X X X2 X3 AN AN AN2 AN3 7S 7 Refresh period AN AN : 5MHz Refresh freuency: Hz - KHz AN2 AN3 Contents Introduction Flip-flops Registers Counters Finite state machines

22 Finite State Machines (FSM) x z x 2 z 2 x 3 x 4 x δ, ω z z 3 z 4 x 5... z 5... Q state S Q = δ(, x) z = ω(, x) S 2 S 3 S 4... Finite State Machine properties Starting at the same state, deterministic FSM's always generate the same output seuence for the same input seuence. Two FSM's are euivalent if they generate the same output seuence for the same input seuence. FSM's can be optimized: an euivalent FSM with a reduced number of states. The state of the machine changes depending on the input seuence so the state represents the whole set of old input symbols (history of the machine) FSM's may not be completely specified: a next state may not be defined for a given current state and input value.

23 Synchronous Seuential Circuits (SSC) FSM's are an excellent tool to model digital circuits with memory. Digital circuits with memory elements (latches) are an excellent technology to implement FSM's: Inputs/outputs: digital signals of one or more bits. State: n-bit word stored in latches Next state function: combinational functions that are applied to the inputs of the latches. Output function: combinational function. Synchronous seuential circuits are digital circuits that implement finite state machines by using combinational circuits and latches. For practical reasons, the state change is controlled by a clock signal: edge-triggered flip-flops are normally used. Synchronous Seuential Circuits (SSC) x δ, ω z x C.C. z Q Q state flip-flops Mealy x δ Q flip-flops ω z

24 Formal representations State diagrams State tables Example : barrier control x=: open y=: close z: door control (: close, : open) Example 2: single-input barrier control x= one cycle: open x= two cycles: close z: door control (: close, : open) State diagram. Mealy Nodes / B / / Arcs Represent states. State names are more or less intuitive. E.g. {A, B, C,...}, {S, S, S2,...}, {wait, start, receiving,...} / A / / D / C / Represent possible state transitions from every state (S). Named as x/z, where: x: input value that triggers the transition from state S. z: output value of the machine when in state S and input is x.

25 State table. Mealy Double input table (rows and columns) with information euivalent to the states diagram. Rows: possible states. Columns: possible input values. In each cell: corresponding next state and output. Each node in the diagram and the arcs starting at that node correspond to a row in the states table. Converting a states diagram to a states table and vice-versa is trivial. State table. Mealy / B / / x S A A, B, B C, A, / A / / C C D D, B, A, B, / D / Q,z

26 State diagram. Moore A/ E/ B/ C/ Nodes Represent states. State names are more or less intuitive. E.g. {A, B, C,...}, {S, S, S2,...}, {wait, start, receiving, } Each node includes the output value corresponding to each state. D/ Arcs Represent possible state transitions from every state (S). Named as x: input value that triggers the transition from state S. State table. Moore Double input table (rows and columns) with information euivalent to the states diagram. Rows: possible states. Columns: possible input values. Output associated to every state in last column. Optionally, output value in each cell like Mealy. Same output for every input value. Each node in the diagram and the arcs starting at that node correspond to a row in the states table. Converting a states diagram to a states table and vice-versa is trivial.

27 State table. Moore x S z B/ A A B B C A A/ E/ C/ C D D A B E D/ E A B Q Applications of the SSC Seuence detectors Output activates only when a given seuence of symbols arrive to the input. Seuence generators The output generates a fixed seuence of symbols, or a variable one depending on the input. Control units The inputs modify the state and the state defines an actuation over an external system: barrier control, temperature control, presence control, liuid level control, etc. Seuential processing The output seuence is the result of applying some operation to the input seuence: parity calculation, seuential arithmetic operations, seuential coding/decoding, etc.

28 FSM design objective Objective Define a FSM that solves a given problem. Implement the FSM using a synchronous seuential circuits. Cost Various cost criteria drive the design process Minimizing the number of memory elements Minimizing the number of devices Operation freuency Energy consumption... Need to compromise different criteria Design processes Hand process Can be done with paper and pencil. Starts with a description of the problem using a state diagram or a state table. The states table is transformed in different steps to lead to a circuit representation. Design process using Computer Aided Design (CAD) tools The problem is translated to a formal description using a hardware description language. Simulation tools are used to check that the operation of the described system is correct. Automatic synthesis tools are used to implement the actual circuit.

29 Design process using CAD tools Word description of the problem Translation State diagram LDH description Translation Test bench Simulation no ok? yes Automatic synthesis Circuit Configuration Verilog FSM descriptions Mealy x δ Q flip-flops Three processes State change: represents the flip-flop block. Next state calculation: excitation euations (δ) Output calculation: output euations (ω). Only the state change process is seuential (includes memory elements) ω z // State change process (seuential) ck, posedge reset) if (reset) state <= A; else state <= next_state; // Next state calculation process // (combinational) begin case (state) A: next_state =...; B: next_state =...;... endcase end // Output calculation process // (combinational) begin z =...; end

30 Verilog FSM. Example x ck reset z See Verilog course / B / / B/ / A / / C A/ E/ C/ / D / D/ Other FSM design styles Mealy x δ Q flip-flops ω z