Power Management Techniques for Design Closure. Jyothi Jujare Rishi Chawla

Transcription

1 Power Management Techniques for Design Closure Jyothi Jujare Rishi Chawla

2 2 Agenda Introduction RTL Power Optimization Power Management through Clock Gating Interoperability of Clock Gating Conclusion Leakage Optimization with Multi-V th libraries Power Compiler low leakage design flows Case study Conclusion Summary

3 3 Key Power Management Areas Low Power Thermal Reliability 90nm Technology Applications Wireless Handheld Concerns Battery life Leakage power Dynamic power Applications Microprocessors Graphics/multimedia Concerns Thermal management Packaging, cooling cost Dynamic & Leakage power Applications All 90nm designs Concerns Chip failure Voltage-drop Electromigration

4 Synopsys Power Management Power Management Throughout the Design Flow 4 Galaxy Design Compiler Power Compiler Dynamic and leakage power optimization within DC / PC PrimeTime SI, PrimePower Module Compiler Power Compiler JupiterXT Physical Compiler Astro, Astro-Rail Star-RCXT DFT Compiler Milkyway PrimePower Peak and average power gate-level analysis JupiterXT Power grid creation, power network analysis Astro-Rail Hercules Voltage-drop and electromigration analysis

5 5 Where Does Power Go? Microprocessor1 Microprocessor2 MPEG2 Decoder ATM Switch Logic Clock Memory I/O Relative Power Dissipation, ISSCC Clock is major contributor to power dissipation

6 Typical Synchronous Load Implementation 6 always (posedge (posedge CLK) CLK) if if (EN) (EN) D_out D_out = D_in D_in OR always@ always@ (posedge (posedgeclk) clk) Q <= <= (enable) (enable)? D_in D_in :: Q; Q; Synchronous-load-enable implementation Levels of Hierarchy Reg Bank FF D_in combo EN Reg Bank D_out OR always@ always@ (posedge (posedgeclk) clk) case case (enable) (enable) 1 b1: 1 b1: Q <= <= D_in; D_in; 1 b0: 1 b0: Q <= <= Q; Q; endcase endcase OR CLK

7 7 Traditional AND based clock gating D_in D_out EN GCLK Reg CLK CLK EN GCLK Glitches in enable signal appear at clock

8 8 Latch-Based Clock Gating D_in EN CLK latch EN1 Active-low latch Reg GCLK D_out Latch transparent when clock is low AND transparent when clock is high CLK EN EN1 Structure behaves like a master-slave, which captures enable signal at posedge of clock GCLK

9 9 Internal Clock Skew D_in EN CLK A CLK@ A latch EN1 B skew delay GCLK Reg D_out Clock at B later than A Skew > Delay Glitches can be propagated EN EN1 CLK@ B GCLK Glitch! Skew < Delay(Clk-Q)

10 Manage Skew with Integrated Clock Gating Cell (ICG) 10 set_clock_gating_style -positive [list integrated:clkg] D_in EN CLK A latch Reg B GCLK SNPS_CLOCK_GATE_HIGH D_out /* EXAMPLE LIBRARY (.lib) */ cell(clkg) { area : ; cell_footprint : fp_12900_6300 ; dont_touch : true ; dont_use : true ; clock_gating_integrated_cell: "latch_posedge" ; statetable( " CLK EN ", " IQ ") {table : " L L : - : L,\ L H : - : H,\ H - : - : N " ;} pin(en) { direction : input ; clock_gate_enable_pin : true; capacitance : 0.002;

11 Working with Integrated Clock Gating Cell (ICG) 11 Identify ICG in library report_lib <lib> [list CGX1 CGX2 ] Cell Footprint Attributes NEW CGX1 "tsca" b, s, u, cg CGX2 "tsca" b, s, u, cg cg - clock gating integrated cell attribute ICG cell sizing Power Compiler supports sizing of ICG Requires different sizes of ICG in library

12 RTL to Synthesis Clock Gating benefits 12 EN CLK EN CLK Synchronous Load Implementation D_IN Latch D_IN G_CLK Register Bank Register Bank D_OUT D_OUT Benefits Reduces switching power on clock net Saves area (muxes not needed) Reduces internal power consumption in gated registers Automatic (no RTL code change) Technology Independent Seamless integration with Synthesis Power Compiler Clock Gating Implementation

13 13 Criteria for RTL Clock Gating Default Requirement for Clock Gating Enable should not be always on Meet setup condition on the clock gating cell Meet minimum register bit width (default is 3) All the above requirements could be overidden by using set_clock_gating_registers set_clock_gating_style -setup set_clock_gating_check <value> or set_clock_gating_style -min_width <number>

14 14 Enhanced Register Clock Gating NEW Reg Bank Reg Bank EN a b (width 2) Reg Bank (width 2) EN CLK Clock Gate GCLK b a (width 2) Reg Bank (width 2) CLK Reg Bank Reg Bank c (width 2) c (width 2) Width condition violation: No CG Common enable factoring

15 15 Implementing clock gating # Sample script set power_enhanced_cg_min_width 2; #default set_clock_gating_style -positive {integrated} -negative {integrated} -control_point before -control_signal scan_enable -min_width 3 read_verilog testcase.v create_clock -p 10 clk1 create_clock -p 10 clk2 Do not use elaborate -gate_clock insert_clock_gating #insert_clock_gating -regular_only #for no enhanced CG propagate_constraints -gate_clock uniquify compile report_clock_gating -gated -ungated -verbose -hier

16 Clock Gate Insertion Report (STD OUT) ================================================================= Gated Include Enable Setup Width Clock Group Flip-Flop Name Exclude Bits Cond. Cond. Cond. Gated ================================================================= GATED REGISTERS cg0 4 yes yes yes yes out1_reg[1] - 1 (*) out1_reg[0] - 1 (*) out2_reg[1] - 1 (*) out2_reg[0] - 1 (*) out3_reg[1] - 1 (*) out3_reg[0] - 1 (*) UNGATED REGISTERS ================================================================ (*): enhanced clock gated register 16 Clock Gating Reporting

17 17 Multi-Stage Clock Gating NEW a stage1 CG Reg Bank a stage1 CG Reg Bank EN CLK b stage1 CG Reg Bank EN CLK stage 2 CG b stage1 CG Reg Bank c stage1 CG Reg Bank c stage1 CG Reg Bank set_clock_gating_style num_stages 2

18 18 Clock Gating report Clock Gating Multi-Stage Report clock_gating -verbose -multi_stage Clock Gating Summary Number of Clock gating elements 4 Number of Gated registers 9 (100.00%) Number of Ungated registers 0 (0.00%) Total number of registers 9 Number of multi-stage clock gates 1 Average multi-stage fanout 3.0 Number of gated cells 9 Maximum number of stages 2 Average number of stages

19 19 Manual Clock Gating module top(sys_clk, en..).. assign ck = sys_clk && en sub_des u1(ck,in,en1,out1);.. endmodule en u1 ck en1 u3 module sub_des(ck,..);.. ck) if(cken) dout=din; endmodule sys_clk en ck u2 Top

20 20 Power Compiler Module Clock Gating NEW u1 en1 sys_clk en latch ck u3 en latch ck Top u2

21 21 Criteria For Replacement Identify clock Clock must be defined using create_clock command Identify clock edge for black box set_module_clock_edges -rising_edge_clock RAM_03/clk The attribute pwr_cg_clock_edge is set

22 22 Implementing Module Level Gating # Sample script set target_library $lib1 $lib2.. link set_clock_gating_style -sequential latch \ -positive {integrated} -negative {integrated} \ -control_point before -control_signal scan_enable read_verilog testcase.v create_clock -p 10 sys_clk1 create_clock -p 10 clk2 set_clock_gating_edge -rising_edge_clock <sub_module>/clk set_module_clock_gate -exclude <list_of cells_not to be replaced> insert_clock_gating -module_level uniquify compile report_clock_gating -gating -gated -ungated -verbose

23 23 Reporting Module Level Gating Clock Gate Replacement Report (STD OUT) insert_clock_gating -module_level Information: Performing clock-gating on design top Information: Bus naming style %s[%d] Clock Gate Replacement Report ======================================================== Clock Include Clock Edge Setup Gate Root Cell Name Exclude Fanin Type Func. Cond. Repl. =================================================== clk2 C7-1 fall or yes yes clk1 C6-1 rise and yes yes ========================================================

24 24 Report Clock Gating Module level Clock gating module replacement report clock_gating -gating_elements -verbose Design : top Version: V Date : Thu Jan 29 10:45: **************************************** Clock Gating Bank : clk_gate_c STYLE = latch, MIN = 3, MAX = 2048, HOLD = 0.00, SETUP = 0.20, OBS_DEPTH = 5 TEST INFORMATION :OBS_POINT =NO,CTRL_SIGNAL= scan_enable,ctrl_point=before INPUTS : clk_gate_c6/clk = clk1 clk_gate_c6/en = en1 clk_gate_c6/te = n6 OUTPUTS : clk_gate_c6/enclk = gclk1 GATED MODULES : u1

25 25 Agenda Introduction RTL Power Optimization Power Management through Clock Gating Interoperability of Clock Gating Conclusion

26 26 Formal Verification of Clock Gating Equivalence Checking - Formality New compare points are created The RTL design does not have this match point Test CLK FF D_in EN Latch G_CLK Reg Bank D_out Compare points

27 27 Formal Verification of clock gating Recognizing clock gating Specify verification_clock_gate_hold_mode to none - Default low Holds clock low during inactive high Holds clock high during inactive any Both high and low styles within design NEW This variable when set, determines that the function is the same as that of design that has no clock gating

28 28 Formal Verification of clock gating(cont..) Recognizing clock gating with test port If clock gating circuit has a scan port Typically disable the inserted scan logic set_constant i:/work/top/test_se 0 -type port

29 29 Testability Support Clock-gated registers are only clocked when enable is true During test mode or scan mode we need to clock the registers irrespective of enable condition Ensure that internal node of clock-gating cell is observable during test mode

30 30 Test Coverage with test_mode test_mode 1 Control Point Levels of design hierarchy DATA In D Q DATA Out Di CLK D Flipflops Q Control logic EN D Q Latch G ENCLK Register bank = not tested = partially tested = fully tested

31 31 Complete Observability Other observability nodes EN3 EN2 CLK Observe Flop test_mode EN1 D Q data_out EN Latch CLK Unobservable point

32 32 Test Coverage with scan_enable scan_enable 0 during capture Control Point Levels of design hierarchy DATA In D Q DATA Out Di CLK D Q Flipflops Control logic EN D Q G Latch ENCLK Register bank = not tested = partially tested = fully tested

33 33 Enhancements in hookup_testports test_mode or scan_enable U0 Is set_dft_signal set? no Is set_test_hold set? no If not, Create port test_mode or scan_enable U0 Is set_scan_signal set? no If not, Create port set_dft_signal -hookup_pin set_scan_signal -hookup_pin The signal type attribute (test_scan_enable / test_mode) set by Power Compiler

34 34 Test_mode and latch-based CG Pre-scan DRC: clock pin is not controlled data_in test_mode EN (internal pin) CLK created falling clock 1/1/1 X/X/X 1/1/1 1/0/1 D Q G previous state X/1/1 1/0/1 SNPS-CLOCK-GATE-HIGH X/0/1 D Q Initial state Is unknown data_out test_setup_additional_clock_pulse = true ( ) The state of the latch is known; The clock pin is controllable

35 35 Scan_enable and latch-based CG Pre-scan DRC: clock pin is not controlled clock CLK not able to capture data_in D Q data_out 0 during capture scan_enable EN (internal pin) CLK created falling clock X/X/X X/X/X 1/0/1 D G Q X/X/X 1/0/1 X/0/X SNPS-CLOCK-GATE-HIGH The user has to change the clock polarity

36 36 Latch-based CG Configurations Clock Gating CLK Control Signal Control Point Scan-inserted Location Register HIGH Latch-based LOW Latch-based test_mode scan_enable test_mode scan_enable test_mode scan_enable test_mode scan_enable Before YES After YES Before YES After YES Before YES** After YES Before NO After NO Before YES After YES Before YES After YES Before YES** After YES Before NO After NO ** fixed for (test_setup_additional_clock_pulse)

37 37 Power Compiler in DC-XG mode NEW All the existing Power Compiler features and commands are ported to DC-XG mode Results indicate capacity improvement of 45% average Run time improvements also available on limited commands in XG mode read_saif report_power

38 38 Clock-Gating Support Logic synthesis Combinatorial setup and hold constraint generation and checks Propagate constraints Formal verification RTL to gate-level equivalence checking Back-end support Clock skew minimization and balancing Testability Controllability & observability test logic XG

39 39 Clock Gating Savings Device Power Savings Area Savings IP Core 65% 14% Line Codec chip 35% 7% Soft IP block 40% 7% Soft IP block 55% 20% Graphics 20% 12% Graphics core 63% 17% Power Savings : 20 to 70% Area Savings : 5 to 20%

40 Leakage Optimization using Multi-V th Libraries Rishi Chawla Power CAE Team

41 Technology Scaling Effect on Leakage Power 41 Device scaling down Smaller geometry Lower VDD Lower threshold voltage Dynamic Leakage 250 Higher power Power (w) High power density High leakage power Leakage power management is required Device Dimension (nm) * Data taken from Intel, UMC

42 42 Voltage Threshold affects Power and Delay 100% 80% 60% 40% 20% 0% Leakage Delay Low-V th Std-V th High-V th Multi-V th process reduces Leakage power by an order of magnitude CMOS is the mainstream of ASIC design in the near future Threshold voltage affect sub-threshold leakage exponentially Higher V th cells have low leakage power but are slow Lower V th cells have high leakage power but are fast Multi-V th libraries enable low leakage design

43 43 Save Power on Non-Critical paths Timing paths Timing paths Before Power Optimization A B C D E Delay After Power Optimization A B C D E Delay Path with Low-V th cells; Critical path Non-Critical paths Timing constraint Leakage reduced Path with High-V th cells Use Low-Vth cells on critical paths to improve timing Use High-Vth cells on non-critical paths to save power No impact on timing

44 44 Improvements in Release Performance improved by10x Leakage QoR improved upto 20% Options to trade-off Performance and QoR Pre-Route & Post-Route Power Optimization Flow

45 Trade-off between QoR and Performance Regular option 45 Leakage power Library cell <= 0.0 Non-critical path Timing path Checks for low power cell candidates in all libraries Provides a good balance between QoR and runtime Multi-V th Libraries Leakage

46 Trade-off between QoR and Performance Cell Swap, naming based option 46 CL AL AS BL Non-critical path CH AH AH BS Shortest optimization runtime Library cell Multi-V th libraries 0.0 AL AS AH BL BS BH CL CS CH Low V th Std V th High V th 0.0 Timing path Speed Leakage Cell swap possible only among cells with same naming style

47 47 Leakage Optimization in Design Compiler RTL compile Minimize leakage with an early optimization Leakage settings compile -incr Multi-V th libraries Gates Preferable to provide Multi-V th library Simple usage flow set target_library HV th.db SV th.db LV th.db compile <power optimization setting> compile -inc Shown on slide 49

48 48 Leakage Optimization in Physical Compiler Floorplan Gates Leakage settings physopt physopt -incr Multi V th libraries Placed Gates set target_library HV th.db SV th.db LV th.db <power optimization setting> physopt Shown on slide 49

49 Options for Leakage Power Optimization Command settings 49 # Regular: set physopt_enable_power_optimization true set power_opto_simple_leakage_mode true set_max_leakage_power 0 mw OR # Cell Swap, naming based: set physopt_enable_power_optimization true set power_use_multi_vt_swap_opto true set power_multi_vt_naming_styles { } set_max_leakage_power 0 mw OR # High Effort: set physopt_enable_power_optimization true read_saif input my.saif inst tb/top set_max_leakage_power 0 mw Provides best balance of QoR & Runtime Recommended set of options Provides better Runtime Provides better QoR

50 Cell Swap Naming Style Command settings 50 Lib1 V th -1 andhd2 andsd2 andld2 xorhd4 xorsd4 xorld4 Lib2 V th -2 muxhd3 muxsd3 muxld3 Naming styles of the above libraries are: Lib3 V th -3 {$1h$2 $1s$2 $1l$2} Use $1 $2 etc. To represent common parts of names among libraries Specify the distinct parts of the names among libraries which are h, s, l in this example The order of the styles is not important, since PwrC automatically sorts cell leakage power

51 Case Study Results of Different Options 51 Before Power Optimization: Leakage = 16.0 mw After Power Optimization High Effort Regular Cell Swap Leakage(mw) Runtime (min) WNS Leaf cells count: Technology: 150K 90 nm Lib Cell: Characterized for State Dependent leakage

52 Quality of Results and Runtime Results of benchmarking 52 60% 40% 20% 0% High Effort Leakage Power Regular Runtime Cell Swap Regular and High Effort options reach for more power savings Regular option is the recommended first choice 800% 600% 400% 200% 0% High Effort Regular Cell Swap Reference: area optimization only.

53 53 Post-Route Leakage Optimization Requirements Customers seeking leakage reduction at late design stage Save leakage power with minimal or no impact on placement and routing Solution Supported in Synopsys Galaxy platform One pass flow in Physical Compiler

54 Post-Route Leakage Optimization Flow 54 Design (Post R) PwrC Settings physopt post_route Astro eco (change by file) SDF set_load Multi-V th Libraries Power optimization option Cell Swap, naming based Short runtime Good result Low Power Design (Post R) Timing Sign off extraction PrimeTime

55 Post-Route Leakage Optimization Settings Command Options 55 set_target_library hvt.db svt.db lvt.db set physopt_enable_power_optimization true set power_use_multi_vt_swap_opto true set power_multi_vt_naming_styles { } set max_leakage_power 0 mw physopt -incr \ -only_power_recovery \ -no_design_rule \ -preserve_footprint \ -post_route Multi-V th cell swap used for power optimization -only_power_recovery no timing optimization -preserve_footprint avoids placement and routing -post_route informs PC to use annotated data for delay analysis

56 Case Study Post-Route v/s Pre-Route 56 Before Power Optimization: Leakage = 19.3 mw WNS = 1.6 ns After Power Optimization Post-Route Pre-Route Cell Swap Cell Swap Regular Leakage (mw) Runtime (mins) 7+Extr High-V th % WNS Leaf cells: 216K; Technology:130 nm Post-Route results does not include Extraction runtime

57 57 Conclusion Synopsys recommends to do leakage optimization before routing, using Regular flow Easy to use Short runtime Best result Synopsys tools can optimize leakage power for routed designs too Significantly faster than scripting Good QoR