Parallel- and sequential data processing
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1 BO 1 Parallel- and sequential data processing Outline Parallelism in VHDL Delta delays and Simulation time VHDL simulation cycle Process activation Parallel- and sequential statements Bengt Oelmann -- copyright Parallellism in VHDL architecture name_arch of name is Declaration of signals Process 1 Process 2 Process 3 Process 4 register ALU memory Controller Parallel statements end name_arch; Each module runs in parallel with the other, therefore VHDL must be able to describe parallelism Copyright Bengt Oelmann
2 BO 2 Simulating VHDL code For each in-vector an out-vector is generated VHDL description of the function Stimuli to the circuit (input data) VHDL simulator Response from the circuit (output data) Copyright Bengt Oelmann Simulating sequential events Simulation time The modeled time the circuit has been simulated (not the real simulator execution-time) Delta-delay Used in the simulator internally to queue events If a delta delay is added to the simulation, the simulation time is still un-changed. Copyright Bengt Oelmann
3 BO 3 Simulating sequential events Example: What is the response at output C? IN: A B & C Suppose that these gates have no internal delays 1 & Delta delays are used for serialization of events within the same simulation time Sim. time delta event 0 ns 1 IN: 1 0 Inv a new value for A is calculated 0 ns 0 ns 0 ns A: 0 1 Nand, And calculate new values B: 1 0 C: 0 1 And calculates a new value for C C: 1 0 No more events A new value will be assigned to C at zero simulation time since the gates have no delays. Copyright Bengt Oelmann Simulation cycle for the VHDL simulator Schedule changes of signals in future simulation time Start simulation response No new events makes the simulation stop Update signals Execute processes Drive signal values that have been scheduled to current simulation time stimuli Terminate simulation Only processes sensitive to inputs that have changed will be activated Copyright Bengt Oelmann
4 BO 4 Scheduling of signals Example #1, no delays specified in the code Time a, b, x Driver (output x) Comments 0ns 1, 0, 0 (0, 0ns) (0, 0ns+Δ) p2 executed (initialization) 0ns +Δ 1, 0, 0 (0, 0ns+Δ) 10ns 1, 1, 0 (1,10 ns + Δ) p2 executed (b changes) 10ns+Δ 1, 1, 1 (1,10 ns + Δ) At t=0 assumed that: a = 1 ; b = 0 ; x = 0 at t=10 ns, b= 1 p2: process(a, b) x <= a and b; end process p2; a b x Copyright Bengt Oelmann Scheduling of signals Example #2, two parallel signal assignments Time a, b, x Driver (output x) Comments 0ns 1, 0, 0 (0, 0ns) (1, 0ns+Δ) p3 executed (initialization) 0ns +Δ 1, 0, 1 (1, 0ns+Δ) 10ns 1, 1, 1 (1,10ns)(1,10ns+Δ)(0,10ns+ Δ) p3 executed (b changes) 10ns+Δ 1, 1, 0 (0,10 ns + Δ) At t=0 we assume: a = 1 ; b = 0 ; x = 0 at t=10 ns, b= 1 p3: process(a, b) a x <= 1 ; b if b = 1 then x <= 0 ; x end if; end process p3; Copyright Bengt Oelmann
5 BO 5 Ex: VHDL code for 3-input AND Exampel #3, a 3-input AND-gate x = a(2) a(1) a(0) and3: process(a) x <= 1 ; for i in 2 downto 0 loop x <= a(i) and x; end loop; end process p3; The new value for x is scheduled to a point in time after the for-loop has been executed X is always 0 in the for-loop X <= a(i) and 0 x = 0 Time a 2,a 1,a 0,x Driver (output x) Comments 0ns 1,1,1,0 (0,0ns) (1,0ns+Δ) (0,0ns+ Δ) (0,0ns+ Δ) (0,0ns+ Δ) 0ns +Δ 1,1,1,0 (0, 0ns+Δ) and3 executed (initialization) Signal-assignments are parallel events. The order of the signal-assignments in the code has no meaning. It doesn t work!! Copyright Bengt Oelmann Ex: VHDL code for 3-input AND a 3-input AND use variables and3: process(a) variable temp: bit; temp := 1 ; for i in 2 downto 0 loop tmp := a(i) and temp; end loop; end process p3; Variable assignment take place immediately without scheduling events in the future By using variables the code becomes sequential where the order of the statements matters Variables can only be used in processes It works!! Copyright Bengt Oelmann
6 BO 6 Processes A process is a sequential program Many processes in an architecture are executed in parallel Communication between processes is done through signals Syntax: [<process_name>:] process [(sensitivity list>)] [<declarations in the process>] <sequential statements> end process [<process_name>]; Copyright Bengt Oelmann Activating processes Process is activated when: -signal in sensitivity list is changed or -Signal in wait-statement Active/executing Process terminates when: -end process is reached -wait-statement is reached Waiting process(a, b, cin) s <= a xor b xor cin; end process; Activated if a, b or c is changed process s <= a xor b xor cin; wait on a,b,cin end process; Goes to wait-state Copyright Bengt Oelmann
7 BO 7 Sequential statements Sequential statements only in processes Sequential statements Their order in the code matters They are executed in zero simulation time They have nothing to do with sequential circuits The sequential statements are IF-THEN-ELSE CASE-WHEN Copyright Bengt Oelmann IF-THEN-ELSE Execute the first statement that follows a true conditions No other statement is executed label: if cond1 then statement1; elsif cond2 then statement2; else statement3; end if; -- not mandatory - not mandatory section -- not mandatory section Copyright Bengt Oelmann
8 BO 8 Boolean expressions with IF-THEN A series of conditions realizes a boolean function process (x, y, z, a, b) if x = 1 then f <= a; elsif y = 1 then f <= b; elsif z = 1 then f <= c; else f <= d; end if; end process; f = xa + x yb + x y zc + x y z d Copyright Bengt Oelmann Logic expression with IF-THEN-ELSE Example: process (xbus) if xbus = "111" then doitnow <= 1 ; else doitnow <= 0 ; end if; end process; Copyright Bengt Oelmann
9 BO 9 Incorrect usage of IF-THEN Exampel: process (xbus) if xbus = "111" then doitnow <= 1 ; end if; end process; -- a latch will be introduced D-LATCH Nothing in the code assigns the output To 0 D Q doitnow Xbus(2) Xbus(1) G Xbus(0) Copyright Bengt Oelmann CASE-WHEN statement Executes only one section that is followed by a true choice or followed by OTHERS The choices must be mutually exclusive All possible choices must be given Results in a multiplexer-based structure label: case selector_expression is when choice1 => statement1; when choice2 => statement2; when choice3 choice4 choice5 => statement3; when OTHERS => statement4; end case; Copyright Bengt Oelmann
10 BO 10 CASE-WHEN example 2:1 Multiplexer case sel is when 0 => z <= a; when 1 => z <= b; end case; 2:1 MUX a z b sel Copyright Bengt Oelmann Parallel statements Parallel statements are at architecture-level Parallel statements The order of the statements as they appear in the code has no meaning The result is an event (signal-assignment) in future simulation time The parallel statements are With-select-when When-else Copyright Bengt Oelmann
11 BO 11 WITH-SELECT-WHEN Is called selected signal assignment Parallel statement sensitive to and operates on signals Selects one out of several values that will drive the signal The selection is based on all possible values of an expression with expression select outsignal <= value1 when val1, value2 when val2,... value9 when val9; Copyright Bengt Oelmann Results generated from with-select-when with expression select outsignal <= value1 when val1, value2 when val2,... value9 when val9; multiplexer value1 value2 outsignal value9 val1 val9 Copyright Bengt Oelmann
12 BO 12 Examples of use of with-select-when add sub -- 2-to-1 multiplexer with addsub select opcode <= add when 0, sub when 1 ; addsub opcode with (a and b) select out <= "1011" when "00" "11--" when "1Z", x OR y when "11", "0000" when others; Logical expressions allowed others is a default choice when none of the listed choices are true with min_integer select outvec <= X"1F" when 35, X"27" when 2 TO 5, X"FF" when OTHERS; A range of values can be specified Copyright Bengt Oelmann When-else Also called conditional signal assignment Parallel statement sensitive to and operates on signals Selects one of several values to drive the signal The selection is based on the first condition to be true outsignal <= value1 when cond1 else value2 when cond2 else... value9; Copyright Bengt Oelmann
13 BO 13 Example on the use of when-else opcode <= add when (addsub = 0 ) else sub when (addsub = 1 ) else nop; out <= "1011" when (a = 0 ) else "11--" when (b = 0 ) else x OR y when (a AND b) = 1 else "0000"; -- 4-to-2 priority encoder outcode <= "11" when in3 = 1 else "10" when in2 = 1 else "01" when in1 = 1 else "00" when in0 = 1 else "00"; Copyright Bengt Oelmann Outline End of Lecture 3 Parallelism in VHDL Delta delays and Simulation time VHDL simulation cycle Process activation Parallel- and sequential statements Copyright Bengt Oelmann
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