University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science

Transcription

1 University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 150 Fall 2005 R. H. Katz Problem Set # 5 (Assigned 5 October, Due 14 October) SOLUTIONS 1. Consider the design of an elevator controller. The building has three floors, an up button on the first floor, up and down buttons on the second floor, a down button on the third floor, and three buttons inside the elevator indicating the floor to go to. Note that more than one button inside the elevator may have been pressed and active at the same time. While you can make assumptions, the behavior of the system must be reasonable. For example, pressing the Floor 2 button with the elevator on the second floor causes the elevator to remain there with its door open. Also if the elevator is moving from the second to the third floor, pressing the first floor button inside the elevator should have no effect. (a) Identify your inputs, outputs, and name and describe your states. What additional circuitry, like timers, flip-flops, comparators, etc., do you need outside of the state machine? One possible solution Inputs: Outputs: F1, F2, F3 (Buttons inside the elevator) 1U, 2U, 2D, 3D (Buttons on each floor) AF1, AF2, AF3 (Sensors to tell when Elevator Arrives at Floor) Open (Whether door is open or closed) For a complex system, timers could be used to wait a few seconds before the door closes after user selects the floor. Registers can be used to store the floor selection of the passenger if multiple floors were selected. S_F1: S_MF1: At Floor One, Open Door. Wait for user to press selection. In Transit to Floor 1. Door closed. Wait for arrival at selected floor via AF1 (Arrival at F1)

2 Draw a symbolic state diagram for your design, labeling all state transitions. F1 AF1 At F1 Open F2 2U 2D Moving to F1 Close F2 2U 2D Moving to F2 Close F1 1U F3 3D AF2 F3 At F3 Open F1 1U At F2 Open F2 AF3 Moving to F3 Close F3 3D (b) Write sketch Verilog code for a Moore Machine implementation of this state diagram. (*) begin NS = CS; Case (CS) S_F1: begin If (F2 2U 2D) NS = S_MF2; If(F3 3D) NS = S_MF3; S_F2: S_F3: begin If(F1 1U) NS = S_MF1; If(F3 3D) NS = S_MF3; begin If(F1 1U) NS = S_MF1;

3 If (F2 2U 2D) NS = S_MF2; S_MF1: begin If (AF1) NS = S_F1; S_MF2: begin If (AF2) NS=S_F2; case S_MF3: begin If (AF3) NS=S_F3; (posedge clk) begin If (Reset) CS<=S_F1; Else CS<=NS; Assign Door_Open = (CS==S_F1) (CS==S_F2) (CS==S_F3); 2. Consider the following variation on the traffic light controller problem. A North-South road intersects an East-West road. In addition to the Red/Yellow/Green traffic lights, the N-S road has green left-turn arrows. The arrows work as follows. With the traffic lights red in all direction, the N-S left turn arrows are illuminated Green. Then they turn yellow and finally they turn red. At this point, the N-S lights cycle Green/Yellow/Red. In the N-S direction, the Green Arrow time is 16 seconds and the Yellow Arrow time is 8 s. Overlapping with this is Red light time, which is 88 s. The Green light time is 24 s and the Yellow light time is 8 s. The Red Arrow time is what is left after the other arrows have been illuminated within the N-S cycle. The E-W lights are: Red 56 s, Green 56 s, and Yellow 8 s. (a) Draw a simple timing chart that shows the behavior of the N-S and E-W traffic lights and the Left Turn Arrow lights.

4 (b) Identify your inputs and outputs. What additional circuitry, like timers and flip-flops, do you need outside of the state machine? Input: Timer Output: NS_R, NS_Y, NS_G, EW_R, EW_Y, EW_G, L_R, L_Y, L_G (Signal for Each Light) Need a timer to keep track of the elapsed time. The timer is formed with a counter with a one second clock. A comparator is then used to check the timer against the time for each state. (c) Draw a symbolic state diagram. Make clear your assumptions, consistent with the specification above. (d) Write sketch Verilog code for a Moore Machine implementation of this state diagram. (*) begin NS = CS; Case (CS) Timer_Reset = 1 b0;

5 NS = CS; ArrowG: begin if (Timer==16) begin NS = ArrowY; ArrowY: begin if (Timer==8) begin NS = EW_G; EW_G: begin if (Timer==56) begin NS = EW_Y; EW_Y: begin if (Timer==8) begin NS = NS_G; NS_G: begin if (Timer==24) begin NS = NS_Y; NS_Y: begin if (Timer==8) begin NS = ArrowG; end Case (posedge clk) begin If (Reset) CS<=S_F1; Else CS<=NS; Assign Arrow_Green = (CS==ArrowG); Assign Arrow_Yellow = (CS==ArrowY); Assign Arrow_Red = ~(ArrowY ArrowG);

6 Assign NS_Green = (CS==NS_G); Assign NS_Yellow = (CS==NS_Y); Assign NS_Red = ~(NS_Green NS_Yellow); Assign EW_Green = (CS==EW_G); Assign EW_Yellow = (CS==EW_Y); Assign EW_Red = ~(EW_Green EW_Yellow); 3. Professor Katz has a complicated washing machine at home. It can advance through the following states in the following sequence: Extra Prewash, Prewash, Main Wash 1, Main Wash 2, Rinse 1, Rinse 2, Rinse 3, Starch, Rinse Hold, Graduated Spin, and Spin. The user selectively positions a dial to Extra Prewash, Prewash, or Main Wash 1 to indicate the initial state for the wash. When the Start button is pressed, the cycle begins in the selected initial state. The machine has a program control to indicate the kind of fabrics being washed: Cotton Normal, Cotton Short, Permanent Press Normal, Permanent Press Short, Delicates Normal, Delicates Short, and Woolens. Normal cotton and permanent press programs cycle through every state following the initial state. Short cotton and permanent press programs and the Delicates Normal program pass through Main Wash 1, skip Main Wash 2, enter Rinse 1 and 2, and skip Rinse 3. Delicates Short and Woolens are similar but also skip the second rinse. Finally if the Short Spin/Rinse Hold button is depressed, the program holds in the Rinse Hold state until the button is released, and then advances directly to Spin skipping the Graduated Spin. (a) Identify your inputs, outputs, and name and describe your states. What additional circuitry, like timers and flip-flops, do you need outside of the state machine? Inputs: Outputs: ExtraPrewash, Prewash, MainWash1, Start, Hold CN, CS, PPN, PPS, DN, DS, W (Type of Material) State Machine In Need a timer that signals the end of the current cycle. (b) Draw a symbolic state diagram for your design, labeling all state transitions. Indicate any additional assumptions you are making.

7 Start & MainWash1 / MainWash1 Initial Start & Extra Prewash / ExtraPrewash Start & Prewash / Prewash Timer & (CN PPN) / MainWash2 Timer & (CN PPN) / MainWash1 Timer & (CN PPN ) / Prewash Timer & (CS PPS DDN) / Rinse1 Timer & (CS PPS DDN) / Rinse1 4 Timer / Rinse 1 5 Timer & (DS W) / Rinse1 Timer & (CS PPS DDN) / Rinse2 Timer & (CN PPN) / Rinse 2 6 Timer & (DS W) / Rinse1 Timer / Idle Timer / Starch 7 Hold & Timer / Rinse Hold ~Hold & Timer / Rinse Hold 8 11 Timer / Graduated Spin ~Hold / Spin 9 10 Timer / Spin (c) Write sketch Verilog code for a Mealy Machine implementation of this state diagram. (*) Begin CS = NS; Case (CS) Initial:

8 If (Start) begin If (ExtraPrewash) begin NS = 1; State = ExtraPrewash If (Prewash) begin NS = 2; State = Prewash; If (MainWash1) begin NS = 3; State = MainWash1; 1: if (Timer) begin If (CN PPN) begin NS = 2; State = Prewash; If (CS PPS DDN) begin NS = 5; If (DS W) begin NS = 7; 2: if (Timer) begin If (CN PPN) begin NS = 3; State = MainWash1; If (CS PPS DDN) begin NS = 5; If (DS W) begin NS = 7; 3: If (Timer && (CN PPN) begin NS = 4; State = MainWash2; 4: If (Timer) begin NS = 5; 5: If (Timer) begin If (CN PPN) begin NS = 6; State = Rinse2; If (CS PPS DDN) begin

9 NS = 7; State = Rinse2; 6: If (Timer) begin NS = 7; State = Starch; 7: If (~Hold && Timer) begin NS = 8 State = RinseHold; If (Hold && Timer) begin NS = 11; State = RinseHold; 8: If (Timer) begin NS = 9 State = GraduatedSpin; 9: If (Timer) begin NS = 10; State = Spin; 10: If (Timer) begin NS = Initial; State = Idle; 11: If (~Hold) begin NS = 10 State = Spin; Case