SECTION 1 FAMILIARIZATION WITH VHDL

Transcription

1 SECTION 1 FAMILIARIZATION WITH VHDL Page Introduction 1.2 Overview of VHDL 1.7 VHDL design units 1.7 Description styles 1.10 Model organization 1.20 Packages 1.25 Signals and delays 1.28 Attributes 1.29 Signal attributes 1.33 References ECEMA Familiarization 1.1 Introduction to VHDL Objectives Characteristics Standardization effort 1993 ECEMA Familiarization 1.2

2 Objectives To provide a unified notation for describing electronic systems at various levels of abstraction (from gate level up). Both machine and human readable. To support the communication of design data. To aid the maintenance, modification and procurement of hardware. To support the development, verification, synthesis and testing of hardware designs as a common description between tools ECEMA Familiarization 1.3 Characteristics Support of modular hierarchical design. Separate interface and body specifications of design entities. Multiple body specifications sharing the same interface (different levels of abstraction, alternatives, versions). Late binding of bodies to entities using configurations. Parameterized behavioral, structural and mixed descriptions. VHDL Common Intermediate form for simplified CAD tool access ECEMA Familiarization 1.4

3 Example of an integrated design system DATA BASE management VHDL Behavior User Synthesis VHDL simulator VHDL Structure Floor planning placement, routing Module generation EDIF (Structure and masks) Standard cells Gate arrays 1993 ECEMA Familiarization 1.5 Standardization effort IEEE Standard VHDL developed through the VHDL Analysis and Standardization Group (VASG), a working group of the Design Automation Standards Subcommittee (DASS) of the Design Automation Technical Committee (DATC) of the Computer Society of the IEEE.Co-sponsored by the Automatic Test Program Generation (ATPG) subcommittee of the IEEE Standards Coordinating Committee 20. IEEE Standard evolved from VHDL Version 7.2 that was sponsored by the US Air Force, within the VHSIC program. IEEE standard adopted on December 10, New Standard ECEMA Familiarization 1.6

4 An overview of VHDL Design Units Entity declaration - Describes the interface view of a component (like a Data Book description) - Implementation independent Architecture body - Describes an implementation of an entity (like a single schematic diagram) - A single interface may have alternative architectures Package (declaration and body) - Contains information common to many Design Units - Functions, Types, Signals, Constants; Project wide design practice - Hides details, simplifies design; may invoke other packages Configuration - Relates local entity and architecture references to actual units in libraries (like a Parts reference list) 1993 ECEMA Familiarization 1.7 Entity and Architectures Entity interface Identifier, Generic constants, Ports Local types, signals, procedures etc. Assertions, Passive Processes Architecture 1 Declarative Part Local signals, procedures, constants, types, files, etc. Statement Part Concurrent statements Architecture n 1993 ECEMA Familiarization 1.8

5 Entity declaration Links the design entity to the external world. entity Full_Adder is -- one-bit adder port ( X, Y: in Bit; Cin : in Bit := '0' ; Sum : out Bit; Cout : out Bit ); end Full_Adder ; 1993 ECEMA Familiarization 1.9 Description styles in architectures Structural Behavioral Dataflow style Algorithmic style Mixed 1993 ECEMA Familiarization 1.10

6 Structural description A description of the object by interconnection of instantiated components X Y S1 Cin SUM S2 Cout S ECEMA Familiarization 1.11 architecture Structural of Full_adder is -- Internal signals signal S1, S2, S3 : Bit; Structural description (cont'd) -- Component declarations - can be in a package component XOR_G port (X1, X2 : in Bit; XO1 : out Bit); -- Formal ports of the component end component; component AND_G port (A1, A2 : in Bit; AO1 : out Bit); end component; component OR_G port (O1, O2 : in Bit; OU1 : out Bit); end component; 1993 ECEMA Familiarization 1.12

7 -- port association, positional: XOR1 : XOR_G port map (X, Y, S1); -- Instantiation XOR2 : XOR_G port map (S1, Cin, SUM); AND1 : AND_G port map (X, Y, S3); AND2 : AND_G port map (S1, Cin, S2); OR1 : -- port association, explicit: OR_G port map (O1 => S2, O2 => S3, OU1 =>Cout); end Structural; 1993 ECEMA Familiarization 1.13 Configuration declaration - A sort of Parts reference list - Relates local entity and architecture references to actual units in libraries: late binding of architectures to entities use work. all; --use the library of stored entities. configuration Conf_Adder of Full_Adder is for Structural --for the architecture structural of entity Full_adder for all : XOR_G use entity XOR_Gate (Behave); end for; -- can also for all : AND_G use entity AND_Gate (Behave); end for; -- map ports for all : OR_G use entity OR_Gate (Behave); end for; -- and generics end for; end Conf_Adder; 1993 ECEMA Familiarization 1.14

8 Behavioral description Dataflow (concurrent signal assignments) Algorithmic (processes containing sequential statements) 1993 ECEMA Familiarization 1.15 Dataflow style architecture DataFlow of Full_Adder is signal S1, S2 : Bit; -- Predefined enumerated type ('0', '1') -- Concurrent signal assignments, executed if and when a signal on the -- right-hand side of an assignment changes value -- Implicit delta delay when no explicit after clause S2 <= S1 and Cin; -- (1) S1 <= X xor Y; -- (2) Sum <= S1 xor Cin; -- (3) Cout <= S2 or (X and Y); -- (4) end DataFlow; Cycle Change Execution 0 X (2); (4) 1 S1, Cout (1); (3) 2 S2, Sum (4) 3 Cout 1993 ECEMA Familiarization 1.16

9 Algorithmic style architecture Functional-simple of Full_adder is process subtype BIT3 is Bit_vector (0 to 2); -- sequential execution case BIT3'(X&Y&Cin) is when "000" => when "001" "010" "100" => when "011" "101" "110" => when "111" => end case; wait on X, Y, Cin; end process; end Functional-simple; Sum <= '0'; Cout <= '0'; Sum <= '1'; Cout <= '0'; Sum <= '0'; Cout <= '1'; Sum <= '1'; Cout <= '1'; 1993 ECEMA Familiarization 1.17 Algorithmic style (cont d) architecture Functional-type-conversion of Full_adder is use Convert_Pack.all -- Contains type conversion functions... EA: block port (A, B, C : in INTEGER; S, CO : out INTEGER); -- Type conversion between bit and integer is performed in ports port map ( A => Bin_to_Int(X), B => Bin_to_Int(Y), C =>Bin_to_Int(Cin), Int_to_Bin(S) => Sum, Int_to_Bin(CO) => Cout); process (A, B, C) -- sensitivity list of the process variable Int1 : INTEGER; -- sequential execution Int1 := A + B + C; S <= Int1 mod 2; CO <= Int1 / 2; end process; end block EA; end Functional-type-conversion; 1993 ECEMA Familiarization 1.18

10 architecture mixed of Full_adder is Mixed description style signal S1: Bit; component XOR_G port (X1, X2 : in Bit; XO1 : out Bit); end component; -- internal signals -- component declarations -- Selection of component bodies for all : XOR_G use entity XOR_Gate (Behave); XOR1 : XOR_G port map (X, Y, S1); -- instantiation XOR2 : XOR_G port map (S1, Cin, SUM); Cout <= (S1 and Cin) or (X and Y); -- concurrent assignment statement end mixed; 1993 ECEMA Familiarization 1.19 Model organization for simulation Test_bench Process(es) Generation of stimuli & verification of responses Optional Test entity E_U_T Entity under test 1993 ECEMA Familiarization 1.20

11 Entity under test entity Full_Adder is -- an one-bit adder port ( X, Y: in Bit; Cin : in Bit := '0' ; Sum : out Bit; Cout : out Bit ); end Full_Adder; architecture DataFlow of Full_Adder is signal S1, S2 : Bit; S1 <= X xor Y; S2 <= S1 and Cin; Sum <= S1 xor Cin; Cout <= S2 or (X and Y); end DataFlow; 1993 ECEMA Familiarization 1.21 Test-bench entity entity Test_Bench is end Test_Bench ; use work. all; --use the library of stored entities. architecture Bench_Adder of Test_Bench is signal XS, YS, CinS, SumS, CoutS : BIT; component F_Adder port ( X, Y: in Bit; Cin : in Bit := '0' ; Sum : out Bit; Cout : out Bit ); end component; for all : F_Adder use entity Full_Adder (DataFlow); -- If we want to use the structural architecture of full_adder, we can use -- the configuration declaration presented earlier: -- for all : F_Adder use configuration Conf_Adder; 1993 ECEMA Familiarization 1.22

12 Test-bench entity (cont'd) EUT : F_Adder port map ( XS, YS, CinS, SumS, CoutS ); -- Waveform definition, 1st = Delta delay; after w.r.t. current time XS <= '0', '1' after 4 ns; YS <= '0', '1' after 2 ns, '0' after 4 ns, '1' after 6 ns; CinS <= '0', '1' after 1 ns, '0' after 2 ns, '1' after 3 ns, '0' after 4ns, '1' after 5 ns, '0' after 6 ns, '1' after 7 ns; end Bench_Adder; Observation of signal values depends on the implementation of the environment ECEMA Familiarization 1.23 A sample session (cont'd) Time Signal Names (ns) X Y CIN SUM COUT 0 '0' '0' '0' '0' '0' 1 *** *** '1' *** *** + 1D *** *** *** '1' *** 2 *** '1' '0' *** *** + 1D *** *** *** '0' *** + 2D *** *** *** '1' *** 3 *** *** '1' *** *** + 1D *** *** *** '0' *** + 2D *** *** *** *** '1' etc ECEMA Familiarization 1.24

13 Packages Allow the definition of data types and subtypes, components, files, procedures and functions,, which may be shared by different models and different users. Following the ADA language specifications, a VHDL 1076 package is made of 2 parts: the declarative part and the body part. The body of a subprogram can be defined in a language other than VHDL. The body is hidden from the user, can be modified without affecting models that use the package.. No global variables ECEMA Familiarization 1.25 Example of packages Package PACK is Type LOGIC4 is ( X, 0, 1, Z ); Constant PI : REAL := ; Function Convert ( A : in LOGIC4 ) return Integer; end PACK; Package body PACK is Function Test (A: LOGIC4 ; ) return Boolean is -- internal function end Test; Function Convert ( A : in LOGIC4 ) return Integer is if Test ( A) then end if; end Convert; end PACK; 1993 ECEMA Familiarization 1.26

14 Package utilization use Library.package.item ; Example 1 use work.pack.logic4 Example 2 use work.pack.all ; Entity Switch is port ( A, B, C, D: in Bit; S: out LOGIC4); end; 1993 ECEMA Familiarization 1.27 Signals and delays Waveform Inertial delay Delta delay Transport delay 1993 ECEMA Familiarization 1.28

15 Waveform A <= '1', '0' after 5 ns, '1' after 10 ns; -- Projected waveform a '1' '0' '1' 0ns 5ns 10ns signal driver '1' a '0' 5ns 10ns 1993 ECEMA Familiarization 1.29 Inertial delay Inertial delay: A <= B after 10 ns; The current value of B will be assigned to A in 10 ns, if B holds this value until then (persistency). B A 5 ns 10 ns 15 ns 20 ns 1993 ECEMA Familiarization 1.30

16 Transport delay Transport delay: A <= transport B after 10 ns; The current value of B will be assigned to A in 10 ns. B A 5 ns 10 ns 15 ns 20 ns 1993 ECEMA Familiarization 1.31 Delta delay process A <= '1'; -- Assignment to a signal is never -- immediate, it occurs D later -- (The so-called Delta Delay) if A = '1' then -- This condition is false if end if; wait on ; end process; -- A is '0' when process is resumed 1993 ECEMA Familiarization 1.32

17 Attributes of Signals Some attributes are signals... S'DELAYED [(T)] -- Signal S delayed by T units. -- S'DELAYED (0) /= S if S just changed S'STABLE [(T)] -- Has value TRUE if signal did not change in the past -- T units of time, else FALSE S'QUIET [(T)] -- Has value TRUE if no driver was active in the past -- T units of time, else FALSE S'TRANSACTION -- Signal whose value toggles between '0' and '1' each -- time S is active (not necessarily changing) 1993 ECEMA Familiarization 1.33 And others are functions... Attributes of Signals (cont'd) S'EVENT S'ACTIVE S'LAST_EVENT S'LAST_ACTIVE S'LAST_VALUE -- Has value TRUE if S changed in the current -- simulation cycle, else FALSE -- Has value TRUE if S is active in the current -- simulation cycle, else FALSE -- The amount of time that has elapsed since the -- last event occurred on S -- The amount of time that has elapsed since the -- last time at which S was active -- The previous value of S, immediately before -- the last change of S 1993 ECEMA Familiarization 1.34

18 REFERENCES [LRM 87] "VHDL Language Reference Manual", IEEE Standard , (Including recent VASG corrections) [Lips89] R. Lipsett, C. Schaefer, C. Ussery, VHDL: Hardware Description and Design,Kluwer Academic Publishers, Boston, [Arms89] J. Armstrong, Chip-Level Modeling with VHDL, Prentice Hall, Englewood Clifs, N.J., [Coel89] D. Coelho, The VHDL Handbook,Kluwer Academic Publishers, Boston, [Airi90] R. Airian, J.-M. Bergé, V. Olive, J.Rouillard, " VHDLdu langage à la modélisation", Presses polytechniques et universitaires romandes et CNET-ENST, [Perr91] Douglas L. Perry, VHDL, McGraw-Hill, Inc., [Berg92] J.-M. Bergé, A. Fonka, S. Maginot, J.Rouillard, VHDL Designer s Reference, Kluwer Academic Publishers, [Merm92] J.Mermet (ed.), VHDL for Simulation, Synthesis and Formal Proofs of Hardware, Kluwer Academic Publishers, [WAVE90] Waveform and Vector Exchange Specification - WAVES, WASG, WAVES PAR1029.1/D1, February Also, WAVES User Guide (WAVES PAR1029.1/D1-1), User's View of Waves (WAVES PAR1029.1/D1-2), WAVES Requirements and Rationale (WAVES PAR1029.1/D1-3). [VHDL90] J.R. Armstrong, Guest Editor, "Tuning VHDL for Multivalued Logic Modeling", and a series of articles on this subject in IEEE Design & Test Magazine, June [Nava93] Zainalabedin Navabi, VHDL - Analysis and Modeling of Digital Systems, McGraw-Hill, Inc., ECEMA Familiarization 1.35 FPGA Synthesis entity COUNTER is port ( CLK : in bit; RESET: in bit; COUNT: out integer range 0 to 7); end COUNTER; architecture ARCHOne of COUNTER is signal COUNT_tmp : integer range 0 to 7; process wait until (CLK event and CLK = 1 ); if RESET = 1 or COUNT_tmp = 7 then COUNT_tmp <= 0; else COUNT_tmp <= COUNT_tmp + 1; --Keep counting end if; end process; COUNT <= COUNT_tmp; End ARCHOne ; Output of synthesis 1993 ECEMA Familiarization 1.36