PLD (eg. PAL) Typically 8 logic elements Technology: AND-OR array. William Sandqvist
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1 PLD (eg. PAL) Typically 8 logic elements Technology: AND-OR array
2 CPLD (eg. MAX) Typically 64 Macrocells Technology : AND-OR array (larger MAX circuits uses MUX-tree technique)
3 Gates with many inputs? CMOS NAND VDD VQ PAL matrix has gates has so many inputs that you have to draw them in a "simplified way" VA VB VC Everyone must lead to get "" = slow when there are many inputs VSS
4 As bad with CMOS NOR CMOS NOR Everyone must lead to get "" = slow when there are many inputs (one of them must lead to get "" = fast)
5 Fast, but with high power dissipation NMOS NOR Can be used for many inputs, but NMOS will use much more power than the CMOS! "Pull-Up" resistor provides "" = Fast but "Power Hungry" when output is "" Just one must lead to get ""? = Fast
6 Large programmable circuits There is therefore a need for other techniques not based on gates with many inputs, in order to be able to build large programmable circuits in CMOS technology!
7 FPGA (eg. Cyclone II) Typically 5 logic elements Technology : MUX tree
8 The Multiplexor MUX The multiplexer can select which input you are going to connect to the output. MUX is now the "standard component" in the development of Digital Logic. X Y S Z Z = SX + S Y
9 Multiplexer MUX To the right we have a MUX in rope technology - April -joke from Scientific American! X Y Z S Z = SX + S Y Did you recognize that it was a MUX that was the "secret" circuit at LAB?
10 Logical functions with MUX How can the following functions be implemented with a 2: Multiplexer? Z Z Z Z = = = = x x x x NOT x AND + x x OR XOR? X Z Y S Z = SX + S Y
11 Quickie Question How to connect the inputs of the MUX in order to implement an inverter? Desired function:
12 Invertering NOT with MUX Specification: if input = then result <= if input = then result <= ; x X Y Z Z = S X + S Y = S = + = x x x NOT Input (x )
13 Quickie Question How to connect the inputs of the MUX in order to implement an and gate? Desired function:
14 AND-function with MUX Specification: x x x X Y Z Z = x x AND S x Z = SX + SY = x x + x = x x
15 OR-function with MUX Specification: x x Z = x + x OR x X Y Z Z = x x + x x + x x = S = { SX + SY} = x ( x + x ) + x x = x = x + x x
16 XOR-function with MUX Specification: x x Z = x x XOR x x X Y Z Z = = SX + SY = x x + x x = x x x S
17 Hierarchies of muxes x x x x Z = x x x x Z s s s s
18 Complex functions with MUXes Choose any of the inputs as address inputs... z x y f = z x + xy + zy z z f... And minimize / implement function that occur? For each input. Draw new Karnaugh diagrams if necessary. x y An (n + )-input function could be implemented with a MUX having n select-inputs!
19 Shannon decomposition Claude Shannon mathematician / electrical engineer (96 2) x n f x n x x f x x n x f x f
20 Shannon decomposition A Boolean function f(x n,, x, x ) can be divided to f ( xn,..., x, x) = x f ( xn,..., x,) + x f ( xn,..., x,) The function can then be implemented with a multiplexer. x n f x n f x x x f x n x f x
21 Recursively All Boolean functions f(x n,, x, x ) can be broken down (recursively) to f ( xn,..., x, x) = x f( xn,..., x,) + x f( xn,..., x,) f x,..., x ) = x f ( x,..., x,) + x f ( x,...,,) ( n n 2 n x2 f f f f f f f f f x f and so on. f x x
22 Proof f ( xn,..., x, x) = x f ( xn,..., x,) + x f ( xn,..., x,) Right hand side: if x = so is the right term zero. Then the f is equal to the left term. if x = so is the left term zero. Then the f is equal to the right term. Left hand side: if x = so is f equal to f(x n,...,x,) if x = so is f equal to f(x n,...,x,) (= left term on right side) (= right term on right side) LHS=RHS
23 MUX networks x yz f One can see xyz as an address, to the squares in the Karnaughmap. With values / from the squares to the inputs of the MUX the function f is realized. Address Value x y Address pins z f
24 Look-up-table (LUT) Programmable cells / / / f x 2 x / A LUT with n inputs can realize all combinational functions with n inputs Two-input LUT
25 LUT for XOR-gate x x2 f f x 2 x Two-input LUT
26 A simple FPGA cell A B C D LUT f The simplest FPGA cell consists of a single Look-Up- Table - LUT, a D flip-flop and a bypass mux. D flip-flop is a memory circuit for synchronization it will come later in the course. With the bypass mux one can exclude the D flip-flop when not needed. A B C D LUT D Q CLK RESET M S D-flipflop will be explained soon in this course
27 LUT function number 3, x2, x, x) = "" f ( x = f 6996 LSB Bit # 5 Bit # Bit # MSB Do you recognize the function...? The functions that are stored in a LUT are usually numbered after the number that is made up of the 's in the truth table / Karnaugh map.
28 LUT function number 3, x2, x, x) = "" f ( x = f 6996 f = x x2 x x Odd parity! No mergings are possible. Now you know which function that has the number 6996! With a LUT, all functions are realized, so none of them are more difficult to make than any other!
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30 Decoder Mostly used as address decoder Only one output is active when the 'enable' (en) is active The active output is selected with a a en a a y y y 2 y a a en y 3 y 2 y y 2-to-4 decoder
31 Demultiplexer The demultiplexer has basically the same function as the decoder, but is drawn differently... The input is connected to a selected output f I s s y y y 2 y Now en is namned I! I y 3 y 2 y y s s
32 Read-only-memory (ROM) Sel Sel / /... / / /... / Programable bits a a... a m... Sel 2 m... / /... / Decoder En Threestate buffers d n- d n-2... d
33 6:4 Encoder Encoders have the opposite function as a decoder, ie it translates 2 N bit input to a N-bitar code. The information is concentrated Eg. Keyboard with 6 (2 4 ) keys 2 n inputs w w 2 n y y n 4-bit HEX-code for the pressed key n outputs
34 Priorityencoder A Priority Encoder gives back the address of the input with the lowest (or highest) indices that are set to a one (or zero depending on what you are looking for). If all inputs are, the output f =, else f has the value =. What if you press several keys at the same time? y y y 2 y 3 f a a Now it will be welldefined what happens if several inputs are active.
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36 Ex code Codeconverter code to BCD-code. When encoding the digits... 9 sometimes a code with weights was used instead of the binary code with the weights In cases where a digit of the code word could be selected in various ways, the code word containing the least number of ones is choosen. (a variant of the code is used today to store the bar code) You will construct such an encoder at exercice /BCD
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38 Code-converter Code-converters translates from one code to another. Typical examples are: Binary to BCD (Binary-Coded Decimal) Binary to Gray-code BCD or BIN to 7-segment decoder
39 Ex 8.5 One of the segments g 7-segment decoder consists of 7 different combinatorial circuits, one for each segment. The optimal 7-segmentdecoder has probably already been invented! One should look at Karnaughmaps for all segments simultaneously. There could be groupings that are common to several segments!
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41 Graycode or Binarycode? Wind direction Wind speed Wind direction indicator usually use Gray code to provide safe decoding.
42 Binary Code disadvantage Binary code, adjacent code words -2 double change 3-4 triple change 5-6 double change 7-8 quadruple change! 9-A double change B-C quadruple change! D-E double change F- quadruple change! But can two bits change at exactly the same time? Safe Data Registration use Graycode Data Processing Binarycode
43 Graycode By changing the order of the code words, one can find codes where it is never more than one bit at a time that changes in the transitions from one codeword to the next. Such codes are called Gray Codes.,,,,,,,,,,,,,,
44 can number the corners of a Boolean space N=4 With Gray codes one can number the "hyper-corners" in a Boolean space.
45 can solve the Towers of Hanoi Gray code is also very helpful for those who want to solve the game "Towers of Hanoi, constructed by the mathematician Edouard Lucas in 883. According to legend, three monks move 64 golden discs, of different sizes, from one bar to another. The discs should be moved one by one, and they must always be placed so that a smaller disc ports on a larger disc. When the monks are done with their work the earth will go under - it will take 2 64 moves, so the whole thing will probably take a while...
46 Conversion Binary-Gray Binary Gray: If Binary bit b n and bit b n- are different, the Graycode bit g n- ", else ". Gray Binary ( the most common transformation direction ): If Binary bit b n and Graycode bit g n- are different the Binary bit b n- is ", else ".
47 Logic Gate for the conversion XOR-gate is if the inputs are different! 4 bit code converter Gray cote to Binary code Gray/Bin
48
49 VHDL-introduction VHDL is a language used to specify the hardware HDL - Hardware Description Language VHSIC - Very High Speed Integrated Circuit Used mostly in Europe Verilog is also a language used to specify the hardware Used mostly in the United States
50 Entity C in A B FA S C out entity fulladder is port( A,B,Cin : IN std_logic; S,Cout : OUT std_logic); end fulladder; The entity describes the ports to the outside of the circuit. The circuit as a block.
51 Architecture C in A B FA S C out architecture behave of fulladder is begin S <= A xor B xor Cin; Cout <= (A and B) or (A and Cin) or (B and Cin); end behave; Architecture describes the function inside the circuit.
52 Why VHDL? VHDL is used to be able to verify that you have the right functioning by simulating the circuit be able to describe large structures in a simple way and then generate the circuit by synthesis enable structured descriptions of a circuit VHDL increases the level of abstraction!
53 Basics in VHDL There are two types of VHDL code VHDL for synthesis: The code is to be input to a synthesis tool which converts it into an implementation (for example, on an FPGA) VHDL for modeling and simulation: The code is used to describe a system in an early stage. Since the code can be simulated you can check on the intended operation is correct.
54 VHDL Hierarchie Package Generics Entity Ports Architecture Architecture Architecture (structural) Concurrent Statements Concurrent Statements Process Sequential Statements
55 Entity The primary abstraction level in VHDL is called entity In a behavioral description one defines the entity through their responses to signals and inputs A behavioral model is the same as a "black box The inside is not visible from the outside The entity's behavior is defined by the black box functionality Input Behavioral Entity Output
56 Entity An entity describes a component's interface with the outside world The PORT-declaration indicates if it is an input or output. An entity is a symbol of a component. ENTITY xor_gate IS PORT( x, y: IN bit; q: OUT bit); END xor_gate; xor_gate q Use English names for variable names in the code!
57 VHDL Port PORT declaration establishes the interface between the component and the outside world. A port declaration contains three things : The name of the port The direction of the port The port's datatype Example : ENTITY test IS PORT( name : direction data_type); END test;
58 The most common data types Scalars (signals/variables) bit (, ) std_logic ( U,,, X, Z, L, H, W, - ) integer real time Vectors (multivalued signals / variables) bit_vector vector of bit s std_logic_vector vector of std_logic
59 Architecture An architecture describes the function of the component. An entity can have many architectures, but only one can be active at a time. An architecture corresponds to the component circuit diagram or behavior. X y q Code for simulation means arrow <= ARCHITECTURE behavior OF xor_gate IS BEGIN q <= a xor b after 5 ns; END behavior;
60 VHDL-Examle: 4/ multiplexer LIBRARY ieee; USE ieee.std_logic_64.all; data_in(3) data_in(2) data_in() data_in() ce_n sel() sel() data_out ENTITY Multiplexer_4 IS PORT(ce_n : IN std_logic; -- Chip En(active low) data_in : IN std_logic_vector(3 DOWNTO ); sel : IN std_logic_vector( DOWNTO ); data_out : OUT std_logic); -- TriState Output END ENTITY Multiplexer_4;
61 VHDL-Example: 4/ multiplexer ARCHITECTURE RTL OF Multiplexer_4 IS BEGIN PROCESS(ce_n, data_in, sel) BEGIN IF ce_n = '' THEN data_out <= 'Z'; ELSE CASE sel IS WHEN ""=> data_out <= data_in(); WHEN ""=> data_out <= data_in(); WHEN ""=> data_out <= data_in(2); WHEN ""=> data_out <= data_in(3); WHEN OTHERS => null; END CASE; END IF; END PROCESS; END ARCHITECTURE RTL; Threestate!
62 Synthesis tool Quartus II QuartusII Will be used in LAB 3
63 More on VHDL The study material on the synthesis shows a number VHDL constructs and the resulting hardware The following images contain additional materials (optionally material) The book gives many examples and detailed explanations of VHDL
64 Optionally material on VHDL
65 signal declaration Signal-declaration is used inside architectures to declare internal (local) signals : signal a,b,c,d : bit; signal a,b,sum : bit_vector(3 downto ); Signal assignment is used to describing the behavior : sum <= a + b; -- assignment without delay
66 VHDL description various styles Structural similar to how to connect components Sequential similar to how to write computer programs Data Flow Concurrent assignments
67 Sequential or Parallel Code There are two types of code execution in VHDL: sequential and parallel Hardware can then be modeled in two different ways VHDL is supporting two different levels of abstraction. Sequential code describes the hardware from a programmer's point of view and are executed in the order it is written. The parallel code is executed regardless of the order it is in and is asynchronous.
68 Sequential style XOR-gate x y q process(x,y) begin if (x/=y) then q <= ; else q <= ; end if; end process; means not!
69 Data flow style XOR-gate x y q q <= a xor b; Or as behavioural dataflow style not equal q <= when a/=b else ;
70 Structural style x y xi yi t3 t4 q u: not_gate port map (x,xi); u2: not_gate port map (y,yi); u3: and_gate port map (xi,y,t3); u4: and_gate port map (yi,x,t4); u5: or_gate port map (t3,t4,q);
71 Structural code in in2 out A component must be declared before it can be used ARCHITECTURE test OF test_entity COMPONENT and_gate PORT ( in, in2 : IN BIT; out : OUT BIT); END COMPONENT;... more statements... Required, unless it is is already in a library somewhere
72 Instantiation Component instantiation connects the component interface with the signals in the architecture. ARCHITECTURE test OF test_entity COMPONENT and_gate in PORT ( in, in2 : IN BIT; out : OUT BIT); in2 END COMPONENT; SIGNAL S, S2, S3 : BIT; BEGIN Gate : and_gate PORT MAP (S,S2,S3); END test; out S S2 S3
73 generate Generate-statement connects many of the same elements ENTITY adder IS GENERIC(N:integer) PORT(a,b:IN bit_vector(n- downto ); sum:out bit_vector(n- downto )); END adder; ARCHITECTURE structural OF adder IS COMPONENT full_adder PORT(a,b,cin:IN bit;cout,s:out bit); END COMPONENT; signal c:bit_vector(n-2 downto ); BEGIN G:for i in to N-2 generate U:full_adder PORT MAP (a(i),b(i),c(i-),c(i),s(i)); end generate; -- G U:full_adder PORT MAP (a(),b(),,c(),s()); UN:full_adder PORT MAP (a(n-),b(n-),c(n-2),open,s(n-); END structural; Generate an n- bit adder!
74 generate n-bit adder a n- b n- a b a b c utn- FA c inn- FA c in c ut FA c in s n- s s Five lines of code generates the ripple-carry n-bit adder from F5!
75 Test Benches To test if your design works so you have to create a test bench. It has three functions : Generating stimuli for simulation Apply these stimuli to an entity to be tested Comparing the output values with expected values You will use a test bench at LAB 3. A test bench program can try tirelessly through all input combinations!
76 Testbench ENTITY testbench IS END testbench; ARCHITECTURE xor_stimuli_ of testbench IS COMPONENT xor_gate PORT(x,y:IN bit; q:out bit); END COMPONENT; signal x,y,u,ut2,ut3:bit; BEGIN x <= not(x) after ns; y <= not(y) after 2 ns; U:xor_gate PORT MAP (x,y,ut); U2:xor_gate PORT MAP (x,y,ut2); U3:xor_gate PORT MAP (x,y,ut3); END example; The ENTITY is empty! The circuit under test is used as a component of the test bench program Here are the test signals generated
77 Testbench A test bench can mark when the desired events occur during the execution. Or mark when unwanted events occur The result of a run with a test bench can be saved in a file, as proof that everything is ok - or as a troubleshooting aid if it did not go well.
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