CS221: VHDL Models & Synthesis
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1 CS221: VHDL Models & Synthesis Dr. A. Sahu DeptofComp.Sc.&Engg. Indian Institute of Technology Guwahati 1
2 Examples : Outline N BitRipple Adder, Mux, Register, FSM VHDL Model DataFlow Component BehavioralModel VHDL Synthesis 2
3 NBitRippleCarryAdder: FA ENTITY full_adder IS PORT(a, b, c_in: INstd_logic; Sum, Carry: OUTstd_logic); END full_adder; ARCHITECTUREfull_adder_arch_1 OF full_adder IS SIGNALS1, S2, S3: std_logic; BEGIN s3 <= ( a ANDb ) after 5 ns; s2 <= ( c_inands1 ) after 5 ns; s1 <= ( a XOR b ) after 15 ns; Carry <= ( s2 ORs3 ) after 5 ns; Sum <= ( s1 XORcin) _ after 15 ns; ENDfull_adder_arch_1; 3
4 NBitRippleCarryAdder ENTITY adder_bits_nis GENERIC(n: INTEGER := 2); PORT( Cin: IN std_logic; a, b: IN std_logic_vector(n 1 downto0); S: OUTstd_logic_vector(n 1 downto0); Cout:OUTstd OUTstd_logic ); END; 4
5 NBitRippleCarryAdder ARCHITECTUREripple_n_archOF adder_bits_nis COMPONENT full_adder PORT(x, y, z: INstd_logic; Sum, Carry: OUTstd_logic); END COMPONENT; SIGNAL t: std_logic_vector(n downto 0); BEGIN t(0) <= Cin; Cout<= t(n); FA: FORiin0 ton 1 GENERATE FA_i: full_adderport MAP (t(i), a(i), b(i), S(i), t(i+1)); end generate; END; 5
6 Test benches for 4 bit adder: Stimulus only ARCHITECTURE tb OF tb_adder_4 IS COMPONENT adder_bits_n GENERIC(n: INTEGER:= 2); PORT( Cin: IN std_logic; a, b: IN std_logic_vector(n 1 downto0); S: OUT std_logic_vector(n 1 downto0); Cout: OUTstd_logic); ENDCOMPONENT; SIGNAL x, y, Sum: std_logic_vector(n downto0); SIGNAL c, Cout: std_logic; BEGIN x <= 0000, 0001 after 200 ns, 0101, after 400 ns; y <= 0010, 0011 after 200 ns, 1010, after 400 ns; c <= 1, 0 after 200 ns; UUT_ADDER_4: adder_bits_ngeneric MAP(4) PORT MAP (c, x, y, Sum, Cout); END 6
7 4 bit multiplexor 4x1 I0 I1 I2 I3 4x1 Mux Y 4 Bit : 3downto0 S1 S0 entity Mux is port( I3: in std_logic_vector(3 downto0); I2: instd_ logic_ vector(3 downto0); I1: instd_logic_vector(3 downto0); I0: instd_logic_vector(3 downto0); S: instd_logic_vector(1 downto0); O: outstd_logic_vector(3 downto0) ); end Mux; 7
8 Architectureof4x1Mux architecturebehvioralof Muxis Begin process (I3,I2,I1,I0,S) begin use case statement cases is when"00" => O <= I0; when"01"=> O<=I1; when"10" => O <= I2; when"11" => O <= I3; whenothers => O <= "ZZZ"; end case; end process; end behvioural; 8
9 Resister entityregis is port( rst, clk, load: instd_logic; input: in std_logic_vector( 3 downto 0 ); output: out std_logic_vector( 3 downto 0 ) ); end regis; architecture regis_arc of regis is begin process( rst, clk, load, input ) begin if( rst= '1') then output <= "0000"; elsif( clk'eventandclk= '1') then if( load = '1') then output <= input; endif; endif; end process; end regis_arc; 9
10 HowtoWriteFSMisVHDL is Init S0 S1 S xxx00 S C= 01 C= 11 entity fsm is port( rst, clk,proceed: in std_logic; comparison: in std_logic_vector( 1 downto 0 ); enable, xsel, ysel, xld, yld: out std_logic ); end fsm; C= 10 S3 S
11 FSMArchitecture architecturefsm_arcoffsmis typestates is( init, s0, s1, s2, s3, s4, s5 ); signalnstate, cstate: states; begin Process1: process( rst, clk) begin if(rst='1')then 1 ) then end ; cstate<= init; elsif( clk'eventandclk= '1') then cstate<= nstate; end if; end process; 11
12 FSM Architecture process( proceed, comparison, cstate) begin variable : OP : std_loic_vector(4 downto 0); case cstate is when init => if( proceed = '0') then nstate<= init; else nstate<= s0; end if; when s0 => OP <= ; nstate<= s1; when s1 => OP< <= ; nstate<= t s2; when s2 => OP<= XXX01 ; if( comparison = "10") then nstate<= s3; elsif(comparison="01")then nstate<=s4; elsif( comparison = "11") then nstate<= s5; end if; when s3 => OP <= nstate<= s2; when s4 => OP <= ; nstate<= s2; when s5 => OP <= ; nstate<= s0; when others => nstate<= s0; end case; enable <= OP(4); xsel<= OP(3);ysel<= OP(2);xld<= OP(1);yld<= OP(0); end process; end fsm_arc; 12
13 DataFlow: FullAdder ENTITY full_adder IS PORT(a, b, c_in: INstd_logic; Sum, Carry: OUTstd_logic); END full_adder; ARCHITECTURE Data_FlowOF full_adder IS SIGNALS1, S2, S3: std_logic; BEGIN s3 <= ( a ANDb ) after 5 ns; s2 <= ( c_inands1 ) after 5 ns; s1 <= ( a XOR b ) after 15 ns; Carry <= ( s2 ORs3 ) after 5 ns; Sum <= ( s1 XORcin) _ after 15 ns; ENDfull_adder_arch_1; 13
14 Components : FA Architecture structural of Full_adder is component XOR_GATE is port( X, Y : instd_logic; F2: outstd_logic ); end component; component AND_GATE is port( X, Y : instd_ logic; F2: outstd_ logic ); end component; component OR_GATE is.. signals1, s2.s3: s3: std_logic; signal signaljustlikewire like Begin XOR1: XOR_GATE port map (a, b, s1); AND1: AND_GATE port map (a, b, s3); AND2 : AND_GATE port map(c_in, s1, s2); OR1 : OR_ GATE port map(s2,s3, Carry); XOR2: XOR_GATE port map(s1,c_in, Sum); end structural; 14
15 Behavioral Model architecture BEHAV_FA of FULL_ADDER is signalint1, int2, int3: std_logic; Begin Process P1 that defines the first half adder P1: process(a, B) begin int1<= A xorb; int2<= A andb; end process; ProcessP2that P2 defines the second half adder and the OR gate P2: process(int1, int2, Cin) begin Sum <= it1orci int1 xorcin; int3 <= int1 and Cin; Cout<= int2 or int3; end process; end BEHAV_FA; 15
16 HardwareSpecification Layout editor directly enter layout Up to ~10 2 of unique transistors Complexcircuits Memory, aided by generators Schematic Capture Enter gates and interconnections Up to ~10 4 transistors HardwareDescription Languages Enter text description 10 7 transistors a b Entity.. If (x < y) then Y=xandz;. F 16
17 Hardware Specification Complexity Maintainability and Modifiability Optimal Efficiency a b F Etit Entity.. If (x < y) then Y=x and z;.
18 ICDesignProcess Idea Layout Die Tested Die Di Design Fbi Fabrication Tti Testing Pki Packaging Specification Implementation Model Synthesis Verification & Simulation 18
19 Hardware/SoftwareDesignFlow HW Specification SW Specification Synthesis Compilation Fabrication Layout IC Binary Code 19
20 Model RepresentationofabstractviewoftheSystem of abstract of the Varying abstractions functional only timing only functional + timing 20
21 Modelling:levelofdetail level of detail Behavioral Level no clock cycle level commitment Register Transfer Level (RTL) Operations committed to clock cycles Gate level structural netlist for (i=0;i <4;i++) S = S+ A[i] Cycle1: T1=A[0]+A[1] A[1] T2 = A[2] + A[3] Cycle 2: S = T1 + T2 21
22 HDL Layout HDL Gates Gates Layout Synthesis Entity.. If (x < y) then Y=x and z;. HW Specification a b F Synthesis Layout 22
23 Synthesis Behavioral Synthesis (Process& Sequential) Behavioral HDL RTL HDL No NonotionofclocktoClocked of to RTL Synthesis RTL HDL Gates Layout Synthesis Gates Layout 23
24 Behavioral Synthesis DesignFlow Behavioral Model RTL Model for (i=0;i <4;i++) S = S+ A[i] Cycle 1: T1 = A[0] + A[1] T2 = A[2] + A[3] Cycle 2: S = T1 + T2 RTL Synthesis Logic Synthesis Layout Synthesis Gate Model OptimalGate Model Layout a b F 24
25 25
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