Case Study AM2901. Hierarchy in Large Designs

Transcription

1 Case Study AM2901 Hierarchy in Large Designs As a means to illustrate how a VHDL description for a meaningful digital system can be developed, we attempt to write a model for an Am2901 that is a 4 -bit microprocessor slice. The architecture consists of an ALU with multiple sources, controlled by two multiplexers, a set of RAM registers, I/O and control. As the Am2901 is a bit -slice device, processors with wordlengths of any multiple of 4, can be constructed. We will see that the Am2901 will allow us to un derstand design decomposition and the importance of hierarchy, reusable libraries, packages and parameterised components. The basic architecture is shown in Figures 1 and 2. Figure 1: Architecture of Am2901 ( Advanced Micro Devices Inc.) Stuart Lawson Page 1 17/10/2001

2 Figure 2: Am2901 Architecture used in discussion. The functional units are as follows: 1. RAM_REGS This is a 16 word dual -port RAM which we are going to realize using flip - flops. FPGA architectures with on -board RAM may be more efficient in terms of area but may make t he VHDL description non -portable. As can be seen from Fig.1, an input shifter allows data to be loaded which has been pre-shifted to the left or the right by one bit -position or unaltered. RAM0 and RAM3 are bidirectional signals used for the shift -in and s hift-out values. RAM_REGS is addressed by two 4 -bit addresses a and b. The corresponding data outputs are ad and bd. In write mode, the data at d (ALU output) is written to the address specified by b. 2. Q_REG This is a one -word register with a shift input. I ts use is primarily for multiplication and division functions. The signals qs0 and qs3 are bidirectional used for the shifting process. Stuart Lawson Page 2 17/10/2001

3 3. SRC_OP This block chooses the ALU source operands from ad, bd, the output of Q_REG, q, and direct data input, d. 4. ALU The ALU performs one of three arithmetic and five logic functions on the source operands. 5. OUT_MUX The output multiplexer chooses between the ALU output and the from RAM_REGS. ad output Mnemonic Microcode ALU Source Operands I 2 I 1 I 0 Octal R S Code AQ A Q AB A B ZQ Q ZB B ZA A DA D A DQ D Q DZ D 0 Table 1: ALU Source Operands Mnemonic Microcode ALU function I 5 I 4 I 3 Octal Code ADD R + S SUBR S - R SUBS R - S OR R OR S AND R AND S NOTRS (NOT R) and S EXOR R XOR S EXNOR R XNOR S Table 2: ALU function table Stuart Lawson Page 3 17/10/2001

4 Mnemonic Microcode RAM Function Q-Reg Function Y RAM Shifter Q Shifter Outpu t I8 I7 I6 Octal Code Shift Load Shift Load RAM0 RAM3 Q0 Q3 QREG X NONE NONE F->Q F X X X X NOP X NONE X NONE F X X X X RAMA NONE F->B X NONE A X X X X RAMF NONE F->B X NONE F X X X X RAMQD DOWN F/2->B DOWN Q/2->Q F F0 IN3 Q0 IN3 RAMD DOWN F/2->B X NONE F F0 IN3 Q0 X RAMQU UP 2F->B UP 2Q->Q F IN0 F3 IN0 Q3 RAMU UP 2F->B X NONE F IN0 F3 X Q3 Table 3: ALU Destination Table where X is don t care, B is register addressed by b address. UP is towards MSB, DOWN is towards LSB. Stuart Lawson Page 4 17/10/2001

5 The 2901 is controlled by a 9 -bit microinstruction (see Fig.1). However there may be other bits for branching around the microprogram. The use of a microprogram sequencer may be useful in this regard. Note the inputs and outputs of the A LU, other than the source operands and destination output, R, S and F. The signals in question are explained in Table 4. Signal name Input or Output Function c n I Carry input. Used for ripple -carry addition/subtraction when cascading chips. c n+4 O Carry output. Used for ripple -carry addition/subtraction when cascading chips. g_bar O Generate output. Used with carry look -ahead chip when cascading 2901s. Faster than ripple carry. p_bar O Propagate Output. Used with carry look -ahead chip when cascading 2901s. Faster than ripple carry. ovr O Arithmetic overflow indicator f_0 O True when ALU output is zero f3 O Most significant bit of output. Used to test whether result is positive or negative. Table 4: ALU inputs and outputs Building a library of components To develop a VHDL model for the Am2901, we will need some basic components. We will use a library made up of several packages. Each package contains a set of common component types such as flip -flops, registers, counters and synchronizers. To be fl exible, components will be specified in several widths. To, we will look at the design of a 1-bit wide D-type FF with an asynchronous reset. To enable the use of multi-bit FFs (registers) we will parameterize our design. -- Set of D-Type Flip-Flops sizes: (1, size) clk -- posedge clock input -- reset -- asynchronous reset -- d -- register input -- q -- register output entity rdff1 is port ( clk, reset: in std_logic; d: in std_logic; q: buffer std_logic); Stuart Lawson Page 5 17/10/2001

6 end rdff1; architecture archrdff1 of rdff1 is p1: process (reset, clk) if reset = '1' then q <= '0'; elsif (clk'event and clk='1') then q <= d; end process; end archrdff1; entity rdff is generic (size: integer := 2); port ( clk, reset: in std_logic; d: in std_logic_vector(size-1 downto 0); q: buffer std_logic_vector(size-1 downto 0)); end rdff; architecture archrdff of rdff is p1: process (reset, clk) if reset = '1' then q <= (others => '0'); elsif (clk'event and clk='1') then q <= d; end process; end archrdff; Note that i/o mode buffer is being used for output ports even if we could use mode out. This is being done to make it easier for a team design. The approach is illustrated in Figur e 3 and compares it with the use of mode out for all outputs. a b x: buffer std_logic c y: buffer std_logic Figure 3: Using mode buffer Stuart Lawson Page 6 17/10/2001

7 The use of the construct generic allows us to parameterize the D-type FF. Effectively it gives us dynamic vector declarations. The next step is to design a set of registers from D -type FF with synchronous enables and asynchronous resets. This design will also allow variable widths. -- Set of registers -- sizes: (1,size) clk -- posedge clock input -- reset -- asynchronous reset -- load -- active high input loads rregister -- d -- register input -- q -- register output entity rreg1 is port( clk, reset, load: in std_logic; d: in std_logic; q: buffer std_logic); end rreg1; architecture archrreg1 of rreg1 is p1: process (reset, clk) if reset = '1' then q <= '0'; elsif (clk'event and clk='1') then if load = '1' then q <= d; end process; end archrreg1; entity rreg is generic (size: integer := 2); port( clk, reset, load: in std_logic; d: in std_logic_vector(size-1 downto 0); q: buffer std_logic_vector(size-1 downto 0)); end rreg; architecture archrreg of rreg is p1: process (reset,clk) if reset = '1' then q <= (others => '0'); elsif (clk'event and clk='1') then Stuart Lawson Page 7 17/10/2001

8 if load = '1' then q <= d; end process; end archrreg; We will also need a general purpose register with a synchronous load. synchronous reset and preset and -- Register Set -- sizes: (size) a generic clk -- posedge clock input -- rst -- asynchronous reset -- pst -- asynchronous preset -- load -- active high input loads register -- d -- register input -- q -- register output entity reg is generic ( size: integer := 2); port( clk, load: in std_logic; rst, pst: in std_logic; d: in std_logic_vector(size-1 downto 0); q: buffer std_logic_vector(size-1 downto 0)); end reg; architecture archreg of reg is p1: process (clk) if rst = '1' then q <= (others => '0'); elsif pst = '1' then q <= (others => '1'); elsif (clk'event and clk='1') then if load = '1' then q <= d; else q <= q; end process; end archreg; In the above code, size cannot be equal to 1. This is because of the use of q <= ( others => 1 ) which implies that q is an array or aggregate. Stuart Lawson Page 8 17/10/2001

9 We now need to create some counters with asynchronous resets and synchronous initialisation and enables. If we wish to implement a counter with, say the asynchronous reset disabled then in its instantiation, the input will be permanently set to 0. This will result in reduced logic. Similarly if an output is not required then it can be left open thus c_out => open. We cannot however leave inputs open. The code for the counters follows: -- Synchronous Counter of Generic Size CounterSize -- size of counter clk -- posedge clock input -- areset -- asynchronous reset -- sreset -- active high input resets counter to 0 -- enable -- active high input enables counting -- count -- counter output use work.std_arith.all; entity ascount is generic (CounterSize: integer := 2); port( clk, areset, sreset, enable: in std_logic; count: buffer std_logic_vector(countersize-1 downto 0)); end ascount; architecture archascount of ascount is p1: process (areset, clk) if areset = '1' then count <= (others => '0'); elsif (clk'event and clk='1') then if sreset='1' then count <= (others => '0'); elsif enable = '1' then count <= count + 1; else count <= count; end process; end archascount; Next two synchronization components will be designed. These consist of t wo D-type FFs in series and are used to synchronize asynchronous inputs to the system clock. One of the synchronizers has an asynchronous reset whilst the other has an asynchronous preset. -- Synchronizers clk -- posedge clock input -- reset -- asynchronous reset (rsynch) Stuart Lawson Page 9 17/10/2001

10 -- preset -- asynchronous preset (psynch) -- d -- signal to synchronize -- q -- synchronized entity rsynch is port ( clk, reset: in std_logic; d: in std_logic; q: buffer std_logic); end rsynch; architecture archrsynch of rsynch is signal temp: std_logic; p1: process (reset, clk) if reset = '1' then q <= '0'; elsif (clk'event and clk='1') then temp <= d; q <= temp; end process; end archrsynch; entity psynch is port ( clk, preset: in std_logic; d: in std_logic; q: buffer std_logic); end psynch; architecture archpsynch of psynch is signal temp: std_logic; p1: process (preset, clk) if preset = '1' then q <= '1'; elsif (clk'event and clk='1') then temp <= d; q <= temp; end process; end archpsynch; The final member of the library of components that we are building is a set of unsigned registers that will help in the design of the Am2901. For this we will use the following standard package numeric_std. Stuart Lawson Page 10 17/10/2001

11 -- Set of registers (unsigned) -- sizes: (1,size) clk -- posedge clock input -- reset -- asynchronous reset -- load -- active high input loads rregister -- d -- register input -- q -- register output use work.numeric_std.all; entity ureg is generic (size: integer := 2); port( clk, reset, load: in std_logic; d: in unsigned(size-1 downto 0); q: buffer unsigned(size-1 downto 0)); end ureg; architecture archureg of ureg is p1: process (reset,clk) if reset = '1' then q <= (others => '0'); elsif (clk'event and clk='1') then if load = '1' then q <= d; else q <= q; end process; end archureg; Having now defined all the building blocks that we will require for the Am2901 design, it is necessary to place them in packages so that they can be used easily. Three packages will be created: regs_pkg, counters_pkg, synch_pkg. 1. regs_pkg use work.numeric_std.all; package regs_pkg is component rdff1 port ( clk, reset: in std_logic; d: in std_logic; q: buffer std_logic); component rdff Stuart Lawson Page 11 17/10/2001

12 generic (size: integer := 2); port ( clk, reset: in std_logic; d: in std_logic_vector(size-1 downto 0); q: buffer std_logic_vector(size-1 downto 0)); component pdff1 port ( clk, preset: in std_logic; d: in std_logic; q: buffer std_logic); component rreg1 port( clk, reset, load: in std_logic; d: in std_logic; q: buffer std_logic); component rreg generic (size: integer := 2); port( clk, reset, load: in std_logic; d: in std_logic_vector(size-1 downto 0); q: buffer std_logic_vector(size-1 downto 0)); component preg1 port( clk, preset, load: in std_logic; d: in std_logic; q: buffer std_logic); component preg generic(size: integer := 2); port( clk, preset, load: in std_logic; d: in std_logic_vector(size-1 downto 0); q: buffer std_logic_vector(size-1 downto 0)); component reg generic ( size: integer := 2); port( clk, load: in std_logic; rst, pst: in std_logic; d: in std_logic_vector(size-1 downto 0); q: buffer std_logic_vector(size-1 downto 0)); component ureg generic (size: integer := 2); port( clk, reset, load: in std_logic; d: in unsigned(size-1 downto 0); q: buffer unsigned(size-1 downto 0)); end regs_pkg; 2. counters_pkg Stuart Lawson Page 12 17/10/2001

13 package counters_pkg is component ascount generic (CounterSize: integer := 2); port( clk, areset, sreset, enable: in std_logic; count: buffer std_logic_vector(countersize -1 downto 0)); end counters_pkg; 3. synch_pkg package synch_pkg is component rsynch port ( clk, reset: in std_logic; d: in std_logic; q: buffer std_logic); component psynch port ( clk, preset: in std_logic; d: in std_logic; q: buffer std_logic); end synch_pkg; These packages can be compiled into a library from where they can be accessed using the use construct. For example if the library is called basic then access to it can be effected by the construct library bas ic. Individual packages or components within can be accessed by using the following as example: library basic; use basic.regs_pkg.rreg1; use basic.regs_pkg.all; -- makes library accessible -- makes rreg1 component declaration visible -- make all components in regs_pkg visible Designing the components of the Am2901 for-bit slice microprocessor Types to be used Control inputs and outputs: std_logic Microinstruction: std_logic_vector Address and Data: unsigned defined in numeric_std A package definin g all the mnemonics introduced in Tables 1 to 3 will be setup now. These mnemonics will make programming the Am2901 easier. Stuart Lawson Page 13 17/10/2001

14 package mnemonics is -- ALU source operand control mnemonics constant aq: std_logic_vector(2 downto 0) := "000"; constant ab: std_logic_vector(2 downto 0) := "001"; constant zq: std_logic_vector(2 downto 0) := "010"; constant zb: std_logic_vector(2 downto 0) := "011"; constant za: std_logic_vector(2 downto 0) := "100"; constant da: std_logic_vector(2 downto 0) := "101"; constant dq: std_logic_vector(2 downto 0) := "110"; constant dz: std_logic_vector(2 downto 0) := "111"; -- ALU function control mnemonics constant add: std_logic_vector(2 downto 0) := "000"; constant subr: std_logic_vector(2 downto 0) := "001"; constant subs: std_logic_vector(2 downto 0) := "010"; constant orrs: std_logic_vector(2 downto 0) := "011"; constant andrs:std_logic_vector(2 downto 0) := "100"; constant notrs:std_logic_vector(2 downto 0) := "101"; constant exor: std_logic_vector(2 downto 0) := "110"; constant exnor:std_logic_vector(2 downto 0) := "111"; -- ALU destination contol mnemonics constant qreg: std_logic_vector(2 downto 0) := "000"; constant nop: std_logic_vector(2 downto 0) := "001"; constant rama: std_logic_vector(2 downto 0) := "010"; constant ramf: std_logic_vector(2 downto 0) := "011"; constant ramqd: std_logic_vector(2 downto 0) := "100"; constant ramd: std_logic_vector(2 downto 0) := "101"; constant ramqu: std_logic_vector(2 downto 0) := "110"; constant ramu: std_logic_vector(2 downto 0) := "111"; end mnemonics; Register File Now we can concentrate finally on the Am2901 components. Firstly consider the design of RAM_REGS. The hardware architecture is shown i n Figure 4. There are sixteen 4 -bit wide registers made up from flip-flops. Note that four 3 to 1 multiplexers appear at the input to the register file. These are used for the shifting operation. A construct that we have not seen before is used here, namely the with.select construct. An example of its use in the implementation of a 2-4 decoder is shown below: architecture with_select of decoder is with a select z <= 0001 when 00, 0010 when 01, 0100 when 10, 1000 when 11, XXXX when others; end architecture with_select; Stuart Lawson Page 14 17/10/2001

15 library ieee, basic; use work.numeric_std.all; use work.mnemonics.all; use basic.regs_pkg.all; --Following added for Warp to find entities in basic library use basic.ureg; entity ram_regs is port ( clk, rst: in std_logic; a, b: in unsigned(3 downto 0); f: in unsigned(3 downto 0); dest_ctl: in std_logic_vector(2 downto 0); ram0, ram3: inout std_logic; ad, bd: buffer unsigned(3 downto 0)); end ram_regs; architecture ram_regs of ram_regs is signal ram_en: std_logic; signal data: unsigned(3 downto 0); signal en: std_logic_vector(15 downto 0); type ram_array is array (15 downto 0) of unsigned(3 downto 0); signal ab_data: ram_array; -- define register array: gen: for i in 15 downto 0 generate ram: ureg generic map (4) port map (clk, rst, en(i), data, ab_data(i)); end generate; -- decode b to determine which register is enabled: with dest_ctl select ram_en <= '0' when qreg nop, '1' when others; decode_b: process (b) for i in 0 to 15 loop if to_integer(b) = i then en(i) <= ram_en; else en(i) <= '0'; end loop; end process; -- define data input to register array: with dest_ctl select data <= (f(2), f(1), f(0), ram0) when ramqu ramu, -- shift-up (ram3, f(3), f(2), f(1)) when ramqd ramd, -- shift-down f when rama ramf, Stuart Lawson Page 15 17/10/2001

16 "----" when others; -- define reg_array output for a and b regs: ad <= ab_data(to_integer(a)); bd <= ab_data(to_integer(b)); -- define ram0 and ram3 inouts: ram3 <= f(3) when (dest_ctl = ramu or dest_ctl = ramqu) else 'Z'; ram0 <= f(0) when (dest_ctl = ramd or dest_ctl = ramqd) else 'Z'; end ram_regs; Q-register Figure 4: Architecture of Register File To implement the Q-register we use the component ureg from the basic library. The register has a shifter on its input data lines and a decoder for the relevant part of the microinstruction. Its architecture is shown in Figure 5. Stuart Lawson Page 16 17/10/2001

17 Figure 5: Architecture of Q register library ieee, basic; use work.numeric_std.all; use work.mnemonics.all; use basic.regs_pkg.all; --Following added for Warp to find entities in basic library use basic.ureg; entity q_reg is port( clk, rst: in std_logic; f: in unsigned(3 downto 0); dest_ctl: in std_logic_vector(2 downto 0); qs0, qs3: inout std_logic; q: buffer unsigned(3 downto 0)); end q_reg; architecture q_reg of q_reg is signal q_en: std_logic; signal data: unsigned(3 downto 0); -- define q register: u1: ureg generic map (4) port map(clk, rst, q_en, data, q); -- define q_en: with dest_ctl select Stuart Lawson Page 17 17/10/2001

18 q_en <= '1' when qreg ramqd ramqu, '0' when others; -- define data input to q register: with dest_ctl select data <= (f(2), f(1), f(0), qs0) when ramqu, -- shift-up (qs3, f(3), f(2), f(1)) when ramqd, -- shift-down f when qreg, "----" when others; -- define q0 and q3 inouts: qs3 <= f(3) when (dest_ctl = ramu or dest_ctl = ramqu) else 'Z'; qs0 <= f(0) when (dest_ctl = ramd or dest_ctl = ramqd) else 'Z'; end q_reg; Source operand selector, SRC_OP Source operands are chosen from a number of sources by the use of multiplexers. The microinstruction reserves 4 bits for the various options (see Table 1). The architecture is shown in Figure 6. Figure 6: Architecture of source operand selector use work.numeric_std.all; use work.mnemonics.all; entity src_op is port( d, ad, bd, q: in unsigned(3 downto 0); src_ctl: in std_logic_vector(2 downto 0); r, s: buffer unsigned(3 downto 0)); Stuart Lawson Page 18 17/10/2001

19 end src_op; architecture src_op of src_op is -- decode alu operand r: with src_ctl select r <= ad when aq ab, "0000" when zq zb za, d when others; with src_ctl select s <= q when aq zq dq, bd when ab zb, ad when za da, "0000" when others; end src_op; Arithmetic and Logic Unit (ALU) The ALU is defined by the function table of Table 2. It has two source operands, one output all four bits wide together with several single bit inputs and outputs to aid cascading of chips such as carry -in and carry -out for ripple carry addition and g, p for carry look -ahead addition. Three bits of each microinstruction is allocated to select the ALU function. Note that before the ALU operation is performed, the input operands are extended by one bit to accommodate carry and overflow operations. use work.numeric_std.all; use work.mnemonics.all; entity alu is port ( r, s: in unsigned(3 downto 0); c_n: in std_logic; alu_ctl: in std_logic_vector(2 downto 0); f: buffer unsigned(3 downto 0); g_bar, p_bar: buffer std_logic; c_n4: buffer std_logic; ovr: buffer std_logic); end alu; architecture alu of alu is signal r1, s1, f1: unsigned(4 downto 0); r1 <= ('0', r(3), r(2), r(1), r(0)); s1 <= ('0', s(3), s(2), s(1), s(0)); alu: process (r1, s1, c_n, alu_ctl) case alu_ctl is when add => if c_n = '0' then f1 <= r1 + s1; Stuart Lawson Page 19 17/10/2001

20 else f1 <= r1 + s1 + 1; when subr => -- subtraction same as 2's comp addn if c_n = '0' then f1 <= r1 + not(s1); else f1 <= r1 + not(s1) + 1; when subs => if c_n = '0' then f1 <= s1 + not(r1) + 1; else f1 <= s1 + r1; when orrs => f1 <= r1 or s1; when andrs => f1 <= r1 and s1; when notrs => f1 <= not r1 and s1; when exor => f1 <= r1 xor s1; when exnor => f1 <= not( r1 xor s1); when others => f1 <= "-----"; end case; end process; f <= f1(3 downto 0); c_n4 <= f1(4); g_bar <= not ( (r(3) and s(3)) or ((r(3) or s(3)) and (r(2) and s(2))) or ((r(3) or s(3)) and (r(2) or s(2)) and (r(1) and s(1))) or ((r(3) or s(3)) and (r(2) or s(2)) and (r(1) or s(1)) and (r(0) and s(0)))); p_bar <= not ( (r(3) or s(3)) and (r(2) or s(2)) and (r(1) and s(1)) and (r(0) and s(0))); ovr <= '1' when (f1(4) /= f1(3)) else '0'; end alu; The output multiplexer (OUT_MUX) Finally a 2-1 multiplexer is design ed. Its inputs are the ALU output and the from the register file. Its VHDL code is the simplest of all the building blocks. ad data output use work.numeric_std.all; use work.mnemonics.all; entity out_mux is port( ad, f: in unsigned(3 downto 0); dest_ctl: in std_logic_vector(2 downto 0); oe: in std_logic; y: buffer unsigned(3 downto 0)); Stuart Lawson Page 20 17/10/2001

21 end out_mux; architecture out_mux of out_mux is signal y_int: unsigned(3 downto 0); y_int <= ad when dest_ctl = rama else f; y <= y_int when oe = '0' else "ZZZZ"; end out_mux; -- output before tri-state buffer Note that the output multiplexer has a tri -state output that is controlled by the output enable, oe. Top level of Am2901 We can now connect the Am2901 building blocks together to complete the design. In the final bit of VHDL code we need first to have a component declaration for each of the five building blocks thus: use work.numeric_std.all; package am2901_comps is component ram_regs port ( clk, rst: in std_logic; a, b: in unsigned(3 downto 0); f: in unsigned(3 downto 0); dest_ctl: in std_logic_vector(2 downto 0); ram0, ram3: inout std_logic; ad, bd: buffer unsigned(3 downto 0)); component q_reg port( clk, rst: in std_logic; f: in unsigned(3 downto 0); dest_ctl: in std_logic_vector(2 downto 0); qs0, qs3: inout std_logic; q: buffer unsigned(3 downto 0)); component src_op port( d, ad, bd, q: in unsigned(3 downto 0); src_ctl: in std_logic_vector(2 downto 0); r, s: buffer unsigned(3 downto 0)); component alu port ( r, s: in unsigned(3 downto 0); c_n: in std_logic; alu_ctl: in std_logic_vector(2 downto 0); f: buffer unsigned(3 downto 0); g_bar, p_bar: buffer std_logic; c_n4: buffer std_logic; Stuart Lawson Page 21 17/10/2001

22 ovr: buffer std_logic); component out_mux port( ad, f: in unsigned(3 downto 0); dest_ctl: in std_logic_vector(2 downto 0); oe: in std_logic; y: buffer unsigned(3 downto 0)); end am2901_comps; Finally we can instantiate each of the five building blocks, effectively connecting together as in Figures 1 and 2. use work.numeric_std.all; use work.am2901_comps.all; entity am2901 is port( clk, rst: in std_logic; a, b: in unsigned(3 downto 0); -- address inputs d: in unsigned(3 downto 0); -- direct data i: in std_logic_vector(8 downto 0); -- micro instruction c_n: in std_logic; -- carry in oe: in std_logic; -- output enable ram0, ram3: inout std_logic; -- shift lines to ram qs0, qs3: inout std_logic; -- shift lines to q y: buffer unsigned(3 downto 0); -- data outputs (3-state) g_bar,p_bar: buffer std_logic; -- carry generate, propagate ovr: buffer std_logic; -- overflow c_n4: buffer std_logic; -- carry out f_0: buffer std_logic; -- f = 0 f3: buffer std_logic); -- f(3) w/o 3-state end am2901; architecture am2901 of am2901 is alias dest_ctl: std_logic_vector(2 downto 0) is i(8 downto 6); alias alu_ctl: std_logic_vector(2 downto 0) is i(5 downto 3); alias src_ctl: std_logic_vector(2 downto 0) is i(2 downto 0); signal ad, bd: unsigned(3 downto 0); signal q: unsigned(3 downto 0); signal r, s: unsigned(3 downto 0); signal f: unsigned(3 downto 0); -- instantiate and connect components u1: ram_regs port map(clk => clk, rst => rst, a => a, b => b, f => f, dest_ctl => dest_ctl, ram0 => ram0, ram3 => ram3, ad => ad, bd => bd); u2: q_reg port map(clk => clk, rst => rst, f => f, dest_ctl => dest_ctl, qs0 => qs0, qs3 => qs3, q => q); Stuart Lawson Page 22 17/10/2001

23 u3: src_op port map(d => d, ad => ad, bd => bd, q => q, src_ctl => src_ctl, r => r, s => s); u4: alu port map(r => r, s => s, c_n => c_n, alu_ctl => alu_ctl, f => f, g_bar => g_bar, p_bar => p_bar, c_n4 => c_n4, ovr => ovr); u5: out_mux port map(ad => ad, f => f, dest_ctl => dest_ctl, oe => oe, y => y); -- define f_0 and f3 outputs f_0 <= '0' when f = "0000" else 'Z'; f3 <= f(3); end am2901; Note that f_0 is an open collector output so it will need an external pull -up resistor. This enables several similar outputs from cascaded chips to be wired together without external gates. The VHDL source code for the Am2901 can be found in warp\examples\vhdlbook\ch6. Stuart Lawson Page 23 17/10/2001