Vinayak Pandey, Vice President Product & Technology Marke8ng. May, 2017

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1 Vinayak Pandey, Vice President Product & Technology Marke8ng May, 2017

2 Overview of JCET Group Founded in 1972 and listed on Shanghai Stock Exchange in 2003 Largest OSAT in China and 3 rd largest OSAT in the world Significant manufacturing scale with factories strategically located in China, Singapore and Korea Comprehensive product pornolio from discrete, wirebond and flip chip packages to advanced wafer level and System-in-Package (SiP) soluions Experienced R&D team driving innovaions in advanced technologies with the largest Intellectual Property (IP) pornolio in the OSAT industry 2

3 JCET Group Event Timeline Restructured to Jiangyin transistor factory established 1994 JV with Phillips IPO on Shanghai Stock Exchange Established C3 & C5 Jiangyin established C6 SiP C8 Suqian established MIS C9 Chuzhou established JV with SMIC B2 Jiangyin established JCET-SC acquires STATS ChipPAC New factory in S. Korea Started as division of Hyundai ST Assembly Test Services established STATS IPO On SGX & Nasdaq Independent from Hyundai STATS merges with ChipPAC R&D Center in Singapore SCC expansion in China SCS expansion in Singapore SCK expansion in S. Korea SCC moves to JSCC in Jiangyin JCET Group is a Ier 1 OSAT service provider with comprehensive packaging assembly and test products and services 3

4 Product and Service Offerings Advanced Packages Full Turnkey Solu/ons Flip Chip Design & Simula/on Wafer Level (Fan-in, Fan-out, IPD, TSV) System-inPackage EEPROM RF BB Assembly Wirebond Packages Discrete Leaded Laminate Test 4 STATS ChipPAC Confiden/al

5 Global Footprint in Strategic Semiconductor Hubs Morges, Switzerland Suqian, China Incheon, S. Korea Fremont, CA Chuzhou, China JCET Group Corporate Headquarters Jiangyin, China San Diego, CA Tempe, AZ Singapore Manufacturing / Test FaciliIes R&D Centers Sales Presence 5 Zoom in on China factory loca8ons

6 Strongest IP Por`olio in OSAT Industry Patents Issued by the US Patent & Trademark Office As of 1Q 2017 Patents Issued by the State Intellectual Property Office of China As of 1Q 2017 Source : Based on Patent InformaIon Published in USPTO Website and State Intellectual Property Office of China Leading the OSAT industry with highest number of issued patents Over 68% of US patents are related to advanced wafer level and flip chip technology 6

7 Drivers for FOWLP / ewlb Elimina/on of chip-to-package interconnect delivers 4 key advantages Reduc/on in package size & thickness X/Y & Z Enhanced Reliability Fewer interfaces Integra/on Capability Heterogeneous die, passives, etc. Performance Improvement Bemer RLC and thermal Innova/ve Integra/on Pla`orm 3D ewlb 7

8 Fan-out Wafer Level Technology (ewlb) Fan-out wafer level packaging (FOWLP or ewlb) provides significant performance, size and cost benefits compared to other packaging technology available today Higher performance & higher bandwidths in a smaller package Super thin packaging soluions in single and muli-die configuraions Ultra fine ball pitch (down to 0.3mm) and a dramaically higher I/O count Interconnect independent of die size Strong thermal and electrical performance for a reliable, power-efficient soluion Versa/le integra/on pla`orm for 2.5D & 3D solu/ons Flexibility to integrate die from diverse semiconductor processes and different silicon wafer nodes More cost effecive approach to silicon pariioning approach than TSVs Line-width/line-space (LW/LS) raios of less than 5um/5um Ability to embed muliple acive and passive components in a wafer level Package-on-Package (PoP) or System-in-Package (SiP) soluion Cost effec/ve HVM process Ability to scale devices to larger manufacturing panel sizes for a lower cost per unit KGD reconsituted into a high density manufacturing format significantly increases yields and reduces cost Seamless transiion between Fan-in and Fan-out wafer level manufacturing 8

9 System-in-Package Technology Key technology building blocks for greater system performance, increased func/onal integra/on and lower power consump/on in a smaller form factor and lower cost Miniaturiza/on 70% size reduc/on Performance & Reliability EEPROM RF BB Cost Effec/ve HVM Process Heterogeneous integraion of muliple ICs in a modularized sub-system Advanced design rules achieve 20~30% Ighter keep-out-zone (KOZ) Thin film wafer level technology eliminates substrates & reduces package size Si pariioning of die and reintegraion for maximum space efficiency Increased design flexibility and integraion opions including die-to-die, die-topassives, and passives-to-passives placement Integrated Passive Devices (IPD) reduce the number of discrete passives Fine lines/spaces (L/S) rouing for high-speed I/O interconnecion Flip chip + wirebond hybrid stacking for increased system level integraion IntegraIon of acives & passives in the same system improves power delivery Advanced SMT process with high accuracy component placement Advanced mold tech for complex topography SiP applicaions Bemer electromagneic interference (EMI) isolaion and cross-talk control High efficiency conformal EMI shielding method with high yield One stop turnkey soluion wafer to fully tested SiP modules Lower total product cost due to avoidance of costly SoC integraion Delivers plug-and-play soluions faster than SoC designs High UPH SMT line & fully automated loading/unloading/avi EMI process Fast response Imes and highest quality reports, ES builds, and TAT Financial commitment to SiP business proliferaion 9

10 Innova&ve Integra&on Solu&ons Laminate ewlb Both Laminate on FOWLP Package on Package SiP on SiP FOWLP on Laminate 10

11 Thank You