2002 Seth Copen Goldstein 1

Transcription

1 58%/Yr compound Complexity growth rate 2%/Yr compound Productivity growth rate $ 5K/Staff Yr. (in 997 Dollars) Source: MATECH NanoComputing Architectures Seth Copen Goldstein Carnegie Mellon University CMU October 7, 22 Outline Manufacturing Paradigm Shift Dealing with the atomic scale Research Directions Defect/Fault Tolerance An Example architecture Abstractions Devices Circuits Architectures Summary NanoComputing, NSF /2 22 Seth Copen Goldstein NanoComputing, NSF /2 22 Seth Copen Goldstein 2.E+.E+.E+9.E+6.E+3.E+ What Comes Next? Ops/sec/$ doubles every. years Tubes/ CMOS Transistor Mechanical/ Relays nanometer doubles every doubles every 7.5 years 2.3 years.e-3 Combination of Hans Moravac + Larry Roberts + Gordon Bell WordSize*ops/s/sysprice.E From Gray Turing Award Lecture NanoComputing, NSF /2 22 Seth Copen Goldstein 3 Technology Shifts Size of Devices Inches to Microns to Nanometers Type of Interconnect Rods to Lithowires to Nanowires Method of Fabrication Hammers to Light to Self-Assembly Largest Sustainable System to 8 to 2 Reliability Bad to Excellent to Unknown NanoComputing, NSF /2 22 Seth Copen Goldstein 4 On the cusp of Major Technology Change Devices will be very small & numerous Scale is new: x smaller, x more Feature size (Nanometers) uprocessor x smaller Nano Tech Devices/design x more NanoComputing, NSF /2 22 Seth Copen Goldstein 5 Mask Cost / Wafer Level Exposure ($) Power Density (W/cm2) Independent of Shift? Affordable Total Cost / Wafer Level Exposure Wafer Exposures/Mask um.25 um.8 um.3 um SIA Roadmap Generation Manufacturing Cost 886 Hot Plate 88 P Pentium Source: Irwin & Borkar, De Intel NanoComputing, NSF /2 22 Seth Copen Goldstein 6 Logic Transistors/Chip (M)... Manufacturing Cost Design Cost Power Density Efficiency Year Feature Logic 3 Yr. Design Staff Size (nm) trans/chip (M) Staff Size Costs $9 M $2 M $6 M $36 M Design Cost SPECint95 Sun s Surface.9.8 y = -5E-5x Rocket.7 Nuclear Nozzle Verification Complexity.6 Reactor.5 Testing Cost Power Density SPEC ratio/mhz Clock Speed (MHz) Efficiency Productivity (K) Trans./Staff-Mo. 22 Seth Copen Goldstein

2 The Atomic Scale Very small devices/wires Increased variability Increased single-event upsets New behaviors/mechanisms No predetermined arbitrary patterns Increased defect densities Lots of devices/wires Scalable.* required CMOS Too Precision is expensive Current Abstractions have a major impact on cost Requires process engineers to deliver robust devices Requires perfect devices CMOS is becoming just another nanoscale component Process rules and mask costs are already eliminating arbitrary patterns NanoComputing, NSF /2 22 Seth Copen Goldstein 7 NanoComputing, NSF /2 22 Seth Copen Goldstein 8 Computing Crystals Computing Crystals A reasonable medium-term position No end-to-end connections Maybe multi-terminal devices No complex predetermined patterns Quasi-regular & non-deterministic Hierarchical assembly Assembly Computing Crystals Control, configuration decompression, & defect mapping seed A reasonable medium-term position No end-to-end connections Maybe multi-terminal devices No complex predetermined patterns Quasi-regular & non-deterministic Hierarchical assembly With defects Assembly Computing Crystals Control, configuration decompression, & defect mapping seed NanoComputing, NSF /2 22 Seth Copen Goldstein 9 NanoComputing, NSF /2 22 Seth Copen Goldstein How to Make Forward Progress Abstraction Layers New Abstractions Defect/fault tolerance Devices Circuits Architectures Close the loop between designers and device engineers Applications Algorithms Programming Languages Intermediate Representations ISA Microarchitecture Tools Fabrication Circuits Devices NanoComputing, NSF /2 22 Seth Copen Goldstein NanoComputing, NSF /2 22 Seth Copen Goldstein 2 22 Seth Copen Goldstein 2

3 Defect/Fault Tolerance Vast body of knowledge, but nanocomputing is different: Massive integration and diverse function High density of defects and faults Constrained fabrication Nanoscale engineering requires that we build systems that work from devices that don t this is fundamental due to atomic scale Fault and Defect tolerance is key to reducing cost and supporting novel devices Hierarchical Solution Must attack this at every level Device engineering Fabrication 2 Circuits 3 Testing methods 6 Architectures 8 Algorithms infinite? Use redundancy and computation to compensate for lack of robustness and precision NanoComputing, NSF /2 22 Seth Copen Goldstein 3 NanoComputing, NSF /2 22 Seth Copen Goldstein 4 Island-Style FPGA Interconnection network Universal gates and/or storage elements Dealing With Defects Need to discover the characteristics of the individual components, but Can t selectively stimulate or probe the components Download test machines Programmable Switches HOST Thin link NanoComputing, NSF /2 22 Seth Copen Goldstein 5 NanoComputing, NSF /2 22 Seth Copen Goldstein 6 Built-In Self-Test Defect Tolerant Architecture Configure testers vertically Configure testers horizontally Configure the device to test itself! Identify fault! Extra devices, wires, and post-processing to route around defective elements Multi-layered approach required Radical architectures to exploit Randomness Reconfigurability Plentiful resources New testing approaches CalTech NanoComputing, NSF /2 22 Seth Copen Goldstein 7 NanoComputing, NSF /2 22 Seth Copen Goldstein 8 22 Seth Copen Goldstein 3

4 Reconfigurable Computing Advantages of Reconfigurable General-Purpose int reverse(int x) { int k,r=; for (k=; k<64; k++) r = x&; x = x >> ; r = r << ; } } int func(int* a,int *b) { int j,sum=; for (j=; *a>; j++) sum+=reverse(*b Compiler Custom Hardware General-Purpose Custom Hardware Flexibility of a processor Performance of custom hardware Defect Tolerant Logic Blocks Routing Resources (Molecular give back area-delay lost in CMOS) NanoComputing, NSF /2 22 Seth Copen Goldstein 9 NanoComputing, NSF /2 22 Seth Copen Goldstein 2 Heart of an FPGA Heart of an FPGA a a data a a Universal gate = RAM a & a2 a a data a The cost of the a a & a2fpga: Increased Area-Delay Product RAM cell Universal gate = RAM Wires to program RAM cell data in control data in control Switch controlled by a -bit RAM cell Switch controlled by a -bit RAM cell NanoComputing, NSF /2 22 Seth Copen Goldstein 2 NanoComputing, NSF /2 22 Seth Copen Goldstein 22 Key Component: Reconfigurable Switch Abstraction Layers Still OK? Reconfigurable Molecular Switch Holds its own configuration state Can be programmed with the signal wires Applications Algorithms Programming Languages Intermediate Representations ISA Microarchitecture Circuits Fabrication Devices Probably Not Tools NanoComputing, NSF /2 22 Seth Copen Goldstein 23 NanoComputing, NSF /2 22 Seth Copen Goldstein Seth Copen Goldstein 4

5 Transistor Abstractions Transistor Abstractions input output input output Output Output Input Input Old model: One device: restores, isolates, All turn on at same point All use same power NanoComputing, NSF /2 22 Seth Copen Goldstein 25 Current model: Many different kinds of Ts: ram, logic different turn-ons, power usage, speed NanoComputing, NSF /2 22 Seth Copen Goldstein 26 Transistor Abstractions SIRM Example input output Output A B B A&B Nano-switch A B New Way Nano-restorer A&B Nano-isolator Input New model: SirM Some devices are switches Some devices are isolators Some devices are restorers A Old Way Breaks up transistor abstraction into its components Allows creation of library of composable components Increases freedom of design NanoComputing, NSF /2 22 Seth Copen Goldstein 27 NanoComputing, NSF /2 22 Seth Copen Goldstein 28 Fabrication New Layer Applications Algorithms Programming Languages Intermediate Representations ISA Microarchitecture nanocircuits Devices Progress can be made NOW! Tools NanoComputing, NSF /2 22 Seth Copen Goldstein 29 Circuit Abstractions Multivalued logic? Compute with and Analog? Logical operations, AND, OR, etc. Connect up devices as needed, Look-up tables? Point-to-pointMeshes? Switch-blocks Synchronize as necessary Combinational logic registersasynchronous? Forced to latch? Unlimited fan-out wires are perfect (maybe RC) What is a wire? NanoComputing, NSF /2 22 Seth Copen Goldstein 3 22 Seth Copen Goldstein 5

6 NanoBlock Abstract +Vdd C Φ Ground Configurable diode at each intersection Latches for Isolation and NanoComputing, NSF /2 22 Seth Copen Goldstein 3 Gain NanoComputing, NSF /2 22 Seth Copen Goldstein 32 C Φ Gnd Nearest Neighbor Routing Nearest Neighbor Routing NW NW NanoComputing, NSF /2 22 Seth Copen Goldstein 33 NanoComputing, NSF /2 22 Seth Copen Goldstein 34 Nearest Neighbor Routing 2-D Mesh Switch block NW NW NanoComputing, NSF /2 22 Seth Copen Goldstein 35 NanoComputing, NSF /2 22 Seth Copen Goldstein Seth Copen Goldstein 6

7 2-D Mesh 2-D Mesh NanoComputing, NSF /2 22 Seth Copen Goldstein 37 NanoComputing, NSF /2 22 Seth Copen Goldstein 38 The NanoFabric NanoFabric Attributes Nanoscale layer put deterministically on top of CMOS Highly regular Control, configuration decompression, & defect mapping seed ~ 8 long lines ~ 6 clusters Cluster has 28 blocks Hierarchical fabrication. Manufacture devices 2. Non-deterministically align wires 3. Self-assemble monolayers onto wires 4. Create meshes 5. Deterministically align w/cmos Reconfigurable Defect tolerant How do we use it? NanoComputing, NSF /2 22 Seth Copen Goldstein 39 NanoComputing, NSF /2 22 Seth Copen Goldstein 4 ISA has to go? Current ISA hides to much Good for forward compatibility human oriented assembly ad hock additions Bad for removing constraints exploiting compiler verification What can replace ISA? Breaking (And Adding) Abstractions Applications Algorithms Programming Languages Intermediate Representations nanocores ISA Microarchitecture Tools Circuits FPGA nanocircuits Fabrication Devices NanoComputing, NSF /2 22 Seth Copen Goldstein 4 NanoComputing, NSF /2 22 Seth Copen Goldstein Seth Copen Goldstein 7

8 Spanning -orders of Magnitude Program Compilers Phoenix Theory Architecture Billion Gates. Program Circuits From Compilers 2. Split-phase Abstract Machines 3. Configurations placed independently 4. Placement on chip int reverse(int x) { int k,r=; for (k=; k<64; k++) r = x&; x = x >> ; r = r << ; } } Certifying Circuits! Computations & local storage Unknown latency ops. NanoComputing, NSF /2 22 Seth Copen Goldstein 43 NanoComputing, NSF /2 22 Seth Copen Goldstein 44 Direct Mapping: App s Gates Likely to be difficult because tool must Build in error recovery Synthesize, place, and route 2 devices Virtualize communication resources Allow movement of computation away from failing components (redo p&r) Compiler doesn t see everything separately compiled applications Operating System interactions NanoComputing, NSF /2 22 Seth Copen Goldstein 45 New Abstraction Layer: Nano-Core Provides parameterized abstractions for datapaths Fetch memory PC i control PC j communication Compiler/OS target Nano-Core Can build any computing device on the fly Abstractions hide defects and faults at cost of additional area, power, delay This allows forward progress now Can pierce this layer over time NanoComputing, NSF /2 22 Seth Copen Goldstein 46 Conclusions Investment in nanodevices and materials is bearing fruit A new manufacturing approach is necessary to fabricate large-scale circuits (> 2 devices/cm 2 ) from nano-scale components. Derivatives of self-assembly have the best chance to succeed. All known approaches result in statistically imperfect macroscale circuit structures. Dealing with imperfections, defects, and outright faults is a new requirement Hardware and software approaches Redundancy and computation compensate for defects/faults Abstraction is the solution Enables simultaneous progress at all levels Dependent only on size and scale Conclusions - 2 Abstractions need to be: tool friendly not human friendly Focus moves from ISA IR Von Neumann Parallel fine-grained fabric Harness reconfigurable computing! NanoComputing, NSF /2 22 Seth Copen Goldstein 47 NanoComputing, NSF /2 22 Seth Copen Goldstein Seth Copen Goldstein 8

9 Conventional Processors No Longer Scale Performance by 5% each year Future potential of novel architecture is large ( vs 3) e+7 e+6 e+5 e+4 e+3 e+2 e+ 52%/year ps/gate 9% Gates/clock 9% Clocks/inst 8% Perf (ps/inst) 9%/year e Bill Dally e+7 e+6 e+5 e+4 Perf (ps/inst) Delay/CPUs e+3 e+2 3: e+ e+,: e- 3,: e-2 e-3 e Bill Dally 52%/year 74%/year 9%/year NanoComputing, NSF /2 22 Seth Copen Goldstein 49 NanoComputing, NSF /2 22 Seth Copen Goldstein 5 22 Seth Copen Goldstein 9