Načrtovanje integriranih vezij in digitalnih elektronskih sistemov
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1 Laboratorij za načrtovanje integriranih vezij Univerza v Ljubljani Fakulteta za elektrotehniko Andrej Trost priprava na laboratorijske vaje 2011 Načrtovanje integriranih vezij in digitalnih elektronskih sistemov Literatura: A. Trost: Načrtovanje digitalnih vezij v jeziku VHDL, FE
2 Digitalni elektronski sistemi Za sisteme je značilna kompleksnost vezja komponente so lahko zelo velika vezja (npr. RAM), vendar imajo enostavno strukturo Sistem lahko vsebuje analogne komp., vendar je večina sistema digitalno vezje najbolj kompleksne funkcije lahko naredimo le z digitalnim vezjem System-on-Chip procesor (CPU) Pomnilnik (RAM, flash) Komunikacijski vmesnik Namenska vezja (IP) RAM IP vmesniki CPU 2
3 Primer sistema: prenosni CD mp3 audio izhod analog. del audio dekoder (CPU) pomnilnik Reed-Solomon korekcija napak mehanizem analog. del servo krmilnik (DSP) zunanji pomnilnik 3
4 Vrste digitalnih integriranih vezij univerzalna vezja vezja za določeno aplikacijo mikroprocesor Application Specific Integrated Circuit enostaven za krmiljenje in nadzor konstantna poraba celic dobra izkoriščenost logike SLABOSTI zaporedno izvajanje ukazov kompleksni programi manjša zmogljivost rabi več pomnilnika počasen odziv na simultane spremembe višja delovna frekvenca paralelno izvajanje operacij hiter odziv na simultane spremembe vhodov SLABOSTI zahtevnejši za načrtovanje kompleksni vezja (avtomati) porabijo veliko celic 4
5 Programirljiva vezja (Programmable) integrirana vezja, ki so vnaprej izdelana ne načrtujemo na fizičnem nivoju krajši čas razvoja nimamo stroškov priprave proizvodnje (miljoni $) omogočajo vedno večjo hitrost obdelave podatkov (TK) v primerjavi z ASIC so počasnejša, imajo večjo površino in porabo aktivni elementi v povezovalni mreži vnašajo zakasnitve del vezja je namenjen programiranju gradniki vezja niso nikoli 100% izkoriščeni 5
6 Programirljiva vezja: CPLD, FPGA Complex Programmable Logic Device Makro-celice s FF in povezovalno polje log. vrat, FF FLASH tehnologija, 1.8V Field Programmable Gate Array Matrika log. celic in povezovalno polje vrat, 100k RAM CMOS tehnologija, 1.2V polje povezav makro-celice FF FF 6
7 7
8 Uporaba programirljivih vezij CPLD enostavni vmesniki povezovalna logika pretvorniki log. nivojev hitri števci in avtomati senzorski vmesniki FPGA obdelava signalov sita, kodirniki, generatorji, video zajem (500LUT, 1.5k kode) zahtevni vmesniki PCI, USB, Ethernet MAC (7.5k), DDR, ATM sistemi na integriranem vezju Tekmovanja na FE digitalni osciloskop, DMX konzola, GPS, VGA video igrice, MIDI vmesniki, mikroprocesorji, audio spektralni analizator 8
9 Vezja FPGA proizvajalca Xilinx Virtex-II Virtex-II pro Virtex-4 Virtex-5 Virtex-6 Virtex-7 Spartan-3 Spartan-6 Artix-7 Spartan-3 XC3S50 XC3S200 XC3S5000 matrika CLB 16 x x x 80 flip-flopov BRAM 4 (9kB) 12 (27kB) 104 (234kB) vh-izh cena $12 $15 $160 Vezje Hitrost Zasedenost MAC 16-bit 150 MHz 4% FIR 64-tap 8 MSPS 12% Picoblaze 8-bit 88 MHz 5% 9
10 Način opisovanja digitalnih vezij 10 specifikacija postopkovni (behavioral) funkcijski (dataflow, RTL) logični nivo transistorjev geometrija vezja (layout) Standardizirani jeziki (IEEE) VHDL Verilog, System Verilog SystemC programirljiva vezja VISOKONIVOJSKI JEZIKI SHEMATSKI OPIS SystemC C VHDL Verilog
11 VHDL ni programski jezik! stavki za opis vezja se izvajajo paralelno vrstni red stavkov ni pomemben! vezje(arhitektura) prireditveni stavki VHDL Very high-speed IC Hardware Description Language q <= n; p1: proces p2: proces komponenta komponenta komponenta p1: process(clk) begin if rising_edge(clk) then n <= n + 1; end if; end process; 11
12 Funkcijski opis vezja v jeziku VHDL stavki opisujejo gradnike vezja vrstni red stavkov ni pomemben (sočasni stavki) entity adder is port ( a, b : in std_logic; carry : in std_logic; sum : out std_logic); end adder; architecture logic of adder is signal c : std_logic; begin sum <= c xor carry; c <= a xor b; end one; a b carry adder(logic) c deklaracija notranjega signala sum 12
13 Postopkovni opis vezja v jeziku VHDL v procesu opišemo delovanje vezja zgradbo vezja določi program za sintezo vezij vrstni red stavkov je pomemben (sekvenčni stavki) arhitektura p1: process ventil <= 0 ; if pretok > 10 then ventil <= 1 ; end if; if alarm = 1 then ventil <= 0 ; end if; pretok alarm p1: 10 > ventil end process; 13
14 Zgradba vezja Primer: vsota z absolutno vrednostjo c = a+ b Kaj vsebuje vezje? seštevalnik, odštevalnik, izbiralnik zasedenost CPLD 8% (21 celic) 14
15 Sinteza vključuje optimizacijo VHDL stavek: c <= a+b when b>0 else a-b; zasedenost 7% (19 celic) Drug zapis: c <= a+bwhen b>=0 else a-b; zasedenost 6% (17 celic) 15
16 Preverjanje delovanja načrtanega vezja Simulacija na osebnem računalniku funkcionalna in časovna simulacija ASIC100% simulacijo > cena napake! Programirljiva vezja vsaj funkcionalna simulacija blokov problem je simulacijski čas emulacija vezja problem je vidnost signalov, čas priprave in možnost priprave kompleksnih testov Mikroprocesorji debagiranje v sistemu ali emulatorju R. Wilson, Verifying FPGA designs, EDN, feb
17 Razvojna orodja in programiranje Proizvajalci Xilinx, Altera, Lattice ponujajo zastonj osnovni paket razvojnih orodij Xilinx ISE WebPACK 12.3 ( 10GB) Nalaganje vezij poteka preko vmesnika JTAG Parallel Cable III, USB Programmer ali namensko vezje FPGA vezja z SRAM konfig. imajo običajno zunanji Flash PROM TDO TMS TCK TDI FPGA CPLD PROM 17
18 Koraki prevajanja vezja 1. Sinteza logičnega vezja (Synthesize) 2. Tehnološka preslikava (Implement Design) vključimo vse datoteke (opis vezja, jedra, knjižnice) predhodno določimo še lokacije priključkov (User Constraints) 3. Izdelava konfiguracijskih datotek (Generate Programming File) 18
19 Razvojni sistemi razvojni sistem za lab. vaje in projekte XC2C256, TQ144, -7 Digilent CPLD CoolRunner II Digilent Spartan-3E Board pri nas razviti FPGA razvojni moduli XC3S200 ali XC3S400, TQ144 LNIV Spartan-3 Razvojni modul 19
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