ΔΙΑΛΕΞΗ 2: FPGA Architectures

Transcription

1 ΗΜΥ 664 ΨΗΦΙΑΚΟΣ ΣΧΕΔΙΑΣΜΟΣ ΜΕ FPGAs Χειμερινό Εξάμηνο 2010 ΔΙΑΛΕΞΗ 2: FPGA Architectures ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ Λέκτορας ΗΜΜΥ Some slides adopted from Digital Integrated Circuits, Rabbey et. al.

2 Schedule Today: FPGA Architectures This week: Complementary lecture on lab procedures Next Week: FPGA Design Flow Steps Sept. 28 th Class is cancelled (will be travelling) ΗΜΥ664 Δ02 FPGA Architectures.2 Θεοχαρίδης, ΗΜΥ, 2010

3 Executives might make the final decisions about what would be produced, but engineers would provide most of the ideas for new products. After all, engineers were the people who really knew the state of the art and who were therefore best equipped to prophesy changes in it. The Soul of a New Machine, Kidder, pg 35 Scientists dream about doing great things. Engineers do them. ΗΜΥ664 Δ02 FPGA Architectures.3 Θεοχαρίδης, ΗΜΥ, 2010

4 Digital Logic Digital Logic Function Product AND (&) Sum OR ( ) 3 Inputs Black Box Truth Table (Look Up Table LUT) SUM of PRODUCTS The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

5 Digital Logic Digital Logic Function Product AND (&) Sum OR ( ) 3 Inputs Black Box Truth Table (Look Up Table LUT) SUM of PRODUCTS The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

6 Digital Logic Digital Logic Function Product AND (&) Sum OR ( ) 3 Inputs Black Box Truth Table (Look Up Table LUT) SUM of PRODUCTS The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

7 Programmable Logic Devices PLDs Inputs SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC ANDs Outputs ORs Logic Functions Un-programmed State Planes of ANDs, ORs The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

8 Programmable Logic Devices PLDs Inputs SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC ANDs Outputs ORs Logic Functions Un-programmed State Planes of ANDs, ORs The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

9 Programmable Logic Devices PLDs Inputs SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC ANDs Outputs ORs Logic Functions Un-programmed State Planes of ANDs, ORs The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

10 Programmable Logic Devices PLDs Inputs SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC ANDs Outputs ORs Logic Functions Un-programmed State Planes of ANDs, ORs Sums Product Terms Programmed PLD The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

11 Programmable Logic Devices PLDs Logic Functions Programmed PLD Sums Product Terms The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

12 Programmable Logic Devices PLDs Logic Functions x x x Programmed PLD x x Sums Product Terms The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

13 Programmable Logic Devices PLDs Logic Functions GLUE LOGIC x x x x Programmed PLD x x x Sums Product Terms The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

14 Complex PLDs CPLDs Programmable PLD Blocks Programmable Interconnects Electrically Erasable links Feedback Outputs CPLD Architecture The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

15 Gate Array ΗΜΥ664 Δ02 FPGA Architectures.15 Θεοχαρίδης, ΗΜΥ, 2010

16 Gate Array vs. Standard-Cell ASIC AND gates ΗΜΥ664 Δ02 FPGA Architectures.16 Θεοχαρίδης, ΗΜΥ, 2010

17 Programmable Logic - History PROM first programmable logic Address lines serve as logic inputs and data lines as logic output Logic functions are inefficient as logic functions rarely use all product terms D0 D2 Source: ΗΜΥ664 Δ02 FPGA Architectures.17 Θεοχαρίδης, ΗΜΥ, 2010

18 PLA Programmable Logic Arrays Programmable wired AND followed by programmable wired OR Inputs to AND plane can be normal or complementary input generates product terms OR sum of products Consider Implementing F=A B C +A BC +AB C +AB C+ ABC PLA problems Two levels of programmability leads to Poor performance Difficult to manufacture ΗΜΥ664 Δ02 FPGA Architectures.18 Θεοχαρίδης, ΗΜΥ, 2010

19 Programmable Array Logic (PALs) Programmable wired AND plane and fixed wired OR plane Source: Brown and Rose, IEEE Design and Test, 1996 ΗΜΥ664 Δ02 FPGA Architectures.19 Θεοχαρίδης, ΗΜΥ, 2010

20 Simple Programmable Logic Devices (SPLDs) PLAs and PALS Programmable logic plane structure size increases rapidly with increase in number of inputs Complex PLDs Programmably interconect multiple SPLDs Altera MAX series pioneered such devices FPGAs ΗΜΥ664 Δ02 FPGA Architectures.20 Θεοχαρίδης, ΗΜΥ, 2010

21 Field Programmable Gate Arrays FPGA Field Programmable Gate Array Simple Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for memory chips (Moore s Law) The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

22 Field Programmable Gate Arrays FPGA Field Programmable Gate Array Simple Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for SRAM memory chips (Moore s Law) Huge Density of Logic Block Islands 1, ,000 s in a Sea of Interconnects FPGA Architecture The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

23 Field Programmable Gate Arrays FPGA The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

24 FPGA vs ASIC Source: Xilinx ΗΜΥ664 Δ02 FPGA Architectures.24 Θεοχαρίδης, ΗΜΥ, 2010

25 Time to Market Pressure ΗΜΥ664 Δ02 FPGA Architectures.25 Θεοχαρίδης, ΗΜΥ, 2010

26 As a side note: NRE and unit cost metrics Costs: Unit cost: the monetary cost of manufacturing each copy of the system, excluding NRE cost NRE cost (Non-Recurring Engineering cost): The one-time monetary cost of designing the system total cost = NRE cost + unit cost * # of units per-product cost = total cost / # of units = (NRE cost / # of units) + unit cost Example NRE=$2000, unit=$100 For 10 units total cost = $ *$100 = $3000 per-product cost = $2000/10 + $100 = $300 Amortizing NRE cost over the units results in an additional $200 per unit ΗΜΥ664 Δ02 FPGA Architectures.26 Θεοχαρίδης, ΗΜΥ, 2010

27 Re-Spinning Currently, roughly 30% of designs are re-spun. Using this number and assuming another $25,000 NRE charge, the probable cost of a re-spin is: Re-spin cost = [(17 weeks*$3000 engineering per week)+nre]*re-spin potential ASIC total cost = 25,000+79, (X units*13). Additional 17 weeks delay in time to market.. ΗΜΥ664 Δ02 FPGA Architectures.27 Θεοχαρίδης, ΗΜΥ, 2010

28 Reasons for Respin Found On First Spin ICs/ASICs: - Functional Logic Error ###################### 43% - Analog Tuning Issue ########## 20% - Signal Integrity Issue ######### 17% - Clock Scheme Error ####### 14% - Reliability Issue ###### 12% - Mixed Signal Problem ##### 11% - Uses Too Much Power ##### 11% - Has Path(s) Too Slow ##### 10% - Has Path(s) Too Fast ##### 10% - IR Drop Issues #### 7% - Firmware Error ## 4% - Other Problem # 3% - Overall 61% of New ICs/ASICs Require At Least One Re-Spin Source: Aart de Geus, Chairman & CEO of Synopsys ΗΜΥ664 Δ02 FPGA Architectures.28 Θεοχαρίδης, ΗΜΥ, 2010

29 More Designs Embracing FPGAs Source: Gartner Group ΗΜΥ664 Δ02 FPGA Architectures.29 Θεοχαρίδης, ΗΜΥ, 2010

30 FPGA Evolution Source: Xilinx ΗΜΥ664 Δ02 FPGA Architectures.30 Θεοχαρίδης, ΗΜΥ, 2010

31 FPGA technology vs ASIC ΗΜΥ664 Δ02 FPGA Architectures.31 Θεοχαρίδης, ΗΜΥ, 2010

32 Current FPGA Architectures ΗΜΥ664 Δ02 FPGA Architectures.32 Θεοχαρίδης, ΗΜΥ, 2010

33 FPGA Application Domains Started as Prototyping platforms Hardware Accelerators Reconfigurable multi-function systems Specialized Applications Aerospace and space - Mars Rover Military Applications Missiles Signal Processing Embedded Systems ΗΜΥ664 Δ02 FPGA Architectures.33 Θεοχαρίδης, ΗΜΥ, 2010

34 Programmable Logic Programmable digital integrated circuit Standard off-the-shelf parts Desired functionality is implemented by configuring on-chip logic blocks and interconnections Advantages (compared to an ASIC): Low development costs Short development cycle Device can (usually) be reprogrammed Types of programmable logic: Complex PLDs (CPLD) Field programmable Gate Arrays (FPGA) CPLD/FPGA Architectures L2-34

35 CPLDs Architecture and Examples CPLD/FPGA Architectures L2-35

36 CPLD/FPGA Architectures L2-36 PLD - Sum of Products A B C C B A C B A f + = 1 C B A B A f + = 2 AND plane Programmable AND array followed by fixed fan-in OR gates Programmable switch or fuse

37 PLD - Macrocell Can implement combinational or sequential logic Select A B C Enable f 1 Flip-flop D Q MUX Clock AND plane CPLD/FPGA Architectures L2-37

38 CPLD Structure Integration of several PLD blocks with a programmable interconnect on a single chip I/O Block PLD Block PLD Block I/O Block Interconnection Matrix I/O Block PLD Block PLD Block I/O Block CPLD/FPGA Architectures L2-38

39 CPLD Example - Altera MAX7000 CPLD/FPGA Architectures L2-39 EPM7000 Series Block Diagram

40 CPLD Example - Altera MAX7000 EPM7000 Series Device Macrocell CPLD/FPGA Architectures L2-40

41 FPGAs Architectures and Elements CPLD/FPGA Architectures L2-41

42 FPGA - Generic Structure FPGA building blocks: Programmable logic blocks Implement combinatorial and sequential logic Programmable interconnect Wires to connect inputs and outputs to logic blocks Programmable I/O blocks Special logic blocks at the periphery of device for external connections I/O Logic block Interconnection switches I/O I/O I/O CPLD/FPGA Architectures L2-42

43 Logic Blocks Logic Functions implemented in Look Up Table LUTs. Flip-Flops. Registers. Clocked Storage elements. Multiplexers (select 1 of N inputs) 16-bit SR 16x1 RAM a b c d 4-input LUT mux flip-flop y e q clock clock enable set/reset FPGA Fabric Logic Block The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

44 Look Up Tables LUTs LUT contains Memory Cells to implement small logic functions Each cell holds 0 or 1. Programmed with outputs of Truth Table Inputs select content of one of the cells as output 3 Inputs LUT -> 8 Memory Cells 16-bit SR 16x1 RAM 3 6 Inputs a b c d 4-input LUT mux flip-flop y e q clock clock enable set/reset SRAM SRAM Multiplexer MUX Static Random Access Memory SRAM cells The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

45 Look Up Tables LUTs LUT contains Memory Cells to implement small logic functions Each cell holds 0 or 1. Programmed with outputs of Truth Table Inputs select content of one of the cells as output Configured by re-programmable SRAM memory cells 3 Inputs LUT -> 8 Memory Cells 16-bit SR 16x1 RAM 3 6 Inputs a b c d 4-input LUT mux flip-flop y e q clock clock enable set/reset SRAM SRAM Multiplexer MUX Static Random Access Memory SRAM cells The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

46 Logic Blocks Larger Logic Functions built up by connecting many Logic Blocks together The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

47 Logic Blocks Larger Logic Functions built up by connecting many Logic Blocks together Determined by SRAM cells SRAM SRAM cells The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

48 Clocked Logic Registers on outputs. CLOCKED storage elements. Synchronous FPGA Logic Design, Pipelined Logic. FPGA Fabric Pulse from Global Clock (e.g. LHC BX frequency) 16-bit SR 16x1 RAM a b c d 4-input LUT mux flip-flop y e q clock clock enable set/reset FPGA Fabric Special Routing for Clocks Clock from Outside world (eg LHC bunch frequency) The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

49 Other FPGA Building Blocks Clock distribution Embedded memory blocks Special purpose blocks: DSP blocks: Hardware multipliers, adders and registers Embedded microprocessors/microcontrollers High-speed serial transceivers CPLD/FPGA Architectures L2-49

50 FPGA Basic Logic Element LUT to implement combinatorial logic Register for sequential circuits Additional logic (not shown): Carry logic for arithmetic functions Expansion logic for functions requiring more than 4 inputs Select Out A B C LUT D Q D Clock CPLD/FPGA Architectures L2-50

51 Look-Up Tables (LUT) Look-up table with N-inputs can be used to implement any combinatorial function of N inputs LUT is programmed with the truth-table A B C D Z Truth-table A B C D A B C LUT LUT implementation D Gate implementation Z Z CPLD/FPGA Architectures L2-51

52 LUT Implementation Example: 3-input LUT Based on multiplexers (pass transistors) LUT entries stored in configuration memory cells X1 X2 0/1 0/1 0/1 0/1 0/1 0/1 F Configuration memory cells 0/1 0/1 X3 CPLD/FPGA Architectures L2-52

53 Programmable Interconnect Interconnect hierarchy (not shown) Fast local interconnect Horizontal and vertical lines of various lengths LE LE LE Switch Matrix Switch Matrix LE LE LE CPLD/FPGA Architectures L2-53

54 Switch Matrix Operation Before Programming After Programming 6 pass transistors per switch matrix interconnect point Pass transistors act as programmable switches Pass transistor gates are driven by configuration memory cells CPLD/FPGA Architectures L2-54

55 Special Features Clock management PLL,DLL Eliminate clock skew between external clock input and on-chip clock Low-skew global clock distribution network Support for various interface standards High-speed serial I/Os Embedded processor cores DSP blocks CPLD/FPGA Architectures L2-55

56 Configuration Storage Elements Static Random Access Memory (SRAM) each switch is a pass transistor controlled by the state of an SRAM bit FPGA needs to be configured at power-on Flash Erasable Programmable ROM (Flash) each switch is a floating-gate transistor that can be turned off by injecting charge onto its gate. FPGA itself holds the program reprogrammable, even in-circuit Fusible Links ( Antifuse ) Forms a forms a low resistance path when electrically programmed one-time programmable in special programming machine radiation tolerant CPLD/FPGA Architectures L2-56

57 Example: Altera Stratix Series CPLD/FPGA Architectures L2-57

58 Floorplan CPLD/FPGA Architectures L2-58

59 Logic Element CPLD/FPGA Architectures L2-59

60 Logic Array Block (LAB) LAB regroups 10 logic elements with a fast local interconnect Interconnect structure Direct link between LABs and adjacent blocks Row interconnects 4, 8, and 24 blocks left or right Column interconnects 4, 8, and 16 blocks up or down CPLD/FPGA Architectures L2-60

61 Embedded Memory Dual-Port RAM M x 1 M4K 4096 x 1 M-RAM 64K x 8 CPLD/FPGA Architectures L2-61

62 Example: Xilinx Virtex-II Pro CPLD/FPGA Architectures L2-62

63 Virtex II Pro Floorplan 622 Mbps to Gbps PowerPCs 1 to 4 PowerPCs 4 to 16 multi-gigabit transceivers 12 to 216 multipliers 3,000 to 50,000 logic cells 200k to 4M bits RAM 204 to 852 I/Os Up to 16 serial transceivers Logic cells CPLD/FPGA Architectures L2-63

64 Logic Slice Architecture Two 4-input LUT, can also be used as: 16-bit synchronous RAM 16-bit shift register Two flip-flops/latches Carry logic for arithmetic circuits (e.g. adder) Fast width expansion logic Implement logic functions with more than 4 inputs CPLD/FPGA Architectures L2-64

65 Configurable Logic Block (CLB) CLB regroups 4 logic slices Fast connection to neighbors Connections for carry logic and shift register mode CPLD/FPGA Architectures L2-65

66 Xilinx: Embedded Multipliers CPLD/FPGA Architectures L2-66

67 Altera: Embedded DSP Blocks Two DSP Block columns per device Number varies by height of column Can implement: Eight 9x9 multipliers Four 18x18 multipliers One 36x36 multiplier Contains adder/subtractor/accumulator Registered inputs can become shift register CPLD/FPGA Architectures L2-67

68 Altera: Embedded DSP Block CPLD/FPGA Architectures L2-68

69 Xilinx: Rocket I/O Gb/s per pair 78 MHz 78 MHz Virtex-II Pro Virtex-II Pro Virtex 4: 11.1 Gbps!!! CPLD/FPGA Architectures L2-69

70 FPGA Vendors & Device Families Xilinx Virtex-II/Virtex-4: Featurepacked high-performance SRAM-based FPGA Spartan 3: low-cost feature reduced version CoolRunner: CPLDs Altera Stratix/Stratix-II High-performance SRAMbased FPGAs Cyclone/Cyclone-II Low-cost feature reduced version for cost-critical applications MAX3000/7000 CPLDs MAX-II: Flash-based FPGA Actel Anti-fuse based FPGAs Radiation tolerant Flash-based FPGAs Lattice Flash-based FPGAs CPLDs (EEPROM) QuickLogic ViaLink-based FPGAs CPLD/FPGA Architectures L2-70

71 State of the Art in FPGAs >90 nm process on 300 mm wafers Virtex 6 on 40 nm Lower cost per function (LUT + register) Smaller and faster transistors: Higher speed System speed up to 500 MHz (and higher) Mainly through smart interconnects, clock management, dedicated circuits, flexible I/O. Integrated transceivers running at 10 Gigabits/sec More Logic and Better Features: >100,000 LUTs & flip-flops >200 embedded RAMs, and same number 18 x 18 multipliers 1156 pins (balls) with >800 GP I/O 50 I/O standards, incl. LVDS with internal termination 16 low-skew global clock lines Multiple clock management circuits On-chip microprocessor(s) and multi-gbps transceivers CPLD/FPGA Architectures L2-71

72 Latest Devices:Capacity & Features - Examples Xilinx Virtex-4 90nm process Up to 960 I/Os > logic cells Up to kb block RAMs (~10Mb RAM) 192 DSP slices (18x18 multiplier-accumulator) 20 digital clock managers (DCM) 24 high-speed serial transceivers (622Mb/s to 11.1Gb/s) Up to four PowerPC 405 cores Altera Stratix-II 90nm process Up to 1170 I/Os logic elements 9.6Mb embedded RAM 96 DSP blocks: x18 multipliers 12 PLLs Serial I/O up to 1Gb/s No hard processor cores CPLD/FPGA Architectures L2-72

73 Recall - Elements of an FPGA fabric Logic. Interconnect. I/O pins. IOB IOB IOB LE LE LE interconnect LE LE LE LE LE LE ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.73 Θεοχαρίδης, ΗΜΥ, 2010

74 Ορολογία Configuration: bits that determine logic function + interconnect. CLB: combinational logic block = logic element (LE). LUT: Lookup table = SRAM used for truth table. I/O block (IOB): I/O pin + associated logic and electronics. ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.74 Θεοχαρίδης, ΗΜΥ, 2010

75 Basic I/O Block Structure Three-State FF Enable Clock Set/Reset Output FF Enable D EC SR D EC SR Q Q Three-State Control Output Path Direct Input FF Enable Registered Input Q D EC SR Input Path ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.75 Θεοχαρίδης, ΗΜΥ, 2010

76 IOB Functionality IOB provides interface between the package pins and CLBs Each IOB can work as uni- or bi-directional I/O Outputs can be forced into High Impedance Inputs and outputs can be registered advised for high-performance I/O Inputs can be delayed ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.76 Θεοχαρίδης, ΗΜΥ, 2010

77 Routing Resources CLB CLB CLB CLB PSM CLB PSM CLB Programmable Switch Matrix PSM PSM CLB CLB CLB ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.77 Θεοχαρίδης, ΗΜΥ, 2010

78 Long and Hex Lines ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.78 Θεοχαρίδης, ΗΜΥ, 2010

79 Double and Direct Lines ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.79 Θεοχαρίδης, ΗΜΥ, 2010

80 Programmable wiring Organized into channels. Many wires per channel. Connections between wires made at programmable interconnection points. Must choose: Channels from source to destination. Wires within the channels. ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.80 Θεοχαρίδης, ΗΜΥ, 2010

81 Programmable interconnection point D Q ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.81 Θεοχαρίδης, ΗΜΥ, 2010

82 Programmable wiring paths ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.82 Θεοχαρίδης, ΗΜΥ, 2010

83 Choosing a path LE LE ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.83 Θεοχαρίδης, ΗΜΥ, 2010

84 Routing problems Global routing: Which combination of channels? Local routing: Which wire in each channel? Routing metrics: Net length. Delay. ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.84 Θεοχαρίδης, ΗΜΥ, 2010

85 Segmented wiring Length 1 Length 2 ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.85 Θεοχαρίδης, ΗΜΥ, 2010

86 Offset segments ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.86 Θεοχαρίδης, ΗΜΥ, 2010

87 I/O Fundamental selection: input, output, three-state? Additional features: Register. Voltage levels. Slew rate. ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.87 Θεοχαρίδης, ΗΜΥ, 2010

88 Programming technologies SRAM. Can be programmed many times. Must be programmed at power-up. Antifuse. Programmed once. Flash. Similar to SRAM but using flash memory. ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.88 Θεοχαρίδης, ΗΜΥ, 2010

89 Configuration Must set control bits for: Logic Elements. Interconnect. I/O blocks. Usually configured off-line. Separate burn-in step (antifuse). At power-up (SRAM). ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.89 Θεοχαρίδης, ΗΜΥ, 2010

90 Configuration vs. programming FPGA configuration: Bits stay at the device they program. A configuration bit controls a switch or a logic bit. CPU programming: Instructions are fetched from a memory. Instructions select complex operations. add r1, r2 memory add IR r1, r2 CPU ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.90 Θεοχαρίδης, ΗΜΥ, 2010

91 Reconfiguration Some FPGAs are designed for fast configuration. A few clock cycles, not thousands of clock cycles. Allows hardware to be changed on-the-fly. ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.91 Θεοχαρίδης, ΗΜΥ, 2010

92 FPGA fabric architecture questions Given limited area budget: How many logic elements? How much interconnect? How many I/O blocks? ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.92 Θεοχαρίδης, ΗΜΥ, 2010

93 Logic element questions How many inputs? How many functions? All functions of n inputs or eliminate some combinations? What inputs go to what pieces of the function? Any specialized logic? Adder, etc. What register features? ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.93 Θεοχαρίδης, ΗΜΥ, 2010

94 Interconnect questions How many wires in each channel? Uniform distribution of wiring? How should wires be segmented? How rich is interconnect between channels? How long is the average wire? How much buffering do we add to wires? ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.94 Θεοχαρίδης, ΗΜΥ, 2010

95 I/O block questions How many pins? Maximum number of pins determined by package type. Are pins programmed individually or in groups? Can all pins perform all functions? How many logic families do we support? ΗΜΥ664 Δ02 Εισαγωγή στην Αρχιτεκτονική FPGA.95 Θεοχαρίδης, ΗΜΥ, 2010

96 Input Output I/O Getting data in and out General-purpose I/O Up to banks > 1,000 0 through I/O pins 7 (several 100 MHz) The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

97 Input Output I/O Getting data in and out General-purpose I/O Up to banks > 1,000 0 through I/O pins 7 (several 100 MHz) Special I/O SERIALISERS ~ 10 Gbps transfer rates Transceiver block Differential pairs FPGA Optical TRx The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright 2004 Mentor Graphics Corp. (

98 Basic FPGA Architectures 2005 Xilinx, Inc. All Rights Reserved

99 Overview All Xilinx FPGAs contain the same basic resources Slices (grouped into CLBs) IOBs Contain combinatorial logic and register resources Interface between the FPGA and the outside world Programmable interconnect Other resources Memory Multipliers Global clock buffers Boundary scan logic CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

100 Virtex-II Architecture Block SelectRAM resource I/O Blocks (IOBs) Dedicated multipliers Programmable interconnect Configurable Logic Blocks (CLBs) Virtex -II architecture s core voltage operates at 1.5V Clock Management (DCMs, BUFGMUXes) CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

101 Slices and CLBs Each Virtex -II CLB contains four slices Local routing provides feedback between slices in the same CLB, and it provides routing to neighboring CLBs A switch matrix provides access to general routing resources Switch Matrix BUFT BUF T SHIFT Slice S1 COUT Slice S3 Slice S2 COUT Slice S0 Local Routing CIN CIN CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

102 Simplified Slice Structure Each slice has four outputs Two registered outputs, two non-registered outputs Two BUFTs associated with each CLB, accessible by all 16 CLB outputs Carry logic runs vertically, up only Two independent carry chains per CLB Slice 0 PRE LUT Carry D Q CE LUT Carry CLR D PRE CE Q CLR CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

103 Detailed Slice Structure The next few slides discuss the slice features LUTs MUXF5, MUXF6, MUXF7, MUXF8 (only the F5 and F6 MUX are shown in this diagram) Carry Logic MULT_ANDs Sequential Elements CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

104 Look-Up Tables Combinatorial logic is stored in Look-Up Tables (LUTs) Also called Function Generators (FGs) Capacity is limited by the number of inputs, not by the complexity Delay through the LUT is constant A B C D Z A B C D Combinatorial Logic Z CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

105 Connecting Look-Up Tables CLB Slice S3 Slice S2 F5 F8 F5 F6 MUXF8 combines the two MUXF7 outputs (from the CLB above or below) MUXF6 combines slices S2 and S3 Slice S1 F5 F7 MUXF7 combines the two MUXF6 outputs Slice S0 F5 F6 MUXF6 combines slices S0 and S1 MUXF5 combines LUTs in each slice CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

106 Fast Carry Logic Simple, fast, and complete arithmetic Logic Dedicated XOR gate for single-level sum completion Uses dedicated routing resources All synthesis tools can infer carry logic CIN COUT To S0 of the next CLB First Carry Chain COUT SLICE S1 SLICE S0 CIN COUT To CIN of S2 of the next CLB COUT Second Carry Chain SLICE S3 SLICE S2 CIN CIN CLB CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

107 MULT_AND Gate Highly efficient multiply and add implementation Earlier FPGA architectures require two LUTs per bit to perform the multiplication and addition The MULT_AND gate enables an area reduction by performing the multiply and the add in one LUT per bit A LUT S DI CY_MUX CO CI MULT_AND CY_XOR A x B LUT B LUT CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

108 Flexible Sequential Elements Either flip-flops or latches Two in each slice; eight in each CLB Inputs come from LUTs or from an independent CLB input Separate set and reset controls Can be synchronous or asynchronous All controls are shared within a slice Control signals can be inverted locally within a slice FDRSE_1 D CE S Q R FDCPE D PRE Q CE CLR LDCPE D PRE CE Q G CLR CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

109 Shift Register LUT (SRL16CE) Dynamically addressable serial shift registers Maximum delay of 16 clock cycles per LUT (128 per CLB) Cascadable to other LUTs or CLBs for longer shift registers Dedicated connection from Q15 to D input of the next SRL16CE Shift register length can be changed asynchronously by toggling address A LUT D CE CLK A[3:0] LUT D CE D CE D CE D CE Q Q Q Q Q Q15 (cascade out) CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

110 Shift Register LUT Example The SRL can be used to create a No Operation (NOP) This example uses 64 LUTs (8 CLBs) to replace 576 flip-flops (72 CLBs) and associated routing and delays 12 Cycles 64 Operation A Operation B 4 Cycles 8 Cycles 64 Operation C Operation D - NOP 3 Cycles 12 Cycles 9 Cycles Paths are Statically Balanced CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

111 IOB Element Input path Two DDR registers Output path Two DDR registers Two 3-state enable DDR registers Separate clocks and clock enables for I and O Set and reset signals are shared Reg OCK1 Reg OCK2 Reg OCK1 Reg OCK2 DDR MUX 3-state DDR MUX Output IOB Input Reg ICK1 Reg ICK2 PAD CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

112 SelectIO Standard Allows direct connections to external signals of varied voltages and thresholds Optimizes the speed/noise tradeoff Saves having to place interface components onto your board Differential signaling standards LVDS, BLVDS, ULVDS LDT LVPECL Single-ended I/O standards LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V) PCI-X at 133 MHz, PCI (3.3V at 33 MHz and 66 MHz) GTL, GTLP and more! CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

113 Digital Controlled Impedance (DCI) DCI provides Output drivers that match the impedance of the traces On-chip termination for receivers and transmitters DCI advantages Improves signal integrity by eliminating stub reflections Reduces board routing complexity and component count by eliminating external resistors Eliminates the effects of temperature, voltage, and process variations by using an internal feedback circuit CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

114 Other Virtex-II Features Distributed RAM and block RAM Distributed RAM uses the CLB resources (1 LUT = 16 RAM bits) Block RAM is a dedicated resources on the device (18-kb blocks) Dedicated 18 x 18 multipliers next to block RAMs Clock management resources Sixteen dedicated global clock multiplexers Digital Clock Managers (DCMs) CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

115 Distributed SelectRAM Resources Uses a LUT in a slice as memory Synchronous write Asynchronous read Accompanying flip-flops can be used to create synchronous read RAM and ROM are initialized during configuration Data can be written to RAM after configuration Emulated dual-port RAM One read/write port One read-only port LUT Slice LUT LUT RAM16X1S D WE WCLK A0 O A1 A2 A3 RAM32X1S D WE WCLK A0 O A1 A2 A3 A4 RAM16X1D D WE WCLK A0 SPO A1 A2 A3 DPRA0 DPO DPRA1 DPRA2 DPRA3 CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

116 Block SelectRAM Resources Up to 3.5 Mb of RAM in 18-kb blocks Synchronous read and write True dual-port memory Each port has synchronous read and write capability Different clocks for each port Supports initial values Synchronous reset on output latches Supports parity bits One parity bit per eight data bits 18-kb block SelectRAM memory DIA DIPA ADDRA WEA ENA SSRA DOA CLKA DOPA DIB DIPB ADDRB WEB ENB SSRB CLKB DOB DOPB CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

117 Dedicated Multiplier Blocks 18-bit twos complement signed operation Optimized to implement Multiply and Accumulate functions Multipliers are physically located next to block SelectRAM memory Data_A (18 bits) Data_B (18 bits) 18 x 18 Multiplier Output (36 bits) 4 x 4 signed 8 x 8 signed 12 x 12 signed 18 x 18 signed CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

118 Global Clock Routing Resources Sixteen dedicated global clock multiplexers Eight on the top-center of the die, eight on the bottom-center Driven by a clock input pad, a DCM, or local routing Global clock multiplexers provide the following: Traditional clock buffer (BUFG) function Global clock enable capability (BUFGCE) Glitch-free switching between clock signals (BUFGMUX) Up to eight clock nets can be used in each clock region of the device Each device contains four or more clock regions CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

119 Digital Clock Manager (DCM) Up to twelve DCMs per device Located on the top and bottom edges of the die Driven by clock input pads DCMs provide the following: Delay-Locked Loop (DLL) Digital Frequency Synthesizer (DFS) Digital Phase Shifter (DPS) Up to four outputs of each DCM can drive onto global clock buffers All DCM outputs can drive general routing CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

120 Spartan versus Virtex Lower cost Smaller process = lower core voltage.09 micron versus.15 micron Vccint = 1.2V versus 1.5V Different I/O standard support New standards: 1.2V LVCMOS, 1.8V HSTL, and SSTL Default is LVCMOS, versus LVTTL More I/O pins per package Only one-half of the slices support RAM or SRL16s (SLICEM) Fewer block RAMs and multiplier blocks Same size and functionality Eight global clock multiplexers Two or four DCM blocks No internal 3-state buffers 3-state buffers are in the I/O CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

121 SLICEM and SLICEL Each Spartan -3 CLB contains four slices Left-Hand SLICEM COUT Right-Hand SLICEL COUT Similar to the Virtex -II Slices are grouped in pairs Slice X1Y1 Left-hand SLICEM (Memory) LUTs can be configured as memory or SRL16 Right-hand SLICEL (Logic) Switch Matrix SHIFTIN Slice X1Y0 LUT can be used as logic only Slice X0Y1 Slice X0Y0 Fast Connects SHIFTOUT CIN CIN CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

122 Virtex-4 Features New features Dedicated DSP blocks Phase-matched clock dividers (PMCD) SERDES built into the Virtex -4 SelectIO standard Dynamic reconfiguration port (DRP) Enhanced features Block RAM can be configured as a FIFO Advanced clocking networks, including regional clock buffers and sourcesynchronous support 11.1 Gbps RocketIO Multi-Gigabit Transceiver (MGT) blocks Enhanced PowerPC processor blocks CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

123 Where Can I Learn More? User Guides Documentation User Guides Application Notes Documentation Application Notes Education resources Your course! Your Instructor! CPLD/FPGA Architectures L Xilinx, Inc. All Rights Reserved For Academic Use Only

124 Labs Digilent XUP Virtex II Pro Board od=xupv2p ΗΜΥ664 Δ02 FPGA Architectures.126 Θεοχαρίδης, ΗΜΥ, 2010

125 The Board ΗΜΥ664 Δ02 FPGA Architectures.127 Θεοχαρίδης, ΗΜΥ, 2010

126 FPGA Toolflow Source: Xilinx ΗΜΥ664 Δ02 FPGA Architectures.128 Θεοχαρίδης, ΗΜΥ, 2010

127 Reminders: Tutorial/Homework #1 has been posted, due tomorrow! Demo / Questions I would like to give one lecture this week for those that feel that are not getting to where they feel they should be with Lab 1. Architecture of Field-Programmable Gate Arrays, Proc. PROCEEDINGS OF THE IEEE. VOL 81. NO 7. JULY 1993 Chap 12: Digital Integrated Circuits Second Edition J. Rabaey et. Al. Chap 4 online text book ADDITIONAL READING ΗΜΥ664 Δ02 FPGA Architectures.129 Θεοχαρίδης, ΗΜΥ, 2010