A Family of Adders. Simon Knowles Element 14, Aztec Centre, Bristol, UK Abstract. 2. Addition as a Prefix Problem. 1.

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1 A Famly of Adders Smon Knowles Element 14, Aztec Centre, Brstol, UK Abstract Bnary carry-propagatng addton can be effcently expressed as a prefx computaton. Several examples of adders based on such a formulaton have been publshed, and effcent mplementatons are numerous. Chef among the nown constructons are those of Kogge & Stone and Ladner & Fscher. In ths wor we show that these are end cases of a large famly of addton structures, all of whch share the attractve property of mnmum logcal depth. The ntermedate structures allow trade-offs between the amount of nternal wrng and the fanout of ntermedate nodes, and can thus usually acheve a more attractve combnaton of speed and area/power cost than ether of the nown end-cases. Rules for the constructon of such adders are gven, as are examples of realstc 32b desgns mplemented n an ndustral 0u25 CMOS process. 1. Introducton There are many ways of formulatng the process of bnary addton. Each dfferent way provdes dfferent nsght and thus suggests dfferent mplementatons. Examples are Wenberger & Smth s carry-looahead adder [Wen58], Nadler s pyramd adder [Nadl56], Slansy s condtonal sum adder [Sla60], Bedrj s carry-select adder [Bedr62], and Ladner & Fscher s prefx adder [Ladn80]. For a general ntroducton see [Omon94]. The prefx formulaton s partcularly attractve because t s easly expressed and suggests very effcent mplementatons, e. adders based on ths formulaton can be attractvely fast and compact when mplemented n VLSI. Ths paper s organsed as follows. The next secton reprses the prefx formulaton of addton, and ntroduces the ey propertes of assocatvty and dempotency whch mae ths formulaton so flexble. Secton 3 covers exstng varants of the prefx addton algorthm and ther correspondng mplementatons. Then n Secton 4 we ntroduce a new famly of addton structures, all of whch have mnmum logcal depth le Ladner & Fscher s adder, but whch express dfferent trade-offs between area and speed. The Kogge-Stone [Kogg73] and Ladner- Fscher [Ladn80] adders are the end-cases of ths famly. Secton 5 tabulates expermental data showng the range of performances avalable from the new famly of adders when mplemented n a modern CMOS technology. Fnally Secton 6 ntroduces some less-regular structures whch mght be advantageous n specfc crcumstances. 2. Addton as a Prefx Problem We wsh to compute a sum S=A+B. We wll use captal letters to represent bnary words, small letters to represent bts, and subscrpts to ndcate arthmetc weght, ncreasng from 0 at the lsb. Thus c sgnfes a carry nto bt, and a 4..0 sgnfes the 5 lsb s of A. Operands A and B have n bts, so sum S has n+1 bts. For smplcty we assume there s no nput carry c 0 ; ths can be easly accommodated and does not affect the thess of the paper. For n-bt addton, n a power of 2, a mnmum-depth prefx adder comprses 1+log 2 n unate logcal stages, plus 1 non-unate logcal stage. In CMOS technology ths maps to 3+log 2 n nvertng gate stages, plus whatever bufferng stages are warranted by the desgn crtera. The frst and last logcal stages are bascally the same for all types; prefx adders are dstngushed by the structure of ther ntermedate stages. We wll descrbe the Ladner- Fscher structure ntally, whch s n some sense a bass for the others. The frst stage of the adder computes carry generate (g), propagate (p), and ll () terms for each bt accordng to the relatons: g = a b = a + b p = a b

2 The g and terms are then combned n log 2 n logcal stages (to be descrbed shortly) to produce carres (c ) nto each bt poston usng the teratve relaton: c = g + c +1 The fnal stage computes sum bts (s ) as: s = p c The frst and last stages are ntrnscally fast because they nvolve only smple operatons on sgnals local to each bt poston. The ntermedate stages embody the long-dstance propagaton of carres, so the performance of the adder hnges on ths part. In a prefx adder ths part s constructed of nodes whch perform the prefx operaton : j g +. g =. j j In logcal terms, the prefx operator conssts of an AND gate and an AND-OR gate. The carry nto any bt poston can be computed as a chan of prefx operatons: c = Navely ths can be mplemented as a rpple-carry process, but the prefx operator has two essental propertes whch allow greater parallelsm, and hence faster crcuts. Frstly t s assocatve: h j j = h where h> j>. Secondly t s dempotent, so: h j = h Assocatvty allows the precomputaton of sub-terms of the prefx equatons, whch means the seral teraton mpled by the prefx equaton above can be parallelzed. Idempotency allows these sub-terms to overlap, whch provdes some useful flexblty n the parallelzaton. The Ladner-Fscher scheme explots the assocatvty property (but not the dempotency property) by constructng a bnary tree of prefx operators. The structure s succnctly represented by the prefx graph of Fgure 1, whch shows the lateral connectvty requred between nodes at each stage of a 32b adder. The nputs are at the top, outputs at the bottom, lsb at the rght hand sde. The graph only shows the lateral connectons; there are also mplct vertcal connectons between nodes n the same column. The frst row of nodes computes the g, p, terms. In subsequent rows, the nodes havng lateral connectons mplement the prefx operator, whle those wth no lateral connectons are just place-holders. The fnal row of nodes also computes the sum bts. The fnal carry-out (the msb of the sum) emerges from the most sgnfcant node at the last level but s not represented explctly n the graph. Ths s clearer n Fgure 2, whch shows a detaled gate crcut for a 32b adder correspondng to the graph of Fgure 1. Note that each lateral connecton n the graph corresponds to 2 wres (g, ) n the crcut, except at the last level where the fnal term s not requred. Adders n whch the computaton of carres s based on the prefx equatons above are naturally called prefx adders. Those whch compute multple sub-terms n parallel by explotng the assocatvty property are called parallel prefx adders. Many of these also explot the dempotency property, the most obvous example beng the Kogge-Stone adder ntroduced n the next Secton. 3. The Evoluton of Parallel Prefx Adders Ladner and Fscher [Ladn80] ntroduced the mnmumdepth prefx graph descrbed n the prevous Secton, based on earler theoretcal wor by Ofman [Ofma63]. The longest lateral fannng wres go from a node to n/2 other nodes. Capactve fanout loads become partcularly large for later levels n the graph as ncreasng logcal fanout combnes wth ncreasng span of the wres. In CMOS mplementatons such as Fgure 2 bufferng nverters are added approprately to support these large loads. There s a correspondng cost n delay. Kogge and Stone [Kogg73] addressed ths fanout ssue by ntroducng the recursve doublng algorthm, whch leads, for example, to the 32b prefx graph of fgure 3. The Kogge-Stone scheme uses the dempotency property to lmt the lateral logcal fanout at each node to unty, but at the cost of a dramatc ncrease n the number of lateral wres at each level. Ths s because there s massve overlap between the prefx sub-terms beng precomputed. The span of the lateral wres remans the same as for the Ladner-Fscher structure, so some bufferng s stll usually requred to accommodate the wrng capactance, even though the logcal fanout has been mnmzed.

3 Other researchers have sought to address the problem of hgh fanout nodes n the Ladner-Fscher structure by allowng the logcal depth of the structure to ncrease. Brent & Kung [Bren82] proposed the explct provson of a set of bnary fanout trees such that the lateral fanout of each node s restrcted to unty, as for the Kogge-Stone graph, but wthout the exploson of wres. Although attractve at an abstract level ths approach maes lttle sense n a practcal CMOS context. Frstly the unt logcal fanout lmtaton s arbtrary and somewhat extreme. Secondly, and of course nseparably, the constructon maes no allowance for the fact that much of the capactve load s due to the span of the wres rather than the number of drven nodes. Practcally, t s more effcent to nsert buffers as requred nto the Ladner- Fscher adder, n the manner of Fgure 2, than to use the Brent-Kung scheme. Han and Carlson [Han87] gve a good overvew of prefx addton formulatons, and present ther own hybrd synthess of the Ladner-Fscher and Kogge-Stone graphs. Agan ths trades an ncrease n logcal depth for a reducton n fanout. It s effectvely a hgher-radx varant of the Kogge-Stone scheme. Kowalczu, Tudor & Mlyne [Kowa91] acheve a smlar compromse by seralzng the prefx computaton occurrng at the hgher fanout nodes, and Beaumont-Smth & Burgess [Beau97] combne ths dea wth the Han-Carlson scheme. All these latter papers allow the logcal depth, and hence the delay, of the adder to ncrease n exchange for reductons n fanout or wre flux. Ths paper llustrates that these gans are avalable wthout ncreasng logcal depth from the mnmum used n the Ladner-Fscher and Kogge-Stone structures. Lynch and Swartzlander [Lync91] present a mnmum-depth prefx addton algorthm whch explots the dempotency of the prefx operaton to acheve effcent varants of the Ladner- Fsher formulaton for non-power-of-2 operand wdth. The adders presented n ths paper all have power-of-2 operand wdth, and could lewse be extended to nonpower-of-2 wdths by the Lynch-Swartzlander scheme. 4. A New Famly of Adders The man purpose of ths paper s to ntroduce Fgure 4, whch shows a number of new mnmum-depth prefx graphs for addton. Graphs are shown for 4b, 8b, and 16b adders. The sets are bounded at ether end by the Ladner-Fscher and Kogge-Stone graphs. The graphs are unquely labelled by lstng the lateral fanouts at each level, from the stage nearest the output, bac towards the nput. Thus the Ladner-Fscher graphs are labelled [2,1], [4,2,1], and [8,4,2,1] for 4b, 8b, and 16b adders respectvely, and the correspondng Kogge-Stone graphs are labelled [1,1], [1,1,1], and [1,1,1,1]. The constructon of other members of the famly s farly ntutve, wth smaller graphs beng combned to form progressvely larger ones, and the dempotency property beng used to fll any gaps n the prefx computaton. The followng rules govern the constructon of these graphs: let the wrng levels between rows of graph nodes be numbered from j=0 at nput to j=log 2 (n) 1 at output, then: Lateral wres at the j th level span 2 j bts. The lateral fanout at the j th level s a power of 2 between 1 and 2 j nclusve. The lateral fanout at the j th level cannot exceed that at the (j+1) th level. These rules are suffcent to determne the number of possble mnmum-depth graphs of ths type (see the next secton for further possbltes whch are not strctly of ths type ). For power-of-2 operand wdths the number of graphs s as follows: operand wdth (bts) number of basc mnmum-depth graphs At 4b wdth, the Ladner-Fscher and Kogge-Stone graphs are the only ones havng mnmum depth. Beyond 4b several new possbltes emerge whch offer trade-offs between fanout and number of wres at each level. Fgure 4 shows all such graphs for 4, 8, and 16 bt operands. Fgure 5 shows an example graph for a new 32b adder havng structure [4,4,2,2,1], and Fgure 6 shows a gate crcut mplementng such an adder. 5. Practcal Results Several of these 32b adder desgns have been taen through an ndustral structured-custom desgn flow to layout n a 0µ25 6-metal CMOS process wth 1µm contacted wre ptch. The selecton ncludes the Ladner- Fscher [16,8,4,2,1] and Kogge-Stone [1,1,1,1,1] extrema, and four ntermedate forms. Speed and area results are tabulated below. The number of bufferng nverters added at each level to optmze speed s gven n a way whch corresponds to the labellng of the graphs. These nverters can be seen clearly n Fgures 2 and 6. For the Kogge-Stone [1,1,1,1,1] and Fgure 6 [4,4,2,2,1] examples, two dfferent bufferng schemes are examned.

4 Structure Bufferng Delay Length Transverse wre flux (ref nvs) (µm) By level Total Ladner-Fscher (fg 2) [16,8,4,2,1] [2,1,1,0,0] [1,2,2,2,2] 9 - [16,4,2,2,1] [2,1,1,0,0] [1,4,4,2,2] 13 - [16,2,2,2,1] [2,1,1,0,0] [1,8,4,2,2] 17 (fg 6) [4,4,2,2,1] [1,1,0,0,0] [4,4,4,2,2] 16 - [4,4,2,2,1] [1,1,1,0,0] [4,4,4,2,2] 16 - [2,2,2,1,1] [1,1,1,0,0] [8,8,4,4,2] 26 Kogge-Stone [1,1,1,1,1] [1,1,0,0,0] [16,16,8,4,2] 42 [1,1,1,1,1] [1,1,1,0,0] [16,16,8,4,2] 42 To remove process and envronmental dependences, crtcal path delays are normalzed to the average of the rse and fall delays of a reference nverter under the same condtons. The reference nverter delay s measured n a tree of dentcal nverters such that each nverter drves 4 others wth zero wrng load. For a contemporary 0µ25 CMOS process at worst-case desgn condtons (worstcase process params, 125C, 2V0) ths reference nverter delay wll typcally be n the range ps; n favourable condtons (typcal process params, 25C, 2V5) t wll be 40-50% lower. As expected, the Kogge-Stone adder s the fastest and the Ladner-Fscher the slowest, although the dfference between them s less than 15%. The adders are lad out as datapath slces usng 10µm hgh cells at 2 cell rows per bt. All examples are therefore 640µm hgh. Those nearer the Kogge-Stone extreme are wre-lmted, wth both Kogge-Stone examples requrng 80% more area than the smallest here ([4,4,2,2,1] buffered [1,1,0,0,0]). Because of the dfferences n bufferng requrements, the Ladner-Fscher adder turns out not to be the smallest, by a small margn. 6. Hybrd Schemes The adders shown n Fgure 4 are somewhat homogeneous n constructon, n that the fanout s the same for all fannng nodes wthn a partcular level. Ths s not absolutely necessary, provded the constructon rules set out n the Secton 4 are respected. Other, less regular, structures exst - for example the 16b graph of Fgure 7. Here the crtcal path of an adder close to the Kogge-Stone extreme (n fact [2,1,1,1]) has been preserved, whle paths whch are ntrnscally shorter and therefore less crtcal have been pared bac towards the Ladner-Fscher extreme. In a structured layout envronment the maxmum (rather than average) wrng flux at each level wll tend to determne the layout densty. Therefore t s unlely that rregular hybrds such as Fgure 7 would offer an area advantage n comparson to the regular verson havng the same structure on ts crtcal path (n ths case structure [2,1,1,1] from Fgure 4). The total amount of wrng has nevertheless been reduced so a power advantage mght accrue. In the random placement and routng envronment typcal of contemporary ASIC desgn flows there mght be some area advantage, but n that context the robustness of the other comparsons made n ths paper s reduced. 7. Conclusons The trade-off between crcut speed and area n CMOS s frequently somewhat sharp, and desgners of hgh performance chps often pay a hgh prce n area to close the last few percent on ther speed targets. Gven an effcent baselne mplementaton of any logc crcut, ths fnal speed-up s usually acheved by the pervasve ntroducton of parallel, logcally-redundant paths. Ths s what we are dong n movng from a Ladner-Fscher to a Kogge-Stone formulaton for prefx addton; the ntroducton of redundancy s reflected n the relance on the dempotency of the prefx operaton. The results presented here ndcate that prefx adders mplemented n contemporary CMOS processes from statc gates can acheve a real speed-up of about 15% by ths means, from the Ladner-Fscher baselne. But the cost of achevng ths full potental by adoptng the Kogge-Stone structure s qute large n terms of wrng, and hence area and power. Ths paper has ntroduced a famly of adders whch span a range of speed vs area/power trade-offs between these two extremes. All these adders have mnmum logcal depth. Crcuts qute close n speed to the Kogge-Stone adder are avalable at sgnfcantly lower wrng cost. References [Know98] S.C. Knowles; Desgnng Addton Crcuts Brtsh Patent Applcaton, 17 Aug. 98. [Wen58] A. Wenberger, J.L Smth; A Logc for Hgh-Speed Addton Nat. Bur. Stand. Crc., 591:3-12, [Nadl56] M. Nadler; A Hgh-Speed Electronc Arthmetc Unt for Automatc Computng Machnes Alta Technca (Prague), 6: , 1956.

5 [Sla60] J. Slansy; Condtonal-Sum Addton Logc IRE Trans., EC-9: , June 60. [Bedr62] O.J. Bedrj; Carry-Select Adder IRE Trans., EC- 11: , June 62. [Omon94] A.R. Omond; Computer Arthmetc Systems ISBN , [Ladn80] R.E. Ladner, M.J. Fscher; Parallel Prefx Computaton JACM, 27(4): , Oct. 80. [Kogg73] P.M. Kogge, H.S. Stone; A Parallel Algorthm for the Effcent Soluton of a General Class of Recurrence Equatons IEEE Trans., C-22(8): , Aug. 73. [Ofma73] Y. Ofman; On the Algorthmc Complexty of Dscrete Functons Sovet Physcs Dolady, 7(7): , Jan 63. [Bren82] R.P. Brent, H.T. Kung; A Regular Layout for Parallel Adders IEEE Trans., C-31(3): , March 82. [Han87] T. Han, D.A. Carlson; Fast Area-Effcent VLSI Adders 8th IEEE Symp. Computer Arthmetc, Como Italy, pp , May 87. [Kowa91] J. Kowalczu, S. Tudor, D. Mlyne; A New Archtecture for Automatc Generaton of Fast Ppelned Adders ESSCIRC, Mlano Italy, pp , Sept 91. [Beau97] A. Beaumont-Smth, N. Burgess; A GaAs 32-bt Adder 13 th Symp. Computer Arthmetc, Aslomar Calforna, pp , June 97. [Lync91] T. Lynch, E.E. Swartzlander Jr; The Redundant Cell Adder 10th IEEE Symp. Computer Arthmetc, Grenoble France, pp , June 91. msb lsb Fgure 1: 32b Ladner-Fscher graph [16,8,4,2,1] Fgure 5: 32b graph [4,4,2,2,1] Fgure 3: 32b Kogge-Stone graph [1,1,1,1,1] Fgure 7: 16b hybrd graph

6 lsb Fgure 2: Ladner-Fscher adder [16,8,4,2,1] msb Fgure 2

7 Fgure 4: 4b, 8b, and 16b mnmum-depth graphs

8 Fgure 6: Adder [4,4,2,2,1]

CHAPTER 4 PARALLEL PREFIX ADDER

93 CHAPTER 4 PARALLEL PREFIX ADDER 4.1 INTRODUCTION VLSI Integer adders fnd applcatons n Arthmetc and Logc Unts (ALUs), mcroprocessors and memory addressng unts. Speed of the adder often decdes the mnmum