Proceedings of the 2008 Winter Simulation Conference S. J. Mason, R. R. Hill, L. Mönch, O. Rose, T. Jefferson, J. W. Fowler eds.

Transcription

1 Proceedings of the 2008 Wer Simultion Conference S. J. Mson, R. R. Hill, L. Mönch, O. Rose, T. Jefferson, J. W. Fowler eds. PLCStudio: SIMULATION BASED PLC CODE VERIFICATION Sng C. Prk, Chng Mok Prk, nd Gi-Nm Wng Jongeun Kwk, nd Sungjoo Yeo UDMTEk 113 Ho Snhkwon, Ajou University, Suwon, , South Kore Dept. of Industril nd Informtion Systems Engineering, Ajou University Suwon , South Kore ABSTRACT Proposed in this pper is the rchitecture of PLC progrmming environment tht enbles visul verifiction of PLC progrms. The proposed rchitecture egrtes PLC progrm with corresponding plnt model, so tht users cn uitively verify the PLC progrm in 3D grphic environment. The plnt model includes ll mnufcturing devices of production system s well s corresponding device progrms to perform their tsks in the production system, nd PLC progrm contins the control logic for the plnt model. For the implementtion of the proposed PLC progrmming environment, it is essentil to develop n efficient methodology to construct virtul device model s well s virtul plnt model. The proposed PLC progrmming environment provides n efficient construction method for plnt model bsed on the DEVS (Discrete Event Systems Specifictions) formlism, which supports the specifiction of discrete event models in hierrchicl, modulr mnner. Simultion is n essentil tool in the design nd nlysis of complex systems tht cnnot be esily described by nlyticl or mthemticl models [5, 6]. It is useful for clculting utiliztion sttistics, finding bottlenecks, poing out scheduling errors nd even for creting mnufcturing schedules. Trditionlly, vrious simultion lnguges, including ARENA nd AutoMod, re used for the simultion of mnufcturing systems [14]. Those simultion lnguges hve been widely ccepted both in industry nd in cdemi; however, they remin s nlysis tools for the rough design stge of production line, becuse their simultion models re not relistic enough to be utilized for detiled design or for implementtion purposes. For exmple, rel production lines re usully controlled by PLC (Progrmmble Logic Controller) progrms [3], s shown in Fig. 1, but conventionl simultion lnguges roughly describe the control logic with independent entity flows (job flows) between processes. 1 INTRODUCTION Generlly, industril production lines re dynmic systems whose sttes chnge ccording to the occurrence of vrious events, thus exhibiting the chrcteristics of discrete event system. If mnufcturers re to remin competitive in continuously chnging mrketplce, they must not only continue to improve their products, but lso strive to improve production systems continuously [10]. Thus, n efficient prototyping environment for production systems is crucil. A modern production line is highly egrted system composed of utomted worksttions such s robots with tool-chnging cpbilities, hrdwre hndling system nd storge system, nd computer control system tht controls the opertions of the entire system. The implementtion of production line requires much investment, nd decisions t the design stge hve to be mde very crefully to ensure tht highly utomted mnufcturing system will successfully chieve the ended benefits. Figure 1: Production system controlled by PLC progrm For detiled design (virtul prototyping) of production line, it is necessry to crete much more detiled simultion model tht cn forecst not only the production cpbility of the system but lso the physicl vlidity nd efficiency of co-working mchines nd control /08/$ IEEE 222

2 Prk, Prk, Wng, Kwk, nd Yeo progrms. As shown in Fig. 1, vrious mchines tht operte simultneously in n industril mnufcturing system re usully controlled by PLCs, currently the most suitble nd widely employed industril control technology [1-4]. A PLC (Progrmmble Logic Controller) emultes the behvior of n electric ldder digrm. As they re sequentil mchines, to emulte the workings of prllel circuits tht respond instntneously, PLCs use n input/output imge tble nd scnning cycle. When progrm is being run in PLC it is continuously executing scnning cycle. The progrm scn solves the Boolen logic relted to the informtion in the input tble with tht in output nd ernl rely tbles. In ddition, the informtion in the output nd ernl rely tbles is updted during the progrm scn. In PLC, this Boolen logic is typiclly represented using grphicl lnguge known s ldder digrm [3]. Previous pproches on PLC progrms cn be ctegorized o two groups; 1) Verifiction of given PLC progrm [18, 19], nd 2) Genertion of dependble PLC progrm [15-17]. In the first group, vrious softwre tools hve been developed for the verifiction of PLCbsed systems vi the use of timed utomt, such s UPPAAL2k, KRONOS, Supremic nd HyTech, minly for progrms written in sttement list lnguge lso termed Boolen [2]. Those softwre tools verify PLC progrms to certin ent; however, they remin limited. Since they re minly focusing on the checking of theoreticl ttributes (sfety, liveness, nd rechbility), it is not esy for users to determine whether the PLC progrms ctully chieve the ended control objectives. In the second group, mny reserchers hve focused on the utomtic genertion of PLC progrms from vrious formlisms including stte digrms, Petri nets nd IDEF0. Those formlisms cn help the design process of control logics, however, it is still difficult to find hidden errors which re the most difficult prt of the verifiction of control progrm. To cope with the problem, we need more trnsprent PLC progrmming environment helping users to recognize hidden errors. The objective of this pper is to propose the rchitecture of PLC progrmming environment tht enbles the visul vlidtion of PLC progrm. The proposed PLC progrmming environment employs virtul plnt model consisting of virtul devices, so tht users cn esily verify the PLC progrm. The overll structure of the pper is s follows. Section 2 illustrtes the rchitecture of the proposed PLC progrmming environment, while Section3 describes n efficient construction methodology for plnt model, which cn be synchronized with PLC progrm. Section 4 shows n exmple nd illustrtions. Finlly, concluding remrks re given in Section 5. 2 VISUAL VALIDATION OF PLC PROGRAMS To design the rchitecture of the PLC progrmming environment, it is importnt to understnd the bsic procedure used to construct PLC progrm (ldder digrm). Chung et l. [1] proposed procedure for the development of n industril utomted production system tht consists of nine steps. They re: 1) Define the process to be controlled; 2) Mke sketch of the process opertion; 3) Crete written sequence listing of the process step by step; 4) On the sketch, dd the sensors needed to crry out the control sequence; 5) Add the mnul controls needed for the process-setup or for opertionl checks; 6) Consider the sfety of the operting personnel nd mke dditions nd djustments s needed; 7) Add the mster stop switches required for sfe shutdown; 8) Crete ldder logic digrm tht will be used s bsis for the PLC progrm; nd 9) Consider the possible pos where the process-sequence my go stry. The most timeconsuming tsk for the control logic designers is the 8-th step, which is usully done by the repetitive method of Code writing, testing nd debugging until the control objectives re chieved [2]. The bottleneck of the 8-th step is tht the conventionl PLC progrmming environments re not especilly uitive, prticulrly for the testing nd debugging of PLC progrm, s they show only the sttus of PLC without providing ny links to the trget system (production line). For the vlidtion of PLC progrm, engineers need to imgine the stte chnges of production line from the input nd output ports of PLC. Tht is the reson conventionl PLC progrmming environments re often inefficient nd prone to humn error. As the configurtions of production lines nd their control progrms become more complicted, there is strong need for more uitive PLC progrmming environment. It is hoped tht this pper will tke positive steps in this direction. Figure 2: The proposed PLC progrmming environment 223

3 Prk, Prk, Wng, Kwk, nd Yeo Fig. 2 shows the rchitecture of the proposed PLC progrmming environment. It consists of two lyers, model lyer nd n ppliction lyer. The model lyer hs three models, plnt model (virtul fctory model), PLC progrm (control model) nd n I/O mpping model. The plnt model includes ll mnufcturing devices of the production system s well s the corresponding device progrms to perform their tsks in the production system, nd the PLC progrm contins the control logic for the plnt model. For the egrtion of the plnt model nd the PLC progrm, it is necessry to define the mpping between the plnt model nd the PLC progrm, which is described by the I/O mpping model. The ppliction lyer simultneously provides two erfces to users. The PLC simultor performs the simultion of the control progrm, nd the plnt model visulizer shows the corresponding plnt model (3D grphic models) reflecting the chnging sttes of the production system during the PLC simultion. Thus, it becomes much esier for users to verify the PLC progrm through the plnt model visulizer. Among the three models of the model lyer, the plnt model plys key role in the proposed PLC progrmming environment. As mentioned erlier, the plnt model should contin ll devices s well s the device control progrms. Thus, it cn be considered s virtul fctory model, model executing mnufcturing processes in computers s well s the rel world [11-13]. To implement virtul fctory, it is necessry to construct digitl models for ll the physicl nd logicl elements (entities nd ctivities) of rel fctory. The plnt model consists of mnufcturing devices with their positions in the lyout. To represent such mnufcturing device, this pper employs the concept of virtul device: digitl model imitting the physicl nd logicl spects of rel device. A virtul device needs to min its reltionships with other devices or PLC progrms s well s the inherent ttributes of the device, such s the kinemtics nd geometric shpe. To do so, virtul device is split o two prts; shell nd core. The shell prt cn dpt to the different configurtions of production systems, nd the core prt undertkes the inherent properties of the device. The concept of virtul device is shown in Fig. 3. Figure 3: Virtul device model The reusbility of virtul device is very importnt, s virtul device cn be used for mny different configurtions of production systems. Without the effective reusbility chrcteristic of virtul device, it is more common to crete new components from scrtch thn to serch for useful elements in other systems. For the reusbility of virtul device, it is essentil for the shell prt of virtul device to be flexible enough to be comptible with ny configurtion of production system. To build such shell prt, this pper employs Zeigler s DEVS (Discrete Event Systems Specifictions) formlism [7, 8], which supports the specifiction of discrete event models in hierrchicl, modulr mnner. The semntics of the formlism re highly comptible with objectoriented specifictions for simultion models. Within the DEVS formlism, one must specify two types of submodels: 1) the tomic model, the bsic models from which lrger models re built, nd 2) the coupled model, how tomic models re connected in hierrchicl mnner. Formlly, n tomic model M is specified by 7-tuple: M =< X, S, Y,,, λ, t > X: input events set; S: sequentil sttes set ; Y: output events set; : S S: ernl trnsition function; : Q * X S: ernl trnsition function Q = {(s,e) s S, 0 e t (s)}: totl stte of M; λ : S Y: output function; t : S Rel: time dvnce function. The four elements in the 7-tuple, nmely,, λ ndt, re clled the chrcteristic functions of n tomic model. The second form of the model, termed coupled model, shows method for coupling severl component 224

4 Prk, Prk, Wng, Kwk, nd Yeo models together to form new model. Formlly, couple model DN is defined s: DN =< X, Y, M, EIC, EOC, IC, SELECT > X: input events set; Y: output events set; M: set of ll component models in DEVS; EIC DN.IN * M.IN: ernl input coupling reltion; EOC M.OUT * DN.OUT: ernl output coupling reltion; IC M.OUT * M.IN: ernl coupling reltion; SELECT: 2 M Ø M: tie-breking selector, where the ensions.in nd.out represent the input port set nd the output port set of the respective DEVS models. For the implementtion of the plnt model, the shell prt of virtul device is represented s n tomic model, nd the entire plnt model is represented s coupled model, including the tomic models (virtul devices) nd the coupling reltionships between them. The detil specifictions for the plnt model re ddressed in the following section. Given tht plnt model consists of virtul devices, the construction method of virtul device is described before explining the construction method of plnt model. As explined erlier, virtul device consists of shell prt nd core prt. The core prt of virtul device includes the inherent properties of the device, such s kinemtics, geometric shpe nd the execution of devicelevel commnds. For the modeling of the core prt of virtul device, the CSG (constructive solid geometry) modeling scheme ws employed, s shown in Fig. 5. In the CSG modeling scheme, user cn erctively construct solid model by combining vrious primitives, such s cylinders, spheres, boxes nd cones. To imitte the kinemtics of rel device, it is necessry to define the moving jos nd the ttributes of ech jo. Our finl gol is to provide librry contining ll stndrd mnufcturing devices, such s mchining sttions, AGVs, nd robots. Therefore, users cn esily instntite virtul devices, without mking efforts for modeling virtul devices. 3 PLANT MODEL CONSTRUCTION The objective of the proposed PLC progrmming environment is to provide n uitive PLC progrmming nd verifiction environment by connecting the plnt model to the PLC progrm. To chieve this objective, it is essentil to develop n efficient construction procedure of plnt model. Fig. 4 shows the erctions mong three models of the PLC progrmming environment. The three models re plnt model, n I/O mpping model, nd PLC progrm. The plnt model is controlled by the PLC progrm through the I/O mpping model. Figure 4: Interctions mong three models of the PLC progrmming environment Figure 5: Core prt modeling of virtul device The shell prt, enclosing the core prt, should llow virtul device model to dpt to different plnt configurtions. This prt is modeled s n tomic model of the DEVS formlism, which is timed-fsa (finite stte utomt). To define the shell prt of virtul device, first it is necessry to identify the set of tsks tht re ssigned to the device. The ctivtion of ech tsk is normlly triggered by n ernl signl from either the PLC progrm or other virtul devices. Once the set of tsks is identified for virtul device, it is then possible to rct the stte trnsition digrm, which defines n tomic model of the DEVS formlism. Fig. 6-() shows simple exmple of n AGV (Automtic Guided Vehicle) with two tsks, T1 (movement from p1 to p2) nd T2 (movement from p2 to p1). As the two tsks should be triggered by ernl events, the shell prt of the AGV must hve two 225

5 Prk, Prk, Wng, Kwk, nd Yeo input ports, termed here s Signl_1 nd Signl_2, s shown in Fig. 6-(b). From the set of tsks, it is possible to instntite the stte trnsition digrm utomticlly. For this exmple, there re four sttes, P1, DoT1, P2 nd DoT2. While P1 nd P2 tke ernl events from the input ports (Signl_1, Signl_2) for stte trnsitions, DoT1 nd DoT2 tke ernl events tht re the end events of the two tsks (T1 nd T2). The DEVS tomic model of the virtul device, corresponding to the AGV, cn be described s follows: Shell of virtul device: M =< X, S, Y,,, λ, t X = {Signl_1, Signl_2} S= {P1, DoT1, P2, DoT2} Y= {T1Done, T2Done} (DoT1) = P2 (DoT2) = P1 (P1, Signl_1) = DoT1 (P2, Signl_2) = DoT2 λ (DoT1) = T1Done λ (DoT2) = T2Done t (DoT1) = Time_1. t (DoT2) = Time_2. > 4-(), cn be described s follows: Plnt Model: DN =< X, Y, M, EIC, EOC, IC, SELECT > X = {input1, input2}, Y = {output1, output2} M: = {VD I, VD J } EIC = {(DN.input1* VD J.input2), (DN.input2* VD I.input1)} EOC = {( VD I.output1, DN.output1), (VD J.output1*DN.output2)} IC= {( VD I.output2* VD J.input1)} SELECT: 2 M Ø M: tie-breking selector. The finl objective of the plnt model is the visul vlidtion of PLC progrm. To do so, it is necessry to define the communicting links between the plnt model nd the PLC progrm, which is described by the I/O mpping model. Fig. 7 shows the I/O mpping model for the AGV exmple shown in Fig. 6. Once the I/O mpping reltions re estblished, the PLC progrm cn control the plnt model through the I/O mpping model. Figure 7: I/O mpping model between plnt model nd PLC progrm Figure 6: Shell modeling of virtul device Once virtul device models re constructed, plnt model cn be defined by combining the virtul devices. While virtul devices re described s tomic models, the entire plnt model is modeled s coupled model, including those tomic models nd coupling reltionships between them. Fig. 4-() shows simple exmple of plnt model including two virtul devices, VD I nd VD J. The DEVS couple model of the plnt model, shown in Fig. The proposed methodology for the construction of plnt model hs two mjor benefits. The first is the reusbility of virtul device model, signifying tht the structure of virtul device model chieves independence from the configurtions of production system. The second benefit is the uitiveness in defining the stte trnsition digrm of the virtul device model. Users with only pssing knowledge of discrete event system modeling cn esily define virtul device model simply by identifying the set of tsks. 226

6 Prk, Prk, Wng, Kwk, nd Yeo 4 EXAMPLES & ILLUSTRATIONS Figure 8: 3D grphic model of welding Cell models: plnt model (virtul fctory model), PLC progrm (control model) nd n I/O mpping model. The plnt model includes ll mnufcturing devices of the production system, nd the PLC progrm contins the control logic for the plnt model. The I/O mpping model functions s communiction link between these two models. As the plnt model plys key role in the proposed PLC progrmming environment, it is essentil to develop prcticl methodology in the construction of virtul device model s well s virtul plnt model. To do so, this pper ddresses n efficient construction method of plnt model bsed on the DEVS (Discrete Event Systems Specifictions) formlism, which supports the specifiction of discrete event models in hierrchicl, modulr mnner. The proposed methodology for the construction of plnt model hs two mjor benefits. The first is the reusbility of virtul device model, signifying tht the structure of the virtul device model chieves independence from the configurtions of production system. The second benefit is tht we cn uitively define the stte trnsition digrm of virtul device model. It is not necessry for users to hve in-depth knowledge of discrete event system modeling, s they simply hve to identify set of tsks in order to define virtul device model. Figure 9: Plnt model of welding cell Figure 10: Gntt chrt for checking simultion result 5 DISCUSSION AND CONCLUSIONS This pper proposes the rchitecture of PLC progrmming environment tht enbles visul verifiction of PLC progrm by synchronizing PLC progrm with corresponding virtul plnt model. The model lyer of the proposed rchitecture consists of three REFERENCES C. P. Chung, X. Ln, J. C. Chen, A systemtic procedure for designing stte combion circuits in PLCs, Journl of Industril Technology, 1999;15(3):2-5. S. Mnesis, K. Akntziotis, Automted synthesis of ldder utomtion circuits bsed on stte-digrms, Advnces in Engineering Softwre, 2005;36: A. Rulln, Progrmmble logic controllers versus personl computers for process control, Computers nd Industril Engineering, 1997;33: J. Jng, P. H. Koo, S. Y. Nof, Appliction of design nd control tools in multirobot cell, Computers nd Industril Engineering, 1997;32: P. Klingstm, P. Gullnder, Overview of simultion tools for computer-ided production engineering, Computers in Industry, 1999;38: A. M. A. Al-Ahmri, K. Ridgwy, An egrted modeling method to support mnufcturing system nlysis nd design, Computers in Industry, 1999;38: B. P. Zeigler, Multifcetted modeling nd discrete event simultion, Acdemic Press, Orlnd, T. G. Kim, DEVSIM++ User s Mnul, Deprtment of Electricl Engineering, KAIST, Kore,

7 Prk, Prk, Wng, Kwk, nd Yeo M. P. Groover, Fundmentls of modern mnufcturing, Wiley, B.K. Choi, B.H. Kim, New trends in CIM: Virtul mnufcturing systems for n genertion mnufcturing, Current Advnces in Mechnicl Design nd Production Seventh Ciro University Int. MDP Conf., Ciro, Februry 15-17, 2000, M. Onosto, K. Iwt, Development of virtul mnufcturing system by egrting product models nd fctory models, CIRP, 1993;42(1): K. Iwt, M. Onosto, K. Termoto, S. Oski, A modeling nd simultion rchitecture for virtul mnufcturing systems, CIRP, 1995;44(1): L. Ye, F. Lin, Virtul system simultion A step beyond the conventionl simultion, 22 nd Int. Conf. on Computer nd Industril Engineering, 1997/12/20, Anglni A, Grieco A, Pcell M, Tolio T. Object-oriented modeling nd simultion of flexible mnufcturing system: rule-bsed procedure, Simultion Modeling Prctice nd Theory, 2002;10: G. Fry, Automtic implementtion of Petri net bsed control lgorithms on PLCs, Proceedings of the Americn control conference ACC 2000, Chicgo; 2000, J. S. Lee, P. L. Hsu, A PLC-bsed design for the sequence controller in discrete event systems, Proceedings of the 2000 IEEE Interntionl conference on Control Applictions, Anchorge; 2000, M. A. Jfri, T. O. Boucher, A rule-bsed system for generting ldder logic control progrm from high level system model, Journl of Intelligent Mnufcturing Systems, 1994 ;5 : D. Alexndre, B. Gerd, G. L. Kim, Y. Wng, A tool rchitecture for the n genertion of UPPAAL, ; 2003 G. L. Kim, P. Pul, Y. Wng, UPPAAL in nutshell, Interntionl Journl on Softwre Tools for Technology Trnsfer, 1997;1(1+2): AUTHOR BIOGRAPHIES S.C. PARK is n ssistnt professor in the Deprtment of Industril & Informtion Systems Engineering t Ajou University. Before joining Ajou, he worked for DimlerChrysler Corp. nd CubickTek Co., developing commercil nd in-house CAD/CAM/CAPP/simultion softwre systems. He received his BS, MS, nd PhD degrees from KAIST in 1994, 1996, nd 2000, respectively, ll in industril engineering. His reserch erests include geometric lgorithms in CAD/CAM, process plnning, engineering knowledge mngement, nd discrete event system simultion. He cn be reched vi emil t <milto:scprk@jou.c.kr>. Gi-NAM WANG is deprtment hed nd professor in the Deprtment of Industril & Informtion Systems Engineering t AJOU University, South Kore. He hs completed his PhD in 1992 from Texs A&M University, in Industril Engineering. He hs worked s visiting professor t University of Texs t Austin during His re of reserch is relted to Intelligent Informtion & mnufcturing system, system egrtion & utomtion, e-business solutions nd imge processing. He cn be reched vi emil t <milto:gnwng@jou.c.kr>. CHANG MOK PARK is reserch professor in the Deprtment of Industril & Informtion Systems Engineering t AJOU University. He hs completed his PhD in 2002 from AJOU University, in Industril Engineering. His reserch erest is relted to Intelligent Informtion & mnufcturing system, nd imge processing. He cn be reched vi emil t <milto:cmprk@jou.c.kr>. JONGEUN KWAK is PHD student in Industril nd Informtion Systems Engineering t Ajou University. He did his BS nd MS in Computer Science Deprtment in yer 1994 nd 1996 respectively, from POSTECH, Kore. Before joining PHD, he worked in LG Coopertive Institute of Technology s senior resercher for 5 yers, he lso worked in Unisoft Ltd, nd t Freelncer until He cn be reched vil emil t <milto:jkwk@jou.c.kr>. SUNGJOO YEO is PHD student in the Deprtment of Industril nd Informtion Systems Engineering t Ajou University. He completed his BS, MS in yer 1999 nd 2001 respectively in Ajou University, IISE Deprtment. Before joining PHD, he worked in FUJITSU LIMITED s senior IT consultnt for 7 yers. His reserch re includes simultion nd dt mining. He cn be contcted vi <milto:orihep@jou.c.kr>. 228