Identification of Crosstalk Switch Failures in Domino CMOS Circuits*

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1 2000 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Identification of Crosstalk Switch Failures in Domino CMOS Circuits* Rahul Kundu and R. D. (Shawn) Blanton Center for Electronic Design Automation ECE Department Carnegie Mellon University Pittsburgh, PA Abstract Capacitative coupling will become a dominant problem due to increased parasitic capacitance between adjacent wires and faster signal switching rates. The coupling problem is more acute for domino logic circuits since an irreversible gate output transition can result. We present a method to analyze domino circuits for susceptibility to crosstalk failures from a layout-extracted netlist. Specifically, sites in the circuit that may fail due to crosstalk are identijed. In addition, failure sites are partitioned into two categories (faults or design errors) based on their likelihood of occurrence in the context of manufacturing variations. The method has been implemented and applied to a dual-rail domino Wallace tree circuit with little loss in accuracy, resulting in a 37X speedup over a full analysis using Hspice. 1 Introduction Crosstalk is defined as coupled interference (inductive or capacitive) from one or more signal lines (referred to as aggressor lines) to a logically unrelated signal line (typically called the victim line). As IC feature sizes are scaled, the minimum distance d between adjacent wires will correspondingly decrease. However, the average wire lengths of global wires are increasing proportional to the square root of the chip area [ 11. Thus, the total wire capacitance C =$=v increases, since wire thickness t is typically kept constant to avoid electromigration and large wire resistance. Effort is made to reduce the dielectric constant e with every new generation of technology to minimize coupling. However, the rate of decrease of e is much slower than the decrease in feature size and the increase in wire-length 1 [2]. These trends lead to the increasing importance of capacitative coupling for every *This research effort is sponsored by the Semiconductor Research Corporation under contract ITC INTERNATIONAL TEST CONFERENCE new generation of CMOS technology. Several other factors related to technology scaling will also exacerbate the problem of capacitative coupling. Manufacturing variations: As feature sizes are decreased, manufacturing variations will become more prominent. Two wires that are safely separated in the nominal design may become closer in the actual fabricated IC resulting in excessive coupling. Decrease of substrate capacitance: As feature sizes are decreased, the amount of area overlap between a device or wire and the substrate also decreases, which in turn decreases the substrate capacitance. This decrease of substrate capacitance plays a significant role in determining the impact of coupling. Increase in the number of metal layers: Every new generation of technology is accompanied by an increase in the number of metal layers. The upperlevel metal layers have very low substrate capacitance because of their physical distance from the substrate. But coupling is larger for these signal lines since they are normally thicker (these wires typically carry global signals) than the lower layers in order to reduce resistance. There has been a great deal of recent work on analyzing and detecting crosstalk noise [3] [4] [51 [61 [7] [SI. However, all previous test-related work has focussed on characterizing the impact of crosstalk on static CMOS circuitry. But the nature of crosstalk failure for dynamic circuits such as domino [9] is quite different. In static circuits, crosstalk creates a transient glitch (i.e. a weak or runt pulse) that must be propagated through successive gates to a primary output or a latch during a precise time interval to cause faulty operation [SI. The ditch, /00 $ IEEE

2 OUT / Figure 1: A crosstalk switch failure in a domino circuit: A pulse on the precharge clock input PC charges the dynamic node D to the supply voltage. Victim line B is supposed to remain static, however a glitch on B due to coupling (with input A = 1) can discharge D and cause the gate output OUT to switch erroneously. in addition, must be propagated along a path that maximizes the likelihood of observance [4]. Thus, it is quite difficult to characterize exactly the detection of crosstalk failures in static circuits. On the other hand, the impact,of crosstalk on domino circuits is much more harmful. Here, the crosstalk glitch at the input of a domino gate causes an irreversible charge loss from the dynamic node D of the gate as shown in Figure 1. The resulting erroneous O+l transition at the gate output OUT propagates through successive gates without attenuation if those gates are properly sensitized. Moreover, the timing is not as strict for dynamic logic; the only constraint is that activation and propagation occur within the clock cycle constraint. To our knowledge, no previous work exists on testing domino circuits for crosstalk failure. However, there has been a significant amount of work for other fault models. For example, [ 101 considers transistor stuck-on and stuck-off failures, [ 111 and [ 121 analyze IDDQ failures, [ 131 considers the test of resistive-bridge defects, and path-delay test is described in [ 141 and [ 151. To our knowledge, the impact of coupling on domino logic functionality has been explicitly considered only in [ 161 and [ 171. Specifically, the work in [ 161 examines the effect of different circuit parameters on the severity of crosstalk, while the work in [17] has developed a metric for analyzing noise immunity to crosstalk. In this paper, we present a method for identifying crosstalk susceptible sites within a domino circuit. We use a conservative criterion to identify the conditions required for erroneous switching to occur in domino gates. These conditions are incorporated into a generalized ATPG tool to determine if the logic value assignments required to create the erroneous switch and to propagate it to an observable point are feasible, given the logic implemented by the circuit. If it is possible to justify the logic value assignments required to activate and propagate a crosstalk failure in the nominal circuit, we designate that as a crosstalk design error. On the other hand, if erroneous operation is only likely in the presence of fabrication variations and/or defects, then the susceptible site is deemed a crosstalk fault. Our method for crosstalk failure analysis has been developed for domino circuits that utilize keepers and footers but no internal pre-chargers. However, the approach can be extended to other varieties of domino logic. The remaining parts of this paper are organized as follows. Section 2 gives an overview of our approach to coupling switch failure identification. In Section 3, we model and analyze the conditions necessary for erroneous gate output switching due to coupling in domino circuits, while Section 4 describes our algorithm for identifying failures using the method of Section 3. Section 5 applies our method to a carry-save adder (Wallace tree) implemented in dual-rail domino, 0.25pm technology. Finally, in Section 6 we summarize our work and present directions for future work. 2 Crosstalk Failures Crosstalk failures in domino circuits can be of two types: Crosstalk Timing Failures: This kind of failure occurs when a victim line is supposed to have a 0+1 transition, but the transition is slowed due to coupling to adjacent lines. This slowed transition manifests as a delay failure; detection requires transition propagation along a path that includes the failure site, with proper timing margin. Our analysis, for now, excludes such failures. Crosstalk Switch Failures: This failure occurs when a victim line is supposed to remain static. But because of coupling to adjacent lines that switch, a crosstalk glitch is created on the victim line. This glitch discharges the dynamic node of the destination gate of the victim line and results in an erroneous 0+1 transition at the output. Detection of this failure requires sensitization of any path from the failure site to an observable point. Our analysis in this paper is focussed on crosstalk switch failures. Our approach to crosstalk switch failure identification is illustrated in Figure 2. First, our crosstalk analyzer examines an extracted netlist of the circuit and produces a list of lines that are potentially susceptible to a crosstalk switch failure. This list of lines is identified in a conservative fashion, that is, the crosstalk analyzer tool always overestimates the amount of crosstalk and therefore never excludes potential failure sites; however, it 503

3 ~~~ Extracted netlist - Crosstalk failure sites Hspice failure sites ATPG and Hspice parameters analyzer * simulator fault simulator --+ Final test set Figure 2: Crosstalk failure identification: The crosstalk analyzer examines an extracted netlist to generate a list of potential failure sites. Failure sites are then analyzed by performing local Hspice simulations of the victim gate to precisely determine the conditions for the failures. Finally, ATPG and fault simulation are performed to produce the final set of test vectors. can falsely include sites that are not vulnerable. But the major advantage is that the crosstalk analyzer effectively disregards a large fraction of lines that are not susceptible to crosstalk. For each potential victim line identified by the crosstalk analyzer, a limited but accurate Hspicebased analysis is performed to determine the minimum amount of coupling required to cause a crosstalk failure. All sets of aggressor lines that meet or exceed the minimum amount of coupling are then determined. Each aggressor line set is then encoded in the fault tuple format [ 181 and passed to a test generator to determine if the corresponding failure is actually testable. If the fault tuple is proven untestable (i.e. cannot be activated and observed), the corresponding failure is considered logically redundant and is dropped. Otherwise, it is reported as a failure and the vector generated by the ATPG tool is added to a final test set. This process can be repeated for different degrees of manufacturing variations and, based on the outcome, the failures can be categorized as either design errors or faults. 3 Modeling Crosstalk In this section, we describe an analytical metric for identifying the initial set of potential failure sites. We begin by stating our assumptions and then analyze the conditions required for the effect of a crosstalk glitch to manifest at the output of a domino gate. 3.1 Preliminaries In analyzing crosstalk in domino logic circuits, we recognize that a line in the circuit can be coupled to multiple adjacent lines (potential aggressor lines). The major crosstalk failure sites (victim lines) are the long global lines. A global victim line may be coupled to a large number of small adjacent lines along its length. The capacitance of the large line to each of the adjacent lines is small, but the combined capacitance of the adjacent lines may be a significant fraction of the total capacitance coupled to the global line. Also, the coupling capacitance of the victim line to each individual adjacent line is assumed to be negligible, such that the adjacent lines are not significantly slowed. Consider n adjacent lines a1, a2,..., a, coupled to one victim line w. Each adjacent line ai is coupled to the victim line with capacitance Ci so that Ci = Ctotal is the the total capacitance coupled to the victim line. Of these adjacent lines, several lines can potentially switch in one clock cycle. These are the aggressor signal lines. The remaining adjacent lines are the non-switching lines or static lines. Partitioning adjacent lines into static and aggressor categories depends on the logical function implemented by the circuit. To analyze the multiple aggressor, single victim case described above, we make three approximations. First, we assume that the aggressor lines switch instantly, that is, an aggressor transition is a perfect step. Second, we assume all aggressors transition simultaneously. These two approximations produce the worst case crosstalk noise [21]. Third, we assume that the potential across the channel of the victim transistor is initially equal to the full supply voltage. This assumption is later removed when an Hspice analysis of the victim gate is performed. (See Section 3.3.) Thus, our crosstalk analyzer is conservative in that it cannot omit potential crosstalk failure sites. Let Ca be the sum of the coupling capacitances of all the aggressor lines and C, be the sum of the coupling capacitances of all the static adjacent lines. Note, that Ca + C, = Ctotal. A circuit model that illustrates this situation is shown in Figure 3. Using Laplace transform techniques, the waveform at the victim line can be estimated to be where Rdrv is the drain resistance of the driving gate,' C, is the input capacitance of the victim gate and VDD is the supply voltage. Since Ctotal is constant for every victim line, the only variable parameter in the expression for the waveform is Ca. 'Drain resistance a,, changes during the duration of the crosstalk pulse depending on the voltage at the drain. 504

4 PC Victim Line v A r- %LJ 0. J I Figure 3: (a) Adjacent lines to a victim signal line are divided into aggressor and static lines. (b) Circuit model used for analyzing the coupling waveform at the dynamic gate input: Ca is the coupling capacitance of the aggressor lines, Cs is the coupling capacitance of the static lines, C, is the input capacitance of the victim gate and RdT, is the drain resistance of the driving gate. 3.2 Coupling Discharge Now consider the discharging of the dynamic node D in Figure 4. In order to predict the current through a MOS- FET, we use the alpha power law proposed in [19]. It predicts the current through the MOSFET as a function of the voltages at its source, drain and gate. The alpha power law equations closely approximate the actual characteristic curves of the 0.25pm technology we use here. The alpha power law equations are shown below: Vth =Vto-yvbs (2) Vdsat = K(Vgs - &hlm (3) ID = Idsat (4) = % B(V~S - ~ t h ) (forvds ~ L Vdsat) (5) ID = Idsat(2 -&)A vdrat v,,,, (for Vds < Vdsat) (6) where W,ff and L,ff are the effective channel width and length respectively, Vth is the threshold voltage, Vto is the threshold voltage at zero substrate voltage, Vg, is the gate-to-source voltage, Vbs is the body-to-source voltage, vd/ds is the drain-to-source voltage, V&at is the drainto-source voltage at saturation, In is the drain current, A... A I B I... 7 I PC n \ D... Figure 4: Discharging of the dynamic node D due to a crosstalk pulse at line A. and K, m, B, y and n are empirical constants derived using techniques described in [19]. After the precharge clock PC becomes high, the voltage at the dynamic node quickly rises to approximately where Cgdl, C&, and Ci,, are the gate-to-drain capacitances of the transistors tl and t4 and the input capacitance of the inverter, respectively. (See Figure 4.) Each gate-to-drain capacitance is a combination of the overlap capacitance and a portion of the gate-to-channel capacitance [20]. The following conditions are assumed to exist before the crosstalk glitch: the gate inputs of all the transistors in the evaluate chain except the victim line are at logic one (which is essential for a test vector) which implies that the node c in Figure 4 is discharged, and the dynamic node D is at VoTig. For a crosstalk failure to occur, the current (It- II,) has to discharge the inverter input so that its transition point is crossed, where the current It passing through transistor t2 and current II, passing through the keeper are derived from the alpha-power law expressions. The switching indut voltage Vrqrri+rh can be easilv calculated 505

5 from the geometry of the inverter and is given in [20] as vdd + vtp + vtn& Vswrtch = (8) 1+JE where pp and Pn are the p factors of the p- and n-type transistors of the inverter, vtp and Vt, are the threshold voltages of the p- and n-channel transistors, respectively. Thus, the total discharge required for a crosstalk switch to occur is described by the expression /(It - Ik)dt 2 (vorig - haitch) x CZnv (9) The integral in (9) can be easily evaluated using simple numerical techniques. Then, a binary search on Ca between the values 0 and Ctotal + C, can easily be performed to determine the minimum C, = Cmin that will satisfy the inequality of (9). Note, the crosstalk analyzer always predicts a lower value of Cmin than what is actually required for failure in the circuit, due to the following pessimistic assumptions. 0 All the aggressor lines switch instantly and simultaneously as explained in Section The voltage at the source of the victim transistor is zero and the drain is at Vorig, when the dynamic node begins discharging. In reality, the source is above the ground with the actual voltage depending on the number and sizes of series-connected transistors below the victim transistor. Also, the drain goes slightly below Vorig depending on the number of series-connected transistors above the victim transistor. The overestimation of Cmin is somewhat relaxed by performing a local analysis of each victim gate using Hspice as described in the next section. 3.3 Hspice Validation If, for a particular victim line, the total coupled capacitance Ctotal is less than the minimum (Cmin) required for failure, the victim line is dropped from further analysis. If, however, Ctotal 2 Cmin, Hspice is used to determine a more precise value of Cmin. Specifically, the destination gate of the victim line is simulated using Hspice. For the simulation, the victim line is connected through a variable capacitance Ccoup to an aggressor waveform that transitions with the maximum slope that can occur in the circuit. (See Figure 6.) Ccoup is varied from 0 to Ctotal to determine the minimum value of Ccoup for - - our Figure 6: Circuit model simulated during Hspice validation. which a failure is induced at node OUT of Figure 6. This minimum value obtained from Hspice analysis is recorded as the new Cmin for the victim line. Hspice analysis removes the some of the pessimism described in the previous section, because the effect of the seriesconnected transistors and the slope of the aggressor transitions are considered. Using Hspice at this stage is justified since only a few victim lines meet the criterion used by the crosstalk analyzer, So, if the crosstalk analyzer reports that a particular line is a potential candidate for crosstalk failure, Hspice is used to determine a more precise value of Cmin. 4 Failure Identification Once the required capacitance Cmin for a victim line is re-calculated using Hspice, all combinations of the adjacent lines whose coupling capacitances sum to at least Cmin is determined. If a logical 1 can be justified on every line in such a combination-justifying a logic 1 in a domino circuit at the gate level creates a O-+ 1 switch in the evaluate phase-a crosstalk pulse of the required strength can be created on the victim line and a crosstalk error at the output of the victim gate can be created.* The smallest subsets of adjacent lines that sum to Cmin are determined. If the smallest subsets cannot be simultaneously sensitized then no superset of those lines can be sensitized, thus they represent the minimal circuit requirements needed to cause a crosstalk failure. The algorithm used for finding the smallest subsets of lines is described in Figure 5. The function Smallest-subset takes as input a set of adjacent lines denoted as combination. It determines if any of the immediate subsets of combination sum to 'Some aggressors are internal lines of a domino gate and thus cannot have a O-tl transition during the evaluate phase. However, the internal lines typically have very small coupling capacitances, and can thus be neglected. 506

6 Small e s t-subset (combination 1 ( invalid = 0; for each immediate subset subi of combination do if CsZLbi C L Cmin {Smallest-subset (subi); set invalid = 1; 1 ) if (invalid == 0) record combination ; Figure 5: Algorithm for determining the minimum set of lines with coupling capacitance Cmin. or exceeds Cmin, where immediate subset refers to the sub-combinations derived by removing any one line from combination. If none of the immediate subsets meets Cmin, it records the combination as a minimum subset. Otherwise, it recursively calls Smallest-subset on those immediate subsets of Combination that meet Cmin. The function Smallest-subset is executed once on the combination containing all the adjacent lines to the victim. The major advantage of the algorithm is that it does not traverse the entire search space of combinations (which is exponential in the number of adjacent lines to the victim). The function Smallest-subset recursively calls itself for only those combinations that meet or exceed Cmin, which is likely to be a small number for most designs. After all sets of adjacent lines are found that satisfy Cj Cj 2 Cmin, the next task is to determine if the required line assignments can be justified, and if the resulting error can be propagated to an observable point. Each such failure due to a subset of adjacent lines is modeled using the fault tuple concept developed in [18]. We formally define a crosstalk failure as a two-tuple (A, U), where A = {al,a2,a3,...,am} (m 5 n) is a set of aggressor signal lines coupled to a victim signal line U. We use the fault tuple test generation and fault simulation tools of [22] and [ 181 respectively, to determine crosstalk switch failure testability. If the fault corresponding to the failure is proven untestable, the failure is dropped since the effect of the failure is unobservable at the circuit outputs. Manufacturing variations are accounted for in the following way. The parameter,d (where 0 5 p 5 1) is used to represent the amount of variation in the fabrication process. In analyzing each failure, the coupling capacitances of all the aggressor lines are increased by a factor of (1 +,d), and the capacitances of all the static lines are decreased by a factor of (1 - p). The victim line driver resistance is also increased by (1 + 0). These changes No. of victim lines identified No. of victim No. of lines validated validated No. of I by crosstalk I by Hspice I crosstalk I testable I Table 1: The number of testable crosstalk switch failures identified for different values of /? for a dual-rail domino Wallace tree multiplier designed using a 2-metal, 0.25pm, 2.5V technology. create conditions more conducive to a crosstalk failure and, thus indicates if the failure can occur in the presence of variations. The entire flow of Figure 2 can be repeated for a new set of capacitance and driver resistance values. These newly identified failures do not occur in the nominal design and therefore are not crosstalk design errors but crosstalk faults that are probable in the presence of manufacturing variations quantified by,d. This analysis can be carried out for different values of,d. As,d increases, an increased number of failures can occur and these failures should be tested at the time of manufacturing, if the level of manufacturing variation indicated by,d reflects the current state of the process. 5 Failure Analysis Results The crosstalk analyzer tool, written in about 2000 lines of C, implements a majority of the flow shown in Figure 2. Our approach requires transistor netlists with accurate couvling cauacitance information. We avplied our 507

7 method to a dual-rail domino Wallace tree multiplier that was designed using a 2-metal, 0.25pm, 2.5V technology [23]. The overall design consists of 1806 transistors, arranged in 43 identical adder cells that formed a total of 172 domino gates. Each domino gate utilizes a footer transistor but no keeper^.^ The average number of lines coupled to each gate output is (with a minimum of 5 and a maximum of 21). The layout of the Wallace tree was generated automatically using an industrial place and route tool. A netlist containing parasitic capacitances was extracted from the layout using the tool Space [24]. The crosstalk analyzer tool was run on the extracted netlist of the multiplier. The time required for analyzing the complete netlist using our analyzer required 86.7 seconds whereas a similar analysis of the whole netlist using Hspice required seconds of CPU time, a speedup 37X. For the nominal design (/3 = 0), the crosstalk analyzer reduced the number of candidate victim lines from 172 to 3. For each of the candidate victim lines, Hspice was used to validate the failure. All possible sets of aggressor lines that can create the failure were then passed to a test generator [22], where it was determined that none of these failures are testable, implying that the nominal design is free from crosstalk design errors. Next, the procedure was repeated for fabrication variations. The results for different values of /3 are shown in Table 1. The first column shows the /3 values used. The second column shows the number of potential crosstalk sites identified by the crosstalk analyzer tool. In each case, it is observed that as /3 increases, more and more lines become potential victims of crosstalk. For each /3 value, the identified candidate victim lines are then passed to the Hspice validation block. The number of victim lines which are validated by Hspice analysis are shown in column three. The number of possible failures for each validated victim line is then generated and shown in column four. The testability of each of these failures is then determined using the ATPG and fault simulator block. The number of testable failures in the entire circuit are shown in column five of Table 1. 6 Conclusion We have described and implemented an efficient methodology for identifying crosstalk failures in CMOS domino circuits. Our crosstalk analysis tool accepts an extracted netlist of the circuit and uses a deterministic metric to identify sites that are likely to suffer from crosstalk. Depending on their likelihood of occurrence, susceptible 3The analysis described in Section 3 was modified by removing the ZL. term from eauation sites are identified as either design errors (present in every instance of the circuit) or faults (present in some circuits due to defects or extreme manufacturing variations). Limited Hspice analysis and ATPG are then used to confirm the existence and testability of the crosstalk failures, respectively. The final output produced is a set of test vectors for the confirmed errors and faults. The efficiency of the technique is demonstrated by the 37X speedup achieved over a similar analysis that uses Hspice. Our methodology, however, is subject to some simplifying assumptions that must be resolved in order to ensure the soundness of our approach. First, it assumes that all aggressor lines transition simultaneously,which obviously may or may not be case. Even if all aggressors can transition (nearly) at the same time, the problem of generating a test vector now becomes a complex optimization task. Related to this issue is the timing analysis required for activating and observing crosstalk failures within a given clock cycle constraint. Current work is focussed on augmenting our methodology to effectively deal with these realistic complexities. References Y. Taur, CMOS Scaling into the Nanometer Regime, Proc. of the IEEE, Vol. 85, No. 4, pp , April D. Sylvester and K. Keutzer, Getting to the Bottom of Deep Submicron, Proc. of the 1998 IEEE/ACM International Conference on Computer-Aided Design, pp , Nov A. Rubio, N. Itazaki, X. Xu and K. Kinoshita, An Approach to the Analysis and Detection of Crosstalk Faults in Digital VLSI Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 13, No. l, pp , March K. T. Lee, C. Nordquist and J. A. Abraham, Test Generation for Crosstalk Effects in VLSI Circuits, Proc. of the 1996 IEEE Intemational Symposium on Circuits and Systems, pp , May W. Chen, S. K. Gupta and M. A. Breuer, Analytic Models for Crosstalk Delay and Pulse Analysis under Non-Ideal Inputs, Proc. of the International Test Conference, pp , Oct W. Chen, S. K. Gupta and M. A. Breuer, Test Generation in VLSI Circuits for Crosstalk Noise, Proc. of the Intemational Test Conference, pp , Oct

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