ACCELERATING CHIP-LEVEL ROUTING AND DESIGN

Transcription

1 ACCELERATING CHIP-LEVEL ROUTING AND DESIGN Johnny Premkumar National Semiconductor Corporation September 2005 ABSTRACT This paper focuses on optimizing and improving time to market of the mixed-signal toplevel layout routing task. Using a design database specifics such as the technology data, design preparation, connectivity information, and routing controls in the Cadence Chip Assembly Router(CCAR) will be discussed. Emphasis will be on fine-tuning the toplevel routing flow to achieve greater density, design quality, speed, and productivity. Data preparation entails the generation and placement of layout blocks and I/O cells. Power and ground rails are then drawn. Some critical nets as well as via arrays are prerouted. Pins and connectivity on all added polygons is ensured. In the CCAR, the plain text do file is optimized to automate as much routing as possible. The I/O cells are routed first. The component pins are connected to the power and ground trunks. This is followed by the global route. Multiple detailed routes are performed to get optimal routing. Finally post-route clean up is done to remove unwanted wiring such as notches and unnecessary vias.

2 1. INTRODUCTION In the electronics industry recent developments have increased the number of devices and the functionality that can be put on a chip where these chips include several digital and analog circuits. Automating a good percentage of chip-level layout design is critical for improving the time to market. The requirements demanding this task are manufacturing, density, design quality, speed, noise sensitivity, and productivity. In this paper the focus will be on automating as much as possible this chip assembly procedure. Firstly, I will briefly describe the layout design of the sub-blocks. Then the preparation and the interconnection of these blocks at the top-level will be dealt with in more detail. The chip assembly flow incorporates a layout accelerator, a design rule driven editing environment, parameterized cells(pcells) and automated routing all in a connectivity based environment to achieve optimal layout and productivity. 2. METHODOLOGY The methodology and the flow utilized helps to accelerate chip layout design. The tools utilized are primarily from Cadence Design Systems which have been customized for the National Semiconductor mixed-signal design CAD environment. The layout generation and design of the sub-blocks is done using the Automated Custom Physical Design(ACPD) flow. The top-level layout, which consists of the sub-blocks, is then generated in Virtuoso XL (VXL). The layout is placed and necessary top-level routing preparation is done. The layout is then routed in the Cadence Chip Assembly Router (CCAR) tool. All the tools and flows are intricately integrated so that the designer does not have to spend too much time in translation, import, and export of intermediary files between different tools or vendors. Flow diagram: Digital Cells(VXL, Pcells, VCP, VCR ) Device Level Layout Design (ACPD flow) Analog Cells(Neocell, Pcells) Pre-routes (Wire Editor) Top Level Placement (VXL) Abstract Views (Abstract Generator) CCAR do files CCT rules Top Level Automatic Routing (CCAR) Load CCAR do file Global Route(Analyze) Detail Route Fix Conflicts, Interactive Routes ECO, Post Route VXL, Physical Verification

3 3. DEVICE LEVEL The top-level schematic typically consists of several symbols and lower level blocks(subblocks) being connected to each other to achieve a meaningful design. The layout generation and design of these blocks, which are sub-blocks in the top level schematic, is done first. 3.1 Layout Design For device level layout generation and design the Automated Custom Physical Design (ACPD) flow is utilized. This is a schematic driven flow. For digital blocks the schematic is opened in the Composer tool. From the schematic the Virtuoso XL (VXL) tool is invoked. VXL is the Cadence Layout Editor and Layout Accelerator tool. The layout instances, majority of these being standard cells, is generated and randomly placed. The Virtuoso Custom Placer(VCP) tool is used to do automatic placement. The placed layout is translated to the Virtuoso Custom Router(VCR) for automatic routing at the cell level. The routed design is then imported back into VXL. For analog blocks, the schematic is invoked. Circuit constraints are entered into the Neocell Constraint Editor for automatic place and route. The Neocell layout Editor is invoked. The layout is generated using pcells and Neocell module generators. The pcells are developed in advanced ROD skill while the Neocell generators are developed in the tcl language by the CAD group. Based on the constraints the Neocell tool can be utilized to do automatic placement. This is followed by automatic routing. This final layout is then exported into VXL. The above steps are repeated for all the sub-blocks in the top-level schematic. 4. TOP LEVEL ROUTING PREPARATION Once all of the sub-blocks are created using the ACPD flow, preparation for the chip level layout design is started. 4.1 Abstract Views Abstract views need to be created for all the sub-blocks. To create abstract views, the Cadence Abstract Generator is invoked from VXL. Some technology file setup is required to be done by the CAD group in order to run the Abstract Generator. The Abstract Generator allows the user to import layout information and create abstracts. For each block the Pins step, the Extract step, and the Abstract step need to be completed. The resulting abstracts, for each sub-block, would essentially be a box consisting of prboundary with boundary purpose layer and also include the I/O pins associated with that block. The abstract views would later be used to facilitate the top-level layout design. Abstracts, as opposed to raw layout data, enable faster data translation from VXL to

4 CCAR as well as improve the interconnect speed in CCAR which is critical at the chip level. 4.2 Virtuoso XL The top-level schematic is opened. VXL is invoked and used to generate the layout from the schematic. In the layout generation form particular metal pin layers for the respective I/O pins is specified. After auto-generation, the layout will have several blocks and instances(pcells) randomly placed. The layout instances and blocks extract the connectivity between them and the I/O pins from the schematic. The layout is then manually placed. All Electro Static Discharge(ESD) devices and pads are manually placed and aligned to instances and blocks to facilitate I/O cell routing in CCAR later. The VXL tool is used to confirm the one-to-one correspondence of the instances, blocks, and pins between the layout and schematic. 4.3 CCT Rules Setup The CCT rules file is the technology file used by CCAR for translating routing data and requirements from VXL. This is a plain text file with separate sections. The icclayers section is where the information about routing layers, contacts, vias, diffusion, well, and implant layers are entered. This is followed by the iccvias section which specifies the contact and via instances to be used while routing from the primitive library. The iccequivalentlayers section specifies the layers that need to be treated the same as the pin purpose layers. This is so that if there is a pin information on these layers then CCAR would recognize the connectivity. The iccboundarylayers section specifies the prboundary with drawing purpose layer as the boundary layer. Lastly, the icckeepouts section lists keepout areas in the design where routing should not happen. Here the prboundary with Boundary purpose is set as a keepout for all routing layers. The prboundary with Boundary purpose layer is the layer that encompasses the abstract view. So basically the router can only route to the pins inside these abstract blocks by cutting keepouts which is specified by the designer. At National Semiconductor, the standard CCT rules are developed and maintained by the CAD group for each process. In the VXL environment, the user is prompted to choose the right CCT rules based on the number of metal layers. This automatically creates the file in the user design area. 4.4 Pre-routes Pre-routes of critical wires and busses are done in VXL. Pre-routes are completed using path stitching or by using the Wire Editor tool. The path stitching feature is maintained in the technology file by the CAD group. The Wire Editor is an automatic point to point automatic router and includes features such as the design rule correct (DRC) interactive routing and editing, bus routing, and the compaction of routes. Some setup, including the CCT rules, is necessary to utilize the Wire Editor. Power rails are drawn at specific locations with a particular width. Via arrays, and extra thick metal segments and busses are also routed.

5 5. CADENCE CHIP ASSEMBLY ROUTER(CCAR) The CCAR tool is an extensive and advanced chip level router primarily for analog designs and small digital designs. CCAR includes on the fly DRC checking for routing layers, pushing of nets while routing, cross-coupled and differential pair routing, and shielded routing. It is a shape based router with an easy interface with the Cadence VXL tool. From VXL, which has the top level placement, the CCAR tool is invoked. The design as well as all the layers and routing information from the cctrules is translated into CCAR. Here the abstract views are translated into CCAR which makes the translation and routing of the design much faster. Before translation, in the Export Form, the option is selected to enable the Cut Pins to Edge feature. This is to cut keepouts so that the Router can reach the pins inside the abstract blocks. The user can use the pull down menus or enter the CCAR commands in the command line. Alternatively the CCAR commands can be entered in a separate plain text file with extension.do. Running this do file will enable CCAR to route the design automatically based on the constraints and commands set in this file. 5.1 CCAR do file setup The CCAR do file is developed from scratch. The do file is constructed with various sections. The comands need to be entered in a particular sequence to achieve best results. A Constraint.do file is created using a text editor to input the commands as specified in the following Initialization and Rules sections. Create another plain text file called Global.do which will include the commands in the Global Route section below. Finally create a Route.do text file that includes commands in the Detail Route section. Initialization We start with specifying the process, wire, via grid sizes. Any offsets may also be included. This is followed by the routing directions for all the routing layers. Typically by default Poly is orthogonal, Metal1 is horizontal, Metal2 is vertical, Metal3 is horizontal, Metal4 is vertical, and Metal5 is horizontal. Poly layer is specified as an unselected layer, meaning it would not be used for routing unless due to extreme space constraint. This is obviously to limit the high resistance associated with the Poly layer. Offgrid routing is avoided either by forbidding or by placing a high cost on it. Via Stacking is turned on. Unnecessary extended wires are to be trimmed. Commands are entered to avoid notches. Groups and classes of nets are created. Particular rules can be assigned to these groups and classes. Specific via arrays are setup. Rules Width and clearance based rules are entered for routing layers. Wide metal spacing rules are specified based on process rules. The minimum process width is specified for all

6 routing layers. Minimum endcap area rules are specified to meet DRC rules. Vias are specified to be placed on the pins. Pin escape command is entered to pre-route short metal wires out of areas such as poly contacts and vias to ease detailed routing later. Specify vias not be placed on the power nets. Specify only certain layers for particular nets. Various inter layer rules not specified in the Opus technology file, such as the spacing between diffusion and contact, are entered. To control the terminal to terminal routing of segments between instances, fromto rules are setup. Specify nets to have the same width always by using the pin_width_taper off command. Alternately, users can specify the wire segment to reduce or enlarge the wire segment when entering or exiting a pin. Some regions may be defined as keepout areas for routing. Net priority is assigned for routing. Implement the option for cutting keepouts to edges which will enable the router to connect to the pins in the keepout regions. Global Route Global route is specified as 3 iterations using the Layer Panel option. The Global route maps paths for each unrouted net in the high level design. Then it creates what are called gcells to guide the detail router during detail routing and in effect reducing the process time for detail routing. Detail Route Select all power and ground nets and route them first. Protect these nets so that the existing routing is saved. Unselect the power and ground nets and select the other nets. Shielding could be be done on sensitive wires. Define net pairs for matched routing such as wire topology, layers, and wire length. Cross talk rules are setup such as the parallel and tandem rule by segment. Re-run global route. Global route is followed by detail routing passes. The clean command is used to remove unnecessary jogs, vias, and contacts. This is to also to reduce space and resistance caused by such routing. This is followed by commands to remove notches that still exist. This completes the development of necessary sample do files needed to complete automatic routing in CCAR. The do files can be adjusted and could be even more detailed depending on the design requirements. 5.2 Route the I/O cells In CCAR all the I/O cells are selected. The Power Router is invoked from the pull-down menu. The As I/O Ring option is selected and applied on all the selected instances. This will start the I/O routing. If there are power route failures which is evident by the x marks in the design, then run the Power Router again. Failures could still exist due to misalignment between power trunks and ports, congestion, and poor placement topology. If there are not too many failures fix the failed routes interactively. You may also leave the failures for successive routing to fix it later. 5.3 Routing Pin to Trunk

7 If the design has power trunks, invoke from the pull-down menus Pin to Trunk routing facility. The nets and the power rails are selected and setup to be routed. This will route most of the power pins that are aligned with the supply trunks. Unrouted pins will be routed later. 5.4 Protect pre-routes All the current wiring done so far, especially the power routes, should be set up to be protected so that CCAR will not over-ride these wires later. 5.5 Run CCAR do file All the three do files developed earlier should reside in the design area. Firstly, the Constraints.do file is executed. This will execute all the commands in sequence. This is followed by executing the Global.do file. After global routing, there should be few failures and a low number of violations. A high failure indicates possible blocked pins in which case these areas may need to be spaced out by manual placement. Run congestion analysis. If there are too many blocked pins, manual placement may be done to space out the block to block spacing. Re-run Global.do until a satisfactory result is achievied. Global route is a quick way to estimate detail routing success. If the global route is satisfactory, then chances are that the detail route will be good. Next the Route.do file is executed. Detail route takes much longer time than global route. At the end of the route, errors are highlighted in CCAR. These errors can be de-bugged to find out if these are clearance, crossover, endcap or other violations. Route errors could be fixed interactively or by entering syntax in the CCAR command line. CCAR provides point to point DRC correct interactive routing capability. Some more global route passes could be done at the command line. To enhance the route completion, the placement of some blocks or devices could be changed to enable the router to complete the routes. This is followed by detail routing passes. Once the route is done the CCAR tool provides information on the existing number of unconnects and the route completion percentage. The number of unconnects refer to the total number of nets not routed by CCAR. The completion field refers to the percentage of the completed routes in relation to the total nets to be routed. If the do file is setup right and the design placement is not too congested the route completion rate should be good. Especially for large designs if a high percentage of the routes could be automated, this would save a lot of layout design cycle time and improve productivity. 5.6 Import to VXL Once routing is complete in CCAR, the design is saved and imported back into VXL. In VXL further clean up may be done if necessary. If more Engineering Change Order(ECO) changes are done to the design, the layout could be updated accordingly and then re-exported to CCAR for further wiring. After final routing, the design is imported back into VXL. These iterations can be done continuosly, in conjunction with physical

8 verification, until the designer is satisfied with the top level routing. This shoud result in the final optimal layout. 6.0 CONCLUSION The flows, setup, and tools discussed are vital in accelerating the detailed task of chip level routing and design. This is complemented by the advanced pcells, technology files for several tools discussed, and a customized CAD environment maintained by the CAD group. Going forward there could be some enhancements. The possible enhancements include a) an integrated Floorplanner for mixed-signal designs to estimate characteristics of the final layout b) a more advanced Compaction tool for block level compaction c) more flexibility for interactive edits in CCAR such as manually inserting via arrays and d) layout editing capabilities within CCAR to limit import and export to VXL. This methodology and flow will no doubt improve the time to market and productivity. Currently the goal is to automate about 70% percent of the routing data preparation and the chip level routing. With this automation and possible future tool enhancements the layout design cycle time can be shortened, and in effect the final layout and productivity can be improved tremendously. REFERENCES [1] Aurangzeb Khan, Recent Developments in High-Performance System-on-Chip IC Design, 2004 International Conference on IC Design and Technology, May [2] Neocell User Guide, Product Version 3.4, Cadence Design Systems Incorporated, May [3] Rami Ahola, Daniel Wallner, Marius Sida, Avi Gupta, Bluetooth Transceiver Design: A Top-Down Flow for Complex RF Mixed-Signal ICs, Mentor Graphics Technical Publication, February [4] Sravasti Nair, Randy Bishop, Mike Fang, Daniel Houlihan, Susan Zhang, A Design Rule Driven Editing Environment in Virtuoso, International Cadence Usersgroup Conference, September [5] Ernie Koeroghlian, Avi Gupta, Addressing the Layout Challenges of Increasing Analog Content in SoCs, Mentor Graphics Deep Submicron Technical Publication, July [6] Virtuoso XL Layout Editor User Guide, Product Version 5.0, Cadence Design Systems Incorporated, 2003.

9 [7] IC Shape-Based Technology Chip Assembly User Guide, Product Version , Cadence Design Systems Incorporated, [8] Manfred Henning, Juergen Scheible, Kurt Liebermann, Thomas Dilling, Cambio Interactive compaction of mixed signal layout with the IC-Station, Mentor Graphics IC Design Technical Forum, September [9] Andy Tran, Jason Chen, Analog/Mixed-Signal Layout Acceleration, National Semiconductor Technology Bridge Conference, February [10] Adel S. Sedra, Kenneth C. Smith, Microelectronic Circuits, 3 rd Edition, 1990